CN109599440A - Stressed channels transistor and its manufacturing method - Google Patents
Stressed channels transistor and its manufacturing method Download PDFInfo
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- CN109599440A CN109599440A CN201811477083.8A CN201811477083A CN109599440A CN 109599440 A CN109599440 A CN 109599440A CN 201811477083 A CN201811477083 A CN 201811477083A CN 109599440 A CN109599440 A CN 109599440A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 39
- 239000001257 hydrogen Substances 0.000 claims abstract description 39
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000007711 solidification Methods 0.000 claims abstract description 6
- 230000008023 solidification Effects 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 230000003068 static effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 118
- 239000010408 film Substances 0.000 description 28
- 230000000903 blocking effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of stressed channels transistors, comprising: gate structure, side wall, source-drain area and channel region.CESL layers be covered on source region, drain region, gate structure the side of side wall and the top surface of polysilicon gate on, CESL layers include using SiN film composition buffer layer and stress provide layer.Stress provide the SiN film of layer H content it is high and after SiN film deposition include hydrogen release process and hydrogen release put after realize the solidification of SiN film and thereby realize the adjusting to the stress of channel region, buffer layer stops the H in hydrogen release process to spread to source region, drain region and channel region, to promote the electric property of device.The invention also discloses a kind of manufacturing methods of stressed channels transistor.The present invention can realize the strain transmitting to channel region using the SiN film of CESL and the hydrogen that can prevent the hydrogen release of SiN film from putting is diffused into channel region and source region and drain region, so as to improve the static leakage performance of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, in particular to a kind of stressed channels transistor；The present invention is also
It is related to a kind of manufacturing method of stressed channels transistor.
Background technique
Stressed channels transistor is widely studied in integrated circuit industry, is utilized contact etching stop layer (CESL)
Stretching (Tensile) SiN technology, can significantly improve the carrier mobility of channel, to improve the performance of device, into
And the constantly size of miniature transistor, realize more massive integrated level；CESL such as can be usually used in 28LP technique
The strain gauge technique of layer.28LP technique is corresponding low-power consumption (Low power, LP) technique in 28nm process node.
As shown in Figure 1, being the structure chart of existing stressed channels transistor, CESL layers are used in structure shown in FIG. 1
SiN processing procedure realizes stress transfer to channel, and existing stressed channels transistor includes:
Semiconductor substrate such as silicon substrate 101 is formed with gate structure, gate structure packet on the surface of semiconductor substrate 101
Gate dielectric layer such as gate oxide 102 and polysilicon gate 103 are included, is also formed with side wall in the side of polysilicon gate 103, in Fig. 1, side
Wall includes oxide layer side wall 104a and silicon nitride spacer 104b.
The region of the semiconductor substrate 101 covered by polysilicon gate 103 is channel region, and can be greater than threshold in grid voltage
Channel is formed on the surface of channel region when threshold voltage.
Active area 107a and drain region 107b is formed on the surface of the semiconductor substrate 101 of 103 left and right sides of polysilicon gate.
CESL layer 104 is covered on the side of the side wall of the side of source region 107a, drain region 107b, polysilicon gate 103 and more
The top surface of crystal silicon grid 103.
CESL layer 104 is to deposit to be formed after source region 107a and drain region 107b is formed, and is using stretching (Tensile)
SiN process deposits are formed, this SiN film H content with higher for stretching SiN technique and being formed, and thickness is about
SiN film deposition after, it is subsequent generally use ultraviolet light (UV) irradiation ultraviolet exposure processing realize hydrogen release put,
It is to put hydrogen release extra in SiN film that hydrogen release, which is put, and SiN thin film densification is finally made to solidify (Curing).In the solidification of SiN
It can generate in the process miniature and (compress) process can be compressed to the polysilicon gate 103 and side wall that it is coated, it is compressed
The stress (Strain) of the SiN film of journey meeting CESL layer 104 is transmitted in channel, is realized the strain of channel, is kept mobility significant
It is promoted.
Existing device can effectively be transmitted to the Strain of CESL layer 104 in channel, but in CESL layer 104
During Tensile SiN is realized, it is necessary to first deposit the highly concentrated SiN film containing H, this SiN film can directly and polysilicon
Grid 103 and side wall and source region 107a and drain region 107b contact, during contraction (shrinkage) of SiN film, H is continuous
Ground in escaping into environment, meanwhile, H from the interface of polysilicon gate 103 and side wall and source region 107a and drain region 107b spread
To channel, the H concentration of channel is promoted, the antistatic property of device is caused to decline.In Fig. 1, indicated with stain 201 in SiN film
In H, arrow 202 indicate during hydrogen release is put hydrogen diffusion direction, it can be seen that hydrogen finally can be to the direction of channel region
Diffusion, to will affect channel and also affect source region 107a and drain region 107b.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of stressed channels transistors, can use the SiN film of CESL
It realizes the strain transmitting to channel region and the hydrogen that can prevent the hydrogen release of SiN film from putting is diffused into channel region and source region and drain region
In, so as to improve the static leakage performance of device.For this purpose, the present invention also provides a kind of manufacturers of stressed channels transistor
Method.
In order to solve the above technical problems, stressed channels transistor provided by the invention includes:
Gate structure is formed by stacking, described more by the gate dielectric layer and polysilicon gate that are formed in semiconductor substrate surface
The side of crystal silicon grid is formed with side wall.
Channel region is formed with by the surface for the semiconductor substrate that the polysilicon gate is covered.
Source region and drain region autoregistration are formed in the semiconductor substrate surface of the gate structure two sides.
CESL layers be covered on the source region, the drain region, the gate structure the side wall side and the polycrystalline
On the top surface of Si-gate, described CESL layers includes that the buffer layer being sequentially overlapped and stress provide layer.
The buffer layer and the stress provide layer and SiN film are all used to form, and the SiN of the buffer layer after deposit is thin
The H content of film provides the H content of the SiN film of layer lower than the stress, and the stress provides layer and also carries out hydrogen release after deposition
It puts technique to be solidified, the stress provides layer and forms stress after hardening and be transmitted in the channel region and thereby adjust institute
State the carrier mobility of channel region.
Described CESL layers by the buffer layer and the source region, the drain region, the gate structure the side wall
The top surface of side and the polysilicon gate contacts and passes through the H in the buffer layer blocking hydrogen release process to the source
Area, the drain region and channel region diffusion, to promote the electric property of device.
A further improvement is that the semiconductor substrate is silicon substrate；The material of the gate dielectric layer is silica；It is described
The material of side wall includes silicon oxide or silicon nitride.
A further improvement is that the buffer layer is formed using pecvd process.
A further improvement is that the hydrogen release process is realized using ultraviolet exposure processing.
A further improvement is that the buffer layer with a thickness ofThe stress provide layer with a thickness of
A further improvement is that it is tensile stress that the stress, which provides the stress that layer provides, the stressed channels transistor is
NMOS tube.
A further improvement is that the stressed channels transistor is the device of 28LP technique.
A further improvement is that being also formed with interlayer film, contact hole, by front metal layer shape on CESL layers of the surface
At source electrode, drain and gate, the source electrode connects the source region by corresponding contact hole, and the drain electrode is connect by corresponding
Contact hole connects the drain region, and the grid connects the polysilicon gate by corresponding contact hole.
In order to solve the above technical problems, the manufacturing method of stressed channels transistor provided by the invention includes the following steps:
Step 1: providing semi-conductive substrate, channel region, gate structure, source are formed in the semiconductor substrate surface
Area and drain region.
The gate structure is formed by stacking by the gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface, described
The side of polysilicon gate is formed with side wall.
The channel region is formed in the surface of the semiconductor substrate covered by the polysilicon gate.
The source region and the drain region autoregistration are formed in the semiconductor substrate surface of the gate structure two sides.
Step 2: sequentially forming CESL layers of buffer layer and stress offer layer, provided by the buffer layer and the stress
Layer superposition made of described CESL layers be covered on the source region, the drain region, the gate structure the side wall side and
On the top surface of the polysilicon gate.
The buffer layer and the stress provide layer and SiN film are all used to form, and the SiN of the buffer layer after deposit is thin
The H content of film provides the H content of the SiN film of layer lower than the stress.
The solidification of layer is provided to the stress Step 3: carrying out the realization of hydrogen release process, the stress provides layer and solidifying
Stress is formed afterwards and is transmitted in the channel region and thereby adjusts the carrier mobility of the channel region.
Described CESL layers by the buffer layer and the source region, the drain region, the gate structure the side wall
The top surface of side and the polysilicon gate contacts and passes through the H in the buffer layer blocking hydrogen release process to the source
Area, the drain region and channel region diffusion, to promote the electric property of device.
A further improvement is that the semiconductor substrate is silicon substrate；The material of the gate dielectric layer is silica；It is described
The material of side wall includes silicon oxide or silicon nitride.
A further improvement is that buffer layer described in step 2 is formed using pecvd process.
A further improvement is that hydrogen release process described in step 3 is realized using ultraviolet exposure processing.
A further improvement is that the buffer layer with a thickness ofThe stress provide layer with a thickness of
A further improvement is that it is tensile stress that the stress, which provides the stress that layer provides, the stressed channels transistor is
NMOS tube.
A further improvement is that the stressed channels transistor is the device of 28LP technique.
The present invention realizes the channel block transitive stress for using CESL layers as device, so as to improve moving for channel carrier
Shifting rate improves the electric property of device.
Meanwhile the present invention is provided with buffer layer in CESL layers, and stress is arranged again after buffer layer formation and provides layer, this
The buffer layer of invention can be realized well provides hydrogen Xiang Yuanqu, drain region, polysilicon gate and the side wall diffusion of layer release to stress, from
And hydrogen can be prevented to be diffused into source region, drain region and channel, from static leakage (IDDQ) performance that can improve device, so as to be promoted
The electric property of device.
In addition, buffer layer of the invention and stress, which provide layer, all uses SiN film, buffer layer and stress can be made to provide layer very
Good compatibility.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structure chart of existing stressed channels transistor；
Fig. 2 is the structure chart of stressed channels transistor of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the structure chart of stressed channels transistor of the embodiment of the present invention, stressed channels of the embodiment of the present invention are brilliant
Body pipe includes:
Gate structure is formed by stacking, described by the gate dielectric layer 2 and polysilicon gate 3 that are formed in 1 surface of semiconductor substrate
The side of polysilicon gate 3 is formed with side wall.
The semiconductor substrate 1 is silicon substrate；The material of the gate dielectric layer 2 is silica；The material packet of the side wall
Silicon oxide or silicon nitride is included, monox lateral wall indicates that silicon nitride spacer is indicated in Fig. 2 with label 4b in Fig. 2 with 4a label.
Channel region is formed with by the surface for the semiconductor substrate 1 that the polysilicon gate 3 is covered.
Source region 7a and drain region 7b autoregistration are formed in 1 surface of the semiconductor substrate of the gate structure two sides.
CESL layer 5 is covered on the source region 7a, the drain region 7b, the side of the side wall of the gate structure and described
On the top surface of polysilicon gate 3, the CESL layer 5 includes that the buffer layer 5a being sequentially overlapped and stress provide layer 5b.
The buffer layer 5a and the stress provide layer 5b and SiN film are all used to form, the buffer layer 5a after deposit
SiN film H content provided lower than the stress layer 5b SiN film H content, the stress provides layer 5b after deposition
It also carries out hydrogen release process to be solidified, the stress provides layer 5b and forms stress after hardening and be transmitted in the channel region
And thereby adjust the carrier mobility of the channel region.The CESL layer 5 passes through the buffer layer 5a and the source region 7a, institute
Drain region 7b, the side of the side wall of the gate structure and the top surface of the polysilicon gate 3 is stated to contact and pass through described
Buffer layer 5a stops the H in hydrogen release process to spread to the source region 7a, the drain region 7b and the channel region, thus lifter
The electric property of part.Using the hydrogen in the expression SiN film of stain 301 in Fig. 2, the hydrogen during the expression hydrogen release of arrow 302 is put expands
Dissipate direction.As can be seen that the buffer layer 5a blocks expansion of the hydrogen into the source region 7a, the drain region 7b and the channel region
It dissipates.
In the embodiment of the present invention, the buffer layer 5a is formed using pecvd process.
The hydrogen release process is realized using ultraviolet exposure processing.
The buffer layer 5a with a thickness ofThe stress provide layer 5b with a thickness of
It is tensile stress that the stress, which provides the stress that layer 5b is provided, and the stressed channels transistor is NMOS tube.
The stressed channels transistor is the device of 28LP technique.
Interlayer film 6, contact hole, the source electrode formed by front metal layer, drain electrode are also formed on the surface of the CESL layer 5
And grid, the source electrode connect the source region 7a by corresponding contact hole, the drain electrode connects institute by corresponding contact hole
Drain region 7b is stated, the grid connects the polysilicon gate 3 by corresponding contact hole.
The embodiment of the present invention realizes the channel block transitive stress for using CESL layer 5 as device, carries so as to improve channel
The mobility for flowing son, improves the electric property of device.
Meanwhile the embodiment of the present invention is provided with buffer layer 5a in CESL layer 5, is arranged again after buffer layer 5a formation and answers
Power provide layer 5b, buffer layer 5a of the invention can realize well to stress provide layer 5b release hydrogen to source region 7a, drain region 7b,
Polysilicon gate 3 and side wall diffusion, so as to prevent hydrogen to be diffused into source region 7a, drain region 7b and channel, from the quiet of device can be improved
State electric leakage (IDDQ) performance, so as to promote the electric property of device.
In addition, the embodiment of the present invention buffer layer 5a and stress provide layer 5b all use SiN film, can make buffer layer 5a and
Stress provides layer 5b and is compatible with well.
The manufacturing method of stressed channels transistor of the embodiment of the present invention includes the following steps:
Step 1: provide semi-conductive substrate 1,1 surface of semiconductor substrate be formed with channel region, gate structure,
Source region 7a and drain region 7b.
The gate structure is formed by stacking by the gate dielectric layer 2 and polysilicon gate 3 for being formed in 1 surface of semiconductor substrate,
The side of the polysilicon gate 3 is formed with side wall.
The channel region is formed in the surface of the semiconductor substrate 1 covered by the polysilicon gate 3.
The source region 7a and the drain region 7b autoregistration are formed in 1 table of the semiconductor substrate of the gate structure two sides
Face.
In present invention method, the semiconductor substrate 1 is silicon substrate；The material of the gate dielectric layer 2 is oxidation
Silicon；The material of the side wall includes silicon oxide or silicon nitride, and monox lateral wall is indicated in Fig. 2 with 4a label, silicon nitride spacer
It is indicated in Fig. 2 with label 4b.
Step 2: sequentially forming the buffer layer 5a of CESL layer 5 and stress provides layer 5b, by the buffer layer 5a and described answer
Power provide the CESL layer 5 that is formed by stacking of layer 5b be covered on the source region 7a, the drain region 7b, the gate structure it is described
On the top surface of the side of side wall and the polysilicon gate 3.
The buffer layer 5a and the stress provide layer 5b and SiN film are all used to form, the buffer layer 5a after deposit
SiN film H content lower than the stress provide layer 5b SiN film H content.
The buffer layer 5a is formed using pecvd process.
The buffer layer 5a with a thickness of
The solidification of layer 5b is provided to the stress Step 3: carrying out the realization of hydrogen release process, the stress provides layer 5b and exists
Stress is formed after solidification and is transmitted in the channel region and thereby adjusts the carrier mobility of the channel region.
The hydrogen release process is realized using ultraviolet exposure processing.
The CESL layer 5 by the buffer layer 5a and source region 7a, the drain region 7b, the gate structure it is described
The top surface of the side of side wall and the polysilicon gate 3 contacts and passes through the H in the buffer layer 5a blocking hydrogen release process
It is spread to the source region 7a, the drain region 7b and the channel region, to promote the electric property of device.
It is tensile stress that the stress, which provides the stress that layer 5b is provided, and the stressed channels transistor is NMOS tube.
The stressed channels transistor is the device of 28LP technique.
Further include later the step of forming interlayer film 6, contact hole and front metal layer, and to the front metal layer into
The step of capable source electrode graphically formed, drain and gate, the source electrode pass through corresponding contact hole and connect the source region 7a, institute
It states drain electrode and the drain region 7b is connected by corresponding contact hole, the grid connects the polysilicon gate by corresponding contact hole
3。
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of stressed channels transistor characterized by comprising
Gate structure is formed by stacking, in the polysilicon by the gate dielectric layer and polysilicon gate that are formed in semiconductor substrate surface
The side of grid is formed with side wall；
Channel region is formed with by the surface for the semiconductor substrate that the polysilicon gate is covered；
Source region and drain region autoregistration are formed in the semiconductor substrate surface of the gate structure two sides；
CESL layers be covered on the source region, the drain region, the gate structure the side wall side and the polysilicon gate
Top surface on, described CESL layers includes that the buffer layer that is sequentially overlapped and stress provide layer；
The buffer layer and the stress provide layer and SiN film are all used to form, the SiN film of the buffer layer after deposit
H content provides the H content of the SiN film of layer lower than the stress, and the stress provides layer, and work is put in also progress hydrogen release after deposition
Skill is solidified, and the stress provides layer and forms stress after hardening and be transmitted in the channel region and thereby adjust the ditch
The carrier mobility in road area；
Described CESL layers by the buffer layer and the source region, the drain region, the gate structure the side wall side
It is contacted with the top surface of the polysilicon gate and stops the H in hydrogen release process to the source region, institute by the buffer layer
Drain region and channel region diffusion are stated, to promote the electric property of device.
2. stressed channels transistor as described in claim 1, it is characterised in that: the semiconductor substrate is silicon substrate；It is described
The material of gate dielectric layer is silica；The material of the side wall includes silicon oxide or silicon nitride.
3. stressed channels transistor as described in claim 1, it is characterised in that: the buffer layer is formed using pecvd process.
4. stressed channels transistor as described in claim 1, it is characterised in that: the hydrogen release process uses ultraviolet exposure
Processing is realized.
5. stressed channels transistor as described in claim 1, it is characterised in that: the buffer layer with a thickness of
The stress provide layer with a thickness of
6. stressed channels transistor as described in claim 1, it is characterised in that: it is that the stress, which provides the stress that layer provides,
Stress, the stressed channels transistor are NMOS tube.
7. stressed channels transistor as described in claim 1, it is characterised in that: the stressed channels transistor is 28LP technique
Device.
8. stressed channels transistor as described in claim 1, it is characterised in that: be also formed with layer on CESL layers of the surface
Between film, contact hole, the source electrode formed by front metal layer, drain and gate, the source electrode by corresponding contact hole connect institute
Source region is stated, the drain electrode connects the drain region by corresponding contact hole, and the grid passes through described in the connection of corresponding contact hole
Polysilicon gate.
9. a kind of manufacturing method of stressed channels transistor, which comprises the steps of:
Step 1: provide semi-conductive substrate, the semiconductor substrate surface be formed with channel region, gate structure, source region and
Drain region；
The gate structure is formed by stacking by the gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface, in the polycrystalline
The side of Si-gate is formed with side wall；
The channel region is formed in the surface of the semiconductor substrate covered by the polysilicon gate；
The source region and the drain region autoregistration are formed in the semiconductor substrate surface of the gate structure two sides；
Step 2: sequentially forming CESL layers of buffer layer and stress offer layer, stacking is provided by the buffer layer and the stress
The source region, the drain region, the side of the side wall of the gate structure and described are covered on for described CESL layers made of adding
On the top surface of polysilicon gate；
The buffer layer and the stress provide layer and SiN film are all used to form, the SiN film of the buffer layer after deposit
H content provides the H content of the SiN film of layer lower than the stress；
The solidification of layer is provided to the stress Step 3: carrying out the realization of hydrogen release process, the stress provides layer shape after hardening
At stress and it is transmitted in the channel region and thereby adjusts the carrier mobility of the channel region；
Described CESL layers by the buffer layer and the source region, the drain region, the gate structure the side wall side
It is contacted with the top surface of the polysilicon gate and stops the H in hydrogen release process to the source region, institute by the buffer layer
Drain region and channel region diffusion are stated, to promote the electric property of device.
10. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: the semiconductor substrate is
Silicon substrate；The material of the gate dielectric layer is silica；The material of the side wall includes silicon oxide or silicon nitride.
11. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: buffered described in step 2
Layer is formed using pecvd process.
12. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: hydrogen release described in step 3
Technique is put to realize using ultraviolet exposure processing.
13. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: the thickness of the buffer layer
ForThe stress provide layer with a thickness of
14. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: the stress provides layer and mentions
The stress of confession is tensile stress, and the stressed channels transistor is NMOS tube.
15. the manufacturing method of stressed channels transistor as claimed in claim 9, it is characterised in that: the stressed channels crystal
Pipe is the device of 28LP technique.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110211921A (en) * | 2019-05-23 | 2019-09-06 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090239344A1 (en) * | 2008-03-24 | 2009-09-24 | Samsung Electronics Co., Ltd. | Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance |
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| US20090239344A1 (en) * | 2008-03-24 | 2009-09-24 | Samsung Electronics Co., Ltd. | Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance |
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| CN110211921A (en) * | 2019-05-23 | 2019-09-06 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
| CN110211921B (en) * | 2019-05-23 | 2021-08-10 | 上海华力集成电路制造有限公司 | Method for manufacturing contact hole |
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