CN109597018A - Benchmark mutually examines the mutual detecting method of circuit, benchmark and electric energy computation chip - Google Patents
Benchmark mutually examines the mutual detecting method of circuit, benchmark and electric energy computation chip Download PDFInfo
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Abstract
It is related to benchmark and mutually examines the mutual detecting method of circuit, benchmark and electric energy computation chip, it includes: first voltage source, the first voltage-frequency conversion module, the first clock source and the first counter that benchmark, which mutually examines circuit,；Wherein, the first clock source exports the first reference frequency signal；First voltage-frequency conversion module is electrically connected at first voltage source, and the voltage signal that first voltage source exports is converted into the second reference frequency signal；First counter and the first voltage-frequency conversion module are electrically connected, and the first counter is also electrically connected with first clock source, calculate the proportionate relationship between the first reference frequency signal and the second reference frequency signal.
Description
Technical Field
The invention belongs to the field of voltage detection, and particularly relates to a double-reference mutual detection circuit, a double-reference mutual detection method and an electric energy metering chip.
Background
The voltage measurement in the circuit generally converts the voltage to be measured into a safe and directly measurable lower voltage signal through a voltage division circuit, and then realizes the measurement of the voltage to be measured through the acquisition of the lower voltage signal. In the measuring process, the performance of the voltage division circuit has great influence on the whole measuring precision.
In the field of intelligent electric meters, the metering accuracy and reliability are of great importance, and the metering accuracy and reliability are directly influenced by parameters of a voltage division circuit. In practical application, the parameters of the voltage divider circuit are easily changed under the influence of environmental factors such as temperature, large current, electromagnetic field and the like, so that voltage measurement errors are caused, and finally electric energy metering errors are caused.
In order to accurately measure the electric energy, a commonly used technique is to use a resistor as a voltage divider of a voltage dividing circuit, and inject a current signal into the voltage dividing circuit to detect parameters of the voltage dividing circuit. When the technology is used for detecting parameters of the voltage division circuit, the detection result is greatly influenced by the precision of the signal source output signal, and if the signal source output signal has larger deviation, the detection result is easy to generate errors.
Power metering devices typically require a clock reference source and a voltage/current reference source. The two reference sources have great influence on the result of electric energy metering, and the reference sources need to be detected in order to ensure the reliability of the equipment. The current commonly used technique is to use multiple clock sources to test each other and multiple voltage/current reference sources to test each other.
Disclosure of Invention
One embodiment of the present application provides a dual reference mutual detection circuit, including: the first voltage source, the first voltage-frequency conversion module, the first clock source and the first counter; wherein the first clock source outputs a first reference frequency signal; the first voltage-frequency conversion module is electrically connected to the first voltage source and converts a voltage signal output by the first voltage source into a second reference frequency signal; the first counter is electrically connected with the first voltage-frequency conversion module, the first counter is also electrically connected with the first clock source, and the first counter calculates the proportional relation between the first reference frequency signal and the second reference frequency signal.
In the double-reference mutual detection circuit, the voltage signal output by the first voltage source is converted into a second reference frequency signal through the first voltage-frequency conversion module, and the proportional relation between the first reference frequency and the second reference frequency is calculated through the first counter. And comparing the proportional relationship with an ideal value of the proportional relationship, and if the difference between the proportional relationship and the ideal value exceeds a first threshold value, judging that at least one of the first voltage source and the first clock source is abnormal.
In an electric energy metering device, a clock source and a voltage source are generally included, and both of them have a great influence on the accuracy of electric energy metering. By using the double-reference mutual detection circuit, mutual detection of the voltage source and the clock source can be realized on the premise of not attracting other reference sources.
Optionally, the first voltage source further comprises a first current source and a first ampere-volt conversion module; the first ampere-volt conversion module is electrically connected with the first current source and converts a current signal output by the first current source into a voltage signal to be output.
Through the double-reference mutual detection circuit, mutual detection of the current source and the clock source can be realized under the condition of not introducing other reference sources.
An embodiment of the present application further provides a dual-reference mutual inspection method, which is applied to the dual-reference mutual inspection circuit; a double-reference mutual detection method is applied to any one of the double-reference mutual detection circuits and is characterized by comprising the following steps of collecting a counting result of a counter; judging whether a reference source is abnormal or not, and judging that at least one of the first voltage source and the first clock source is abnormal when the deviation of the counting result and the ideal value of the counting result exceeds a first threshold value; otherwise, the first voltage source and the first clock source are judged to be normal.
In an electric energy metering device, a clock source and a voltage source are generally included, and both of them have a great influence on the accuracy of electric energy metering. By using the double-reference mutual detection method, the mutual detection of the voltage source and the clock source can be realized on the premise of not attracting other reference sources.
An embodiment of the present application further provides an electric energy metering chip, which includes one of the above dual-reference mutual detection circuits.
By packaging the double-reference mutual detection circuit in a chip, the reliability of the circuit is further improved while the function of the included circuit is realized, and meanwhile, the wiring area can be reduced.
Drawings
Fig. 1 is a schematic circuit diagram of a dual-reference mutual detection circuit a according to a first embodiment of the present application.
Fig. 2 is a schematic circuit diagram of a dual-reference mutual detection circuit B according to a second embodiment of the present application.
Fig. 3 is a schematic circuit diagram of a dual-reference mutual detection circuit C according to a third embodiment of the present application.
Fig. 4 is a schematic circuit diagram of a dual reference mutual detection circuit D according to a fourth embodiment of the present application.
Fig. 4A is a schematic diagram of an equivalent circuit principle of the dual reference mutual detection circuit D provided in the fourth embodiment of the present application when the operating power supply U1 operates alone.
Fig. 4B is a schematic diagram of an equivalent circuit principle of the dual-reference mutual detection circuit D provided in the fourth embodiment of the present application when the current source Iref operates alone.
Fig. 5 is a schematic flowchart of a dual-reference mutual inspection method E provided in a fifth embodiment of the present application.
Fig. 6 is a schematic flowchart of a dual-reference mutual inspection method F according to a sixth embodiment of the present application.
Fig. 7 is a schematic flow chart of a dual-reference mutual inspection method G according to a seventh embodiment of the present application.
Fig. 8 is a schematic flow chart of a double-benchmark mutual inspection method H according to an eighth embodiment of the present application.
Detailed Description
The embodiments disclosed in the present invention are described below with reference to specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure in the present specification regarding "detecting circuit and method for voltage divider circuit, reference mutual detecting circuit and electric energy metering chip". The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. The drawings of the present invention are for illustrative purposes only and are not drawn to scale. The following embodiments will further explain the technical contents related to the present invention in detail, but the disclosure is not intended to limit the technical scope of the present invention.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements or signals, etc., these elements or signals should not be limited by these terms. These terms are used to distinguish one element from another element, or from one signal to another signal. In addition, as used herein, the term "or" may include all combinations of any one or more of the associated listed items as appropriate.
As shown in fig. 1, a dual reference cross-checking circuit a is a first embodiment provided in the present application. The double-reference mutual detection circuit A comprises: a voltage source P1, a clock source P2, a voltage-to-frequency conversion module P3 and a counter P4.
As shown in fig. 1, the voltage-to-frequency conversion module P3 is electrically connected to a voltage source P1, and converts a voltage signal U2 output by the voltage source P1 into a frequency signal f2 in proportion. Assuming that k is the conversion coefficient of the voltage-to-frequency conversion module P3, f2 is k × U2. The counter P4 is a counter that can count up an edge. The counting control pin, such as the counting reset pin, is electrically connected to the voltage-to-frequency conversion module P3. The counting input pin of the counter P4 is electrically connected to the clock source P2.
When the frequency signal f2 is high, the counter P4 is in the count reset state, and the counter P4 output remains zero. When the frequency signal f2 is at low level, the counter P4 counts the number of rising edges of the frequency signal f1 from zero, and finishes counting when the rising edge of f2 arrives. As a result of the counting, the number of rising edges of f1 when f2 is at low level, that is, the number of f1 fluctuations within a half period of f2, that is, the count result S is f1/(2 × f2) ═ f1/(2 × f2 × U2). If the difference between the ideal values of counting results S and S exceeds a first threshold, it may be determined that at least one of voltage source P1 and clock source P2 is malfunctioning.
The circuit provided by the embodiment can also be connected in other ways. For example, the clock source P2 is connected to the count input pin of the counter P4, and the voltage-to-frequency conversion module P3 is connected to the other count control pins of the counter P4; for another example, the voltage-to-frequency conversion module P3 is connected to the count input pin of the counter P4, the clock source P2 is connected to the count control pin of the counter P4, and so on. The working principle is similar to that of the circuit, and the description is omitted.
In this embodiment, the counter P4 may also be a falling edge count, a double edge count or other counting method.
In this embodiment, latches or other logic devices may also be added to provide a richer, more reliable way of counting, and a more convenient way of data reading.
In this embodiment, the voltage source P1 may be a dc source or may be an ac source instead.
Through the embodiment, mutual detection of the voltage source and the clock source can be realized on the premise of not introducing other reference sources.
The double-reference mutual detection circuit A can further comprise a second voltage source, … … and an N1 voltage source, wherein N1 is a natural number which is greater than or equal to 2.
The nth 1 voltage source may further include an nth 1 current source and an nth 1 ampere-volt conversion module.
The dual reference cross checking circuit B may also include a second clock source, … …, and an N2 clock source, where N2 is a natural number greater than or equal to 2.
The mutual check of one or more clock sources and one or more voltage/current sources can be realized without introducing a new reference source.
Fig. 2 is a diagram of a dual reference cross-checking circuit B according to a second embodiment of the present application. The circuit includes: the device comprises a voltage source P1, a clock source P2, a voltage-frequency conversion module P3, a counter P4, a frequency divider P7 and a phase-locked loop P8.
As shown in fig. 2, the voltage source P1 outputs a dc reference voltage signal with a voltage of U2, which can be used as a voltage reference for AD sampling, assuming that U2 is 2.5V. The clock source P2 outputs a reference clock signal with frequency f1, which can be used as a time reference for the timing start of AD sampling or power calculation, assuming that f1 is 12800 Hz.
As shown in fig. 2, the voltage-to-frequency conversion module P3 is electrically connected to the voltage source P1, and converts the voltage signal output by the voltage source P1 into the frequency signal f 2. Assuming that the conversion coefficient k of the voltage-to-frequency conversion module P3 is 600Hz/V, in an ideal case, f2 is 2.5 × 600 is 1500 Hz.
The divider P7 and the phase locked loop P8 are frequency converters, in which the divider P7 may lower the frequency and the phase locked loop P8 may raise the frequency. As shown in fig. 2, the frequency divider P7 is electrically connected to the voltage-to-frequency conversion module P3, and down-converts the frequency signal into a frequency signal f22 according to a ratio. Assuming that the down-conversion ratio of the frequency divider P7 is 1024, in an ideal case, f22 is 1500/1024 is 1.46484375 Hz. As shown in fig. 2, the pll P8 is electrically connected to the clock source P2, and the frequency of the reference clock signal output by the clock source P2 is scaled up, and assuming that the scaling of the up-conversion of P8 is 8, ideally, the frequency f11 of the output signal of the pll P8 is 12800 × 8 — 102400 Hz.
As shown in fig. 3, counter P4 is a 16-bit edge counter. The count input pin CP of the counter P4 is connected to the phase-locked loop P8, and the count mode is a rising edge count. The count reset RST pin of the counter P4 is connected to the frequency divider P7. when f11 is high, the count output pin of the counter is in reset state, B [15:0] is kept to zero; when f11 is low, B [15:0] counts from zero. In this connection, the final count result of the counter P4 is the number of rising edges of f11 in the half cycle of f 22.
Ideally, the counting result B [15:0] ═ f22 ÷ (f11 × 2) ≈ 34952.5, i.e., the ideal counting result is between 34952 to 34953. Assuming that the first threshold is 3, when the counting result is not between 34950 ~ 34955, it can be determined that at least one of the voltage source P1 and the clock source P2 is abnormal, i.e. the mutual detection of the voltage source P1 and the clock source P2 is realized. In the ideal case of the voltage-to-frequency conversion module P3, the detection error is less than ± 0.01%.
A latch may also be included on the count output pins B [15:0] of counter P4 to hold the count result of counter P4 for easy data reading.
In this embodiment, the counter P4 may be replaced by a counter with higher calculation accuracy to improve the detection accuracy, such as 20 bits or 24 bits, and will not be described herein again.
The double-reference mutual detection circuit B can also be connected in other modes. For example, the phase locked loop P8 is connected to the CP pin of the counter P4, and the divider P7 is connected to the other count control pin of the counter P4. The dual reference cross-checking circuit B may also include logic circuitry to provide a richer, more reliable way of counting.
As shown in fig. 2, the frequency divider P7 in the dual reference cross detection circuit B may be eliminated, and instead, the voltage-to-frequency conversion module P3 is directly connected to the counter P4.
As shown in fig. 2, the phase-locked loop P8 in the dual reference cross checking circuit B can be removed, and instead, the clock source P2 is directly connected to the counter P4.
As shown in fig. 2, the dual reference cross-checking circuit B may be further configured such that the clock source P2 is connected to the frequency divider P7.
As shown in FIG. 2, the dual reference mutual detection circuit B may be a voltage-to-frequency conversion module P3 connected to the PLL P8
In this embodiment, the counter P4 may also be a falling edge count, a double edge count or other counting method. The count period of the counter P4 may be a half cycle in which f11 is at a high level, a half cycle in which f11 is at a low level, or one cycle of f 11. And other equivalent variations, are discussed in detail herein.
As shown in fig. 3, a dual reference cross check circuit C is provided as a second embodiment of the present application. The mutual detection circuit comprises: the device comprises a current source P5, an ampere-volt conversion module P6, a voltage-frequency conversion module P3 and a counter P4.
The ampere-volt conversion module P6 is electrically connected to the current source P5, and converts the current output by the current source P5 into a voltage signal for output. The current source P5 and the ampere-volt switching module P6 are equivalent to one voltage source. The ampere-volt conversion module P6 is electrically connected with the voltage-frequency conversion module P3. The principle of the double-reference mutual detection circuit C is similar to that of the double-reference mutual detection circuit a, and the details are not repeated herein.
The current source P5 in the dual reference cross-checking circuit C may be a dc current source or an ac current source.
The voltage converting module P6 in the dual reference mutual detection circuit C may be a resistor, a hall current sensor or other circuit unit capable of converting a current signal into a voltage signal. The circuit unit includes an electronic device, a circuit, and an electronic apparatus.
Through the double-reference mutual detection circuit C, mutual detection of the current source and the clock source can be realized on the premise of not introducing other reference sources.
As shown in fig. 4, a fourth embodiment provided by the present application is a dual reference mutual detection circuit D. The double-reference mutual detection circuit D comprises: the circuit comprises an operating power supply U1, a load ZL, a resistor R1, a resistor R2, a resistor R4, a current source Iref, a signal processing unit 22, a clock source P2, a voltage-frequency conversion module P3, a frequency divider P5 and a counter P4.
The resistor R4 is an ampere-volt conversion module, and converts the current signal output by the current source Iref into a voltage signal. The resistor R4, the clock source P2, the voltage-frequency conversion module P3, the frequency divider P5 and the counter P4 form a local circuit, the local circuit can realize mutual detection of the current source Iref and the clock source P2, the working principle of the local circuit is the same as that of the double-reference mutual detection circuit C, and details are not repeated here.
As shown in fig. 4, the operating power supply U1 is an ac voltage source that supplies power to the load ZL. The load ZL is electrically connected to two ends of the operating power supply U1. The voltage to be measured is the voltage across the load ZL, which is equal to the voltage of the operating power supply U1 in fig. 4. The circuit under test (not shown) includes an operating power supply U1, a load ZL, and wiring therebetween. The operating frequency is a frequency included in the frequency component of the output voltage signal of the U1 in the normal operation.
As shown in fig. 4, the current source Iref can output a first frequency detection signal operating at a first frequency. Wherein the first frequency is not equal to the integral multiple of the working frequency. If the circuit to be tested comprises a plurality of working frequencies when the circuit to be tested works normally, the first frequency is not equal to the integral multiple of each working frequency.
As shown in fig. 4, the resistor R1 and the resistor R2 are respectively a first voltage divider and a second voltage divider, which are connected in series to form a voltage dividing circuit and electrically connected across two ends of the load ZL. The resistor R4 is electrically connected to the connection point of the resistor R1 and the resistor R2, and injects the current outputted by the current source Iref into the voltage dividing circuit formed by the resistor R1 and the resistor R2. By measuring the voltage across the resistor R2, whether the parameters of the voltage division circuit are normal can be judged. The signal processing unit 22 is electrically connected to the resistor R2 and the resistor R4, and collects and analyzes the voltage signals at the two ends of the resistor R2 and the voltage signals at the two ends of the resistor R4.
As shown in fig. 4A, an equivalent circuit when the operating power supply U1 operates alone can obtain:
UR2a＝U1×R2/(R1+R2) (1)
as shown in fig. 4B, an equivalent circuit when the current source Iref operates alone can obtain:
UR2b＝Iref×R1×R2/(R1+R2) (2)
the actual voltage Uo across R2 according to the principle of power superposition is:
Uo＝UR2a+UR2b＝U1×R2/(R1+R2)+Iref×R1×R2/(R1+R2) (3)
wherein U isR2aIs configured to include only the operating frequency, UR2bIs the same as the frequency configuration of the current source Iref. When the current source Iref outputs the first frequency detection signal, UR2bOnly the first frequency. Uo is collected and frequency analysis is carried out, so that a working frequency component, namely U, only containing working frequency can be obtainedR2aA measured value of (a); and a first frequency component containing only the first frequency, i.e. UR2bIs measured. The operating frequency component can be used as a measured value of the voltage to be measured for voltage detection, electric energy metering and the like. First frequency component and UR2bComparing the ideal values, and judging that the parameters of the voltage division circuit are abnormal if the difference exceeds a second threshold value, wherein the parameters of the voltage division circuit comprise the resistance values of R1 and R2 and the parameters of parasitic circuits thereof.
As shown in fig. 4, the operating power source U1 is an ac voltage source, which may be replaced by a dc source. The operating power supply U1 may also be replaced by a current source or a combination of various active devices.
The load ZL may be a resistor, which may also be a combination of resistive, capacitive and inductive devices, or even a plurality of passive devices.
The circuit under test (not shown) may be replaced by a circuit network of one or more active devices and one or more passive devices. The corresponding voltage to be measured may be the voltage between any two nodes in the circuit network. The voltage divider is connected across the two nodes.
As shown in fig. 4, the current source Iref and the resistor R4 can be replaced by a voltage source.
As shown in fig. 4, the voltage divider circuit is formed by connecting a resistor R1 and a resistor R2 in series, wherein R1 and R2 are a first voltage divider and a second voltage divider, respectively. The first voltage divider and the second voltage divider may also be replaced by resistive, inductive or capacitive devices, or a combination of the above. The voltage dividing circuit may further include a third voltage divider, … …, an Mth voltage divider, where M is a natural number not less than 3. Wherein the Mth voltage divider is a resistive device, an inductive device, or a capacitive device, or a combination thereof.
As shown in fig. 4, the resistor R4 is an ampere-volt switching module. The resistor R4 may be replaced by other resistor type current sensors, current transformers, hall current sensors, or other modules that can be used to detect current. The module includes circuitry, electronics, and electrical equipment.
Further, the current source Iref may further output a second frequency signal operating at a second frequency, … …, and an nth frequency signal operating at an nth frequency, where N is a natural number not less than 2. Wherein the second frequency is not equal to the integer multiple of the operating frequency. If the circuit to be tested comprises a plurality of working frequencies when working normally, the second frequency is not equal to the integral multiple of each working frequency; the nth frequency is not equal to an integer multiple of the operating frequency. If the circuit to be tested comprises a plurality of working frequencies when the circuit to be tested works normally, the Nth frequency is not equal to the integral multiple of each working frequency.
It should be noted that the signal processing unit 22 may be eliminated from the dual reference mutual detection circuit and replaced by an external circuit or device having the same function.
As shown in fig. 4B, when the current source Iref operates alone, the load ZL is in a short-circuit state, that is, the dual-reference mutual detection circuit D of the embodiment does not affect the normal operation of the circuit to be tested (not shown). Because the working frequency component and the first frequency component can be sufficiently separated in a frequency analysis mode, the double-reference mutual detection circuit D can not influence the measurement of the voltage while detecting the parameters of the voltage division circuit.
As shown in fig. 5, a fifth embodiment, a dual reference mutual inspection method E, is provided. The double-reference mutual detection circuit is applied to any one of the double-reference mutual detection circuits and comprises the following steps.
In step S10, the count result of the counter is collected.
In step S20, the count result generated in step S10 is compared with the theoretical value of the count result.
And if the difference between the first voltage source and the second clock source exceeds a first threshold value, judging that at least one of the first voltage source and the first clock source is abnormal.
And if the difference between the counting result and the theoretical value of the counting result does not exceed a first threshold value, judging that the first voltage source and the first clock source are normal.
The mutual inspection of the clock source and the voltage source can be realized on the premise of not introducing a new reference source.
As shown in fig. 6, the present application provides a sixth embodiment, a dual-benchmark mutual inspection method F. The double-reference mutual detection circuit is applied to any one of the double-reference mutual detection circuits and comprises the following steps.
In step S10, the count result of the counter is collected.
In step S20, the count result generated in step S10 is compared with the theoretical value of the count result.
And if the difference between the first current source and the second current source exceeds a first threshold value, judging that at least one of the first current source and the first clock source is abnormal.
And if the difference between the counting result and the theoretical value of the counting result does not exceed a first threshold value, judging that the first current source and the first clock source are normal.
The mutual inspection of the clock source and the current source can be realized on the premise of not introducing a new reference source.
As shown in fig. 7, the present application provides a seventh embodiment, a dual reference mutual inspection method G. The dual-reference mutual detection circuit D applied to the fourth embodiment provided in the present application includes the following steps.
In S10, the first current source is controlled to output the first frequency detection signal.
In S20, the first current source is cross-checked with the first clock source.
S30, if the first current source or the first clock source is abnormal in the detection result of step S20, go to S60, otherwise go to S40.
And S40, acquiring voltage signals at two ends of the second voltage divider, and performing frequency analysis to obtain a first frequency component.
And S50, if the deviation between the first frequency component and the ideal value of the first frequency component exceeds a second threshold value, judging that the parameters of the voltage division circuit are abnormal, entering S60, and otherwise, exiting.
And S60, an exception handling step, alarming or correcting voltage measurement parameters.
For example, the online detection circuit provided by the embodiment of the application can be used in a 220V power frequency alternating current power grid. In this case, the operating frequency is 50Hz, and we can set the first frequency to 75 Hz. Since the noise frequency in the power grid is mainly concentrated on integral multiples of 50Hz, such as 150Hz and 250Hz, the 75Hz detection signal is less susceptible to interference.
First, the current source is controlled to output a 75Hz detection signal, which is assumed to be 10mA in magnitude.
Then, whether the detection signal output by the first current source is normal is judged by mutual detection of the first current source and the first clock source, and the detected content can include whether the amplitude of the detection current is 10mA, whether the frequency is 75Hz, whether the waveform is a sine wave, and the like.
If the current source output is detected to be abnormal, the method goes to an abnormal processing step
And collecting voltage signals at two ends of the second voltage divider, and analyzing the frequency to separate out 75Hz components from the collected results.
And then comparing the ideal value of the component with the ideal value of the component, if the difference between the ideal value and the ideal value exceeds a second threshold value, judging that the parameters of the voltage division circuit are abnormal, and otherwise, judging that the voltage division circuit is normal.
When the current source output is abnormal or the voltage division circuit parameters are abnormal, an abnormality processing step can be executed, and the measurement parameters can be corrected or an alarm can be given.
Wherein the first current source can be exchanged for the first voltage source.
By using the double-reference mutual detection method, the mutual detection of the voltage source and the clock source can be realized, and the online detection of the parameters of the voltage division circuit can be realized. The online detection method can not influence the normal work of the circuit to be detected and the voltage measurement circuit. Meanwhile, the online detection of the current source in the online detection circuit can be realized, so that the online detection result of the voltage division circuit is more reliable.
Wherein the first voltage source may be replaced by a first current source.
As shown in fig. 8, an eighth embodiment provided by the present application is a dual reference mutual detection circuit H. The dual-reference mutual detection circuit D applied to the fourth embodiment provided in the present application includes the following steps.
And S10, controlling the first current source to output the J-th frequency detection signal.
S20, detecting the first current source and the first clock source.
S30, if the first current source or the first clock source is abnormal in the detection result of step S20, go to step S60, otherwise go to step S40.
And S40, collecting voltage signals at two ends of the second voltage divider, and carrying out frequency analysis to obtain a J-th frequency component.
And S50, if the deviation between the J-th frequency component and the J-th frequency component ideal value does not exceed a second threshold value, judging that the J-th detection result of the voltage division circuit parameter is normal, otherwise, judging that the J-th detection result is abnormal.
And S60, an exception handling step, alarming or correcting voltage measurement parameters.
The above process is repeatedly executed by J to 1 to N, so that N detection results can be obtained, and the detection results can be mutually verified and supplemented, so that the detection result is accurate and reliable. Whether the voltage division circuit is normal or not can be comprehensively judged according to the N detection results, for example, most results are taken as final results. When the circuit to be detected has large interference, the detection result generated by some frequency signals may fail, and the detection result generated by other frequency signals can be used as the final detection result to ensure the normal operation of the system, so that the anti-interference capability of the detection method can be enhanced.
Wherein the first current source can be replaced by a first voltage source.
It should be noted that the processing method of the S60 exception handling step is not limited thereto, and the S60 exception handling step may be eliminated from the method and an external circuit or device may perform the relevant function instead.
An embodiment of the present application further provides an electric energy metering chip, which includes any one of the above dual-reference mutual detection circuits.
By solidifying the circuit in the chip, the function provided by the circuit can be realized, namely, the mutual detection function between the existing clock source and the voltage source or the mutual detection function between the clock source and the current source is realized on the premise of not introducing a new reference source. Meanwhile, the double-reference mutual detection circuit is solidified in the chip, so that the stability and the reliability of the circuit are further improved, and the wiring area of the circuit is further reduced.
The voltage/current source may be located outside the chip and electrically connected to the rest of the dual reference cross-point circuit.
The user can select a more suitable voltage/current source to connect to the chip according to actual needs, such as using a higher-precision voltage/current source for pursuing higher voltage/current reference precision, or using other external voltage/current sources independent of the chip for pursuing more flexible circuit topology.
The clock source can be arranged outside the chip and electrically connected with other parts of the online detection circuit.
A user may select a more suitable clock source to connect to the chip according to actual needs, for example, to pursue higher clock reference accuracy and adopt a higher-accuracy clock source, or to pursue a more flexible circuit topology and adopt other external clock sources independent of the chip.
Furthermore, the voltage-frequency conversion module/counter can be arranged outside the chip and electrically connected with other parts of the double-reference mutual detection circuit.
The user can select a more suitable voltage-to-frequency conversion module/counter to connect with the chip according to actual needs, for example, to pursue higher reference detection accuracy and use a higher accuracy voltage-to-frequency conversion module/counter, or to pursue a more flexible circuit topology and use other external voltage/current sources independent of the chip.
It should be noted that the embodiments described above with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention. It will be understood by those skilled in the art that various modifications and equivalent arrangements can be made without departing from the spirit and scope of the invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (12)
1. A dual reference mutual sensing circuit, comprising: the first voltage source, the first voltage-frequency conversion module, the first clock source and the first counter; wherein,
the first clock source outputs a first reference frequency signal;
the first voltage-frequency conversion module is electrically connected to the first voltage source and converts a voltage signal output by the first voltage source into a second reference frequency signal;
the first counter is electrically connected with the first voltage-frequency conversion module, the first counter is also electrically connected with the first clock source, and the first counter calculates the proportional relation between the first reference frequency signal and the second reference frequency signal.
2. The dual reference mutual sensing circuit of claim 1, wherein said first voltage source further comprises a first current source and a first volt conversion module; wherein,
the first ampere-volt conversion module is electrically connected with the first current source and converts a current signal output by the first current source into a voltage signal to be output.
3. The dual reference mutual sensing circuit of claim 1, further comprising a first frequency converter electrically connected to said first clock source, said first frequency converter further electrically connected to said first counter.
4. The dual reference mutual detection circuit of claim 1, further comprising a second frequency converter electrically connected to said first voltage to frequency conversion module, said second frequency converter further electrically connected to said first counter.
5. The dual reference mutual sensing circuit of claim 1, further comprising:
the voltage dividing circuit is electrically connected to the circuit to be detected, comprises a first voltage divider and a second voltage divider which are connected in series, converts voltages at two ends of the voltage dividing circuit into voltage signals at two ends of the second voltage divider through the first voltage divider and the second voltage divider, and is also electrically connected to the first voltage source;
the first voltage source outputs a detection signal, wherein the detection signal comprises a first frequency detection signal working at a first frequency;
the frequency contained in the circuit to be tested during normal work is the working frequency, and the first frequency is not equal to the integral multiple of the working frequency.
6. The dual reference mutual detection circuit of claim 5, further comprising a signal processing unit electrically connected to the first counter and electrically connected to two terminals of the second voltage divider for measuring and analyzing a voltage across the second voltage divider to obtain the first frequency component.
7. The dual reference mutual detection circuit of claim 5,
the voltage divider circuit further comprises at least one voltage divider connected in series with the first voltage divider and the second voltage divider.
8. The dual reference mutual detection circuit as claimed in claim 5, wherein the first current source further outputs an Nth detection frequency signal operating at an Nth frequency, N being a natural number not less than 2, wherein the N frequencies are different from each other and are not equal to integer multiples of the operating frequency.
9. A double-reference mutual detection method applied to the double-reference mutual detection circuit as claimed in claims 1-8, characterized by comprising the following steps
Judging the deviation of the counting result of the counter and an ideal value;
when the deviation exceeds a first threshold, determining that at least one of the first voltage source and the first clock source is abnormal or at least one of the first current source and the first clock source is abnormal;
otherwise, the first voltage source and the first clock source are determined to be normal or the first current source and the first clock source are determined to be normal.
10. The double-reference mutual detection method according to claim 9, applied to the double-reference mutual detection circuit according to any one of claims 6 to 9; the parameters of the voltage division circuit are parameters of devices contained in the voltage division circuit and parameters of a parasitic circuit of the voltage division circuit; the method is characterized by comprising the following steps:
detecting a first voltage source and a first clock source;
judging whether one of the first voltage source and the first clock source is abnormal or not or whether one of the first current source and the first clock source is abnormal or not according to the detection result;
if the judgment result is abnormal, quitting;
if the judgment result is normal, performing frequency analysis on the voltage signals at the two ends of the second voltage divider to obtain a first frequency component;
judging whether the deviation of the first frequency component from the ideal value of the first frequency component exceeds a second threshold value;
if the judgment result is yes, determining that the parameters of the voltage division circuit are abnormal;
and if the judgment result is negative, determining that the parameters of the voltage division circuit are normal.
11. An electric energy metering chip, characterized by comprising the double-reference mutual detection circuit of any one of claims 1 to 9.
12. The metering chip of claim 11, wherein at least one of the clock source and the first voltage source, the first current source, the voltage-to-frequency conversion module, and the counter is disposed outside the metering chip.
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