CN109587409B - Video processor self-adaptive cascade method, device and system - Google Patents
Video processor self-adaptive cascade method, device and system Download PDFInfo
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Abstract
The embodiment of the invention discloses a video processor self-adaptive cascade method, a device and a system. The signal cascade device sends a test data stream to the video processor end through a known output port, a video processor of the video processor end feeds back local identification information after receiving the test data stream, and the signal cascade device determines the corresponding relation between the known port of the signal cascade device and the video processor through the identification information of the video processor contained in the received data information, so that the configuration of the corresponding relation between the cascade channel scheduling logic and the physical wiring link is completed. According to the method and the device, manual configuration is not needed, the uniformity of the connection relation of the actual physical link and the logical relation of the system scheduling software is automatically detected, and the accuracy and the efficiency of the corresponding relation of the configuration cascade channel scheduling logic and the physical wiring link are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display of a splicing wall, in particular to a video processor self-adaptive cascade method, a device and a system.
Background
With the increasing demand of users on the screen display scale, the tiled wall display technology is applied and widely applied to control rooms and scheduling halls in various practical application scenes.
The spliced wall display system consists of a screen display spliced wall and a video processor, wherein the screen display spliced wall can be spliced by a small screen or a large screen, and can be spliced by a single screen or a pair of MxN whole screens; because the size of a tiled wall supported by a single video processor is limited, when a super-large-scale tiled wall needs to be supported, multiple video processors need to be cascaded, for example, please refer to the example block diagram shown in fig. 1, so as to implement the whole-wall roaming of a signal window.
When the display system of the tiled wall is configured, usually, engineering installation personnel correspondingly configure the actual physical connection link and the system configuration logic, for example, the port numbers of the physical links of the video processor 1# and the signal cascade device correspond to the system configuration logic relationship, and if the set port is not consistent with the actual physical link port, the signal cascade scheduling of the system is mistaken, and normal display cannot be performed.
However, when the size of the tiled wall display system is increased, the number of required video processors is increased, and the corresponding relationship between the scheduling logic of the configured cascaded channel and the physical link is very complicated, so that a large amount of time is wasted, and errors are easy to occur; furthermore, additional device commissioning time needs to be added.
Disclosure of Invention
The embodiment of the disclosure provides a video processor self-adaptive cascade method, a device and a system, which do not need manual configuration and effectively improve the accuracy and efficiency of configuring the corresponding relationship between cascade channel scheduling logic and physical wiring links.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
an embodiment of the present invention provides a video processor adaptive cascade method, based on a signal cascade device, including:
sending the test data stream to a video processor end through a first port;
acquiring data information sent by a target video processor in the video processor end, wherein the data information comprises identification information of the target video processor;
and determining the corresponding relation between the first port and the target video processor according to the data information so as to complete the configuration of the corresponding relation between the cascade channel scheduling logic and the physical wiring link.
Optionally, the determining, according to the data information, a correspondence between the first port and the target video processor includes:
after receiving the test data stream sent by the output end of the first port, a target video processor at the video processor end copies the test data stream added with the local identification information to an output port for outputting;
polling and detecting each input port, and determining a first input port with valid data, wherein the valid data is a test data stream carrying identification information of the target video processor, the input port and the output port;
and obtaining the corresponding relation between the output end of the first port of the signal cascade device and the input port of the target video processor, the first input port and the output port of the target video processor according to the effective data.
Optionally, obtaining the corresponding relationship between the first port output end of the signal cascade and the input port of the target video processor, the first input port, and the output port of the target video processor according to the valid data includes:
decoding the effective data to obtain the identification information of the target video processor;
and determining the corresponding relation between the output end of the first port and the input port of the target video processor and the corresponding relation between the output end of the target video processor and the output end of the first port according to the identification information.
Optionally, when the signal cascade device sends the test data stream through the first port, setting other ports other than the first port to be in a closed state, where the acquiring of the data information sent by the target video processor in the video processor includes:
and acquiring a response packet sent to the local area network by the target video processor from the local area network, wherein the response packet comprises the IP address information of the target video processor.
Optionally, the determining, according to the data information, a correspondence between the first port and the target video processor includes:
judging whether effective signals exist in each input channel or not;
if so, binding the first port with the target video processor;
the video processor end comprises a plurality of video processors with preset and unique IP address information; each video processor and each signal cascade device are respectively connected with the switch; and the target video processor is the video processor which receives the test data stream in the video processor end, and copies and loops out the received signal and sends a response packet to the local area network when the target video processor detects that the signal of the input port is effective.
The embodiment of the invention also provides a video processor self-adaptive cascade device, which is based on the signal cascade device and comprises the following components:
the data sending module is used for sending the test data stream to the video processor end through the first port;
a feedback data acquisition module, configured to acquire data information sent by a target video processor in the video processor, where the data information includes identification information of the target video processor;
and the corresponding relation setting module is used for determining the corresponding relation between the first port and the target video processor according to the data information so as to complete the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link.
The embodiment of the invention also provides a video processor self-adaptive cascade method, which is applied to the video processor and comprises the following steps:
receiving a test data stream sent by a signal cascade device through a first port output end;
adding local identification information to the test data stream to generate valid data;
copying the valid data to an output port and sending the valid data to the signal cascade device;
wherein the valid data carries input port information and the output port information for receiving the test data stream.
The embodiment of the invention also provides a video processor self-adaptive cascade method, which is based on the video processor and comprises the following steps:
judging whether the signal swing amplitude of the input port exceeds a preset threshold value or not;
if yes, copying the received signal data, and sending a response packet to the local area network for feeding back information of the received test data stream signal sent by the signal cascade device through the first port;
the signal cascade device and the video processor are respectively connected with the switch, and the video processor is provided with a preset and unique IP address; the response packet includes the IP address information of the target video processor.
The embodiment of the invention finally provides a video processor self-adaptive cascade system, which comprises a plurality of video processors with preset and unique IP address information, a switch and a signal cascade device; each video processor and the signal cascade are respectively connected with the switch so as to realize free access of each video processor and the signal cascade through a local area network;
the signal cascade device is used for sending a test data stream through a first port and setting other ports which are not the first port to be in a closed state; after receiving a response packet sent by a target video processor through a network, judging whether effective signals exist in each input channel, and if yes, binding the first port with the target video processor;
each video processor is used for copying and looping out received signal data when detecting that the signal of the input port is effective, and sending a response packet to the local area network.
Optionally, each video processor is configured to copy and loop out received signal data when detecting that the signal swing of the input port exceeds a preset threshold.
The technical scheme provided by the application has the advantages that the signal cascade device sends the test data stream to the video processor end through the known port, the video processor at the video processor end sends the data information capable of identifying the local information after receiving the test data stream, and the signal cascade device determines the corresponding relation between the known port of the signal cascade device and the video processor by receiving the identification information of the video processor contained in the data information, so that the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link is completed. The method has the advantages that manual configuration is not needed, the logical relationship between the actual physical link connection relationship and the system scheduling software is automatically detected to be unified, various wiring modes can be adapted, the problems that the cascade setting is complicated and easy to mistake in the installation and debugging process of the manual engineering of the ultra-large-scale wall splicing system are solved, the system debugging time is reduced, the accuracy and the efficiency of configuring the corresponding relationship between the cascade channel scheduling logic and the physical wiring links are effectively improved, and the flexibility of field equipment installation and deployment is improved.
In addition, the embodiment of the invention also provides a corresponding implementation device and a corresponding system for the video processor self-adaptive cascade method, so that the method has higher practicability, and the device and the system have corresponding advantages.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural frame diagram of a tiled wall system according to an exemplary embodiment of the present disclosure;
fig. 2 is a flowchart illustrating an adaptive cascading method for video processors according to an embodiment of the present invention;
fig. 3 is an interaction flow diagram of an adaptive cascading method for video processors according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating an interaction flow of another adaptive cascade method for video processors according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a framework of an adaptive cascade apparatus of a video processor according to a first exemplary embodiment of the present invention;
fig. 6 is a schematic diagram of a framework of an adaptive cascade apparatus of a video processor according to a second exemplary embodiment of the present invention;
fig. 7 is a block diagram of a video processor adaptive cascade device according to a third exemplary embodiment of the present invention;
fig. 8 is a block diagram of an embodiment of an adaptive cascade system of a video processor according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a framework structure of an adaptive cascade system of video processors according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
Having described the technical solutions of the embodiments of the present invention, various non-limiting embodiments of the present application are described in detail below.
Referring to fig. 2, fig. 2 is a schematic flow chart of an adaptive cascade method for a video processor according to an embodiment of the present invention, where an execution subject of the embodiment of the present invention is a signal cascade device, which may include the following:
s201: and sending the test data stream to the video processor through the first port.
The signal cascade has a plurality of ports, each port having an output and an input. After receiving the data output instruction, the signal generator inside the signal cascade device outputs the data to be transmitted as a test data stream through the port according to the data output port information carried in the data output instruction, for convenience of description, in the embodiment of the present invention, the output port is referred to as a first port output end, and the first port output end may be an output end of any one port (for example, No. 1) of the signal cascade device.
The video processor end is a general name of all video processors in the spliced wall system.
S202: and acquiring data information sent by a target video processor in the video processor end, wherein the data information comprises identification information of the target video processor.
Any video processor in the splicing wall system feeds back local identification information after receiving the data output by the signal cascade connector, so that the signal cascade connector obtains which video processor responds to the video processor of the first port as the video processor from the received signal. Any one of the video processors in the tiled wall system has unique identification information for uniquely identifying itself, which may be, for example, the video processor's ID number.
For convenience of description, a video processor that receives a test data stream transmitted by a signal cascade may be referred to as a target video processor.
S203: and determining the corresponding relation between the first port and the target video processor according to the data information so as to complete the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link.
It should be noted that, in the embodiment of the present invention, a port (first port) of the signal cascade device is taken as an example to describe a process of setting a corresponding relationship between the cascade channel scheduling logic and the physical connection link, and other ports may execute steps S201 to S203 to bind the ports of the entire signal cascade device and the video processor, thereby completing configuration of the corresponding relationship between the cascade channel scheduling logic and the physical connection link of the entire splicing wall system.
In the embodiment of the invention, a signal cascade device sends a test data stream to a video processor end through a known port, a video processor at the video processor end sends data information capable of identifying local information after receiving the test data stream, and the signal cascade device determines the corresponding relation between the known port of the signal cascade device and the video processor by receiving the identification information of the video processor contained in the data information, thereby completing the configuration of the corresponding relation between the scheduling logic of a cascade channel and a physical wiring link. The method has the advantages that manual configuration is not needed, the logical relationship between the actual physical link connection relationship and the system scheduling software is automatically detected to be unified, various wiring modes can be adapted, the problems that the cascade setting is complicated and easy to mistake in the installation and debugging process of the manual engineering of the ultra-large-scale wall splicing system are solved, the system debugging time is reduced, the accuracy and the efficiency of configuring the corresponding relationship between the cascade channel scheduling logic and the physical wiring links are effectively improved, and the flexibility of field equipment installation and deployment is improved.
In an embodiment, please refer to fig. 3, where fig. 3 is an interaction flow diagram of an adaptive cascade method for a video processor according to an embodiment of the present invention, and the embodiment of the present invention may include the following:
s301: the signal cascade device sends the test data stream to the video processor end through the first port output end.
S302: and a target video processor at the video processor end receives the test data stream, and adds the local identification information to the test data stream to generate effective data.
After any video processor in the splicing wall system receives the data output by the signal cascade connector, the received test data stream carrying local identification information is copied to a local output port for output.
Any one of the video processors in the tiled wall system has unique identification information for uniquely identifying itself, which may be, for example, the video processor's ID number.
For convenience of description, a video processor that receives a test data stream transmitted by a signal cascade may be referred to as a target video processor.
S303: and copying the valid data to an output port and sending the valid data to the signal cascade.
The target video processor can copy the test data stream to the local output port, and then output the test data stream after adding the local ID number; or after the ID number of the local computer is increased, the data can be copied to an output port for output, which does not influence the implementation of the application.
S304: the signal cascade device polls and detects each input port and determines the first input port with valid data.
The signal cascade device sends a test data stream, polls and detects each input port, and judges whether the data of each input port is valid, because only one input port of the signal cascade device can receive the data fed back, for example, the validity of the data can be judged by judging whether the received data stream contains specific information, if the received data stream contains the specific information, the input port receives the data sent by the video processor, and the port is the input port with valid data.
For convenience of description, an output terminal of a port that receives data transmitted by a target video processor may be referred to as a first input port.
The effective data is a test data stream carrying identification information of the target video processor, an input port and an output port. The input port is a port for receiving the test data stream by the target video processor, and the output port is a port for sending the test data stream carrying the local identification information by the target video processor.
S305: and obtaining the corresponding relation between the first port output end of the signal cascade device and the input port, the first input port and the output port of the target video processor according to the effective data.
When the signal cascade device detects that the data of the first input port is valid, the signal cascade device can obtain the identification information (such as an ID number) of the video processor carried in the test data stream from the valid data by decoding the valid data to obtain the corresponding relation between the output end of the first port of the signal cascade device and the input port of the processor corresponding to the ID number and the output end of the processor corresponding to the ID number and the first input port of the signal cascade device, namely, the unified setting of the logical data and the physical link of the corresponding port of the output end of the first port of the signal cascade device is completed.
It should be noted that, in the embodiment of the present invention, a port of a signal cascade device is taken as an example to describe a process of setting a correspondence relationship between a cascade channel scheduling logic and a physical connection link, and other ports may execute steps S201 to S205 to bind the ports of the entire signal cascade device and a video processor, thereby completing configuration of the correspondence relationship between the cascade channel scheduling logic and the physical connection link of the entire mosaic wall system.
In the technical solution provided in the embodiment of the present invention, a signal cascade device sends a data stream to a video processor end through a known output port, a video processor at the video processor end receives the data stream, adds local identification information, and then sends the data stream from the output port to the signal cascade device, and the signal cascade device determines a corresponding relationship between an output port of the signal cascade device and an input port of the video processor, an input port of the signal cascade device and an output port of the video processor through identification information of the video processor included in the data stream received by an input port of the signal cascade device, and input port and output port information passed through in a data stream transmission process, thereby completing configuration of a corresponding relationship between a scheduling logic of a cascade channel and a physical wiring link. The method has the advantages that manual configuration is not needed, the logical relationship between the actual physical link connection relationship and the system scheduling software is automatically detected to be unified, various wiring modes can be adapted, the problems that the cascade setting is complicated and easy to mistake in the installation and debugging process of the manual engineering of the ultra-large-scale wall splicing system are solved, the system debugging time is reduced, the accuracy and the efficiency of configuring the corresponding relationship between the cascade channel scheduling logic and the physical wiring links are effectively improved, and the flexibility of field equipment installation and deployment is improved.
In addition, the present application also provides another embodiment, please refer to fig. 3, where fig. 3 is an interaction flow diagram of another video processor adaptive cascade method according to the embodiment of the present invention, and the embodiment of the present invention may include the following contents:
s401: the signal cascade device sends a test data stream to the video processor end through the first port, and sets other ports which are not the first port to be in a closed state.
For convenience of description, in the embodiment of the present invention, a port for outputting data is referred to as a first port, and the first port may be any one port (for example, number 1) of the signal cascade device.
When the signal cascade device sends data, only the port sending the data is in an open state, and other ports not sending the data are closed. For example, when the signal cascade device transmits data through the port 1, the ports 2 to n are all in the closed state, and when the data is transmitted through the port 2, the ports 1 and 3 to n are all in the closed state.
S402: and each video processor at the video processor end detects whether the signal swing of each input port exceeds a preset threshold value.
After the signal cascade device sends data, each video processor can simultaneously detect whether an effective signal exists in each input port, and when the effective signal is judged, only the signal swing amplitude is detected to exceed a certain threshold, and the signal data does not need to be decoded. The port of the signal cascade which does not send data does not have any swing signal output because the port is in the closed state, and the video processor connected with the port does not detect that the signal is valid.
S403: and if the signal swing amplitude of the input port of the target video processor exceeds a preset threshold value, copying the received signal data out and sending a response packet to the local area network.
The video processor end comprises a plurality of video processors with preset and unique IP address information, and each video processor and the signal cascade device are respectively connected with the switch.
The target video processor is a video processor which receives the test data stream in the video processor end, when the video processor detects that the data is valid, the signal is copied and looped out, and a response packet is generated in the network to inform the signal cascade device that the signal is detected. For example, when the target video processor detects that the signal at the input port is valid, the target video processor copies the received signal out and sends a response packet to the local area network.
The response packet contains IP address information of the corresponding video processor (target video processor) so that the signal cascade device can determine which video processor receives the data after receiving the response packet.
S404: the signal cascade device obtains the response packet of the target video processor from the local area network and detects whether effective signals exist in each input channel.
After detecting the network response packet, the signal concatenator detects whether valid signals exist at each input port of the video processor after knowing that the video processor has detected the information, that is, detects which input port receives the data fed back by the video processor, and for example, can determine that valid signals exist in the input channel by determining whether the signal amplitude of the input port meets the requirement, for example, the signal amplitude exceeds a preset threshold.
S405: and if the input channel has an effective signal, binding the first port with the target video processor to complete the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link.
When the signal of a certain input port is detected to be effective, the port of the signal cascade device for outputting data is bound with the target video processor, so that the binding of the cascade port and the cascade port of the corresponding answering video processor can be completed.
And the signal cascade device binds other residual ports and the corresponding video processors according to the same method, thereby completing the configuration of the corresponding relation between the whole cascade channel scheduling logic and the physical wiring link.
As can be seen from the above, the signal cascade device and the video processor in the embodiment of the present invention access through a network, the signal cascade device sends data to the outside through the known port, the video processor receives the reply, and after receiving the reply message, the signal cascade device can determine the corresponding relationship between the known port and the port of the responding video processor, that is, the physical cascade channel connection relationship between the video processor and the signal cascade device is determined. The method has the advantages that manual configuration is not needed, the logical relationship between the actual physical link connection relationship and the system scheduling software is automatically detected to be unified, various wiring modes can be adapted, the problems that the cascade setting is complicated and easy to mistake in the installation and debugging process of the manual engineering of the ultra-large-scale wall splicing system are solved, the system debugging time is reduced, the accuracy and the efficiency of configuring the corresponding relationship between the cascade channel scheduling logic and the physical wiring links are effectively improved, and the flexibility of field equipment installation and deployment is improved.
The embodiment of the invention also provides a corresponding implementation device for the video processor self-adaptive cascade method, so that the method has higher practicability. In the following, the adaptive cascade device for a video processor provided by the embodiment of the present invention is introduced, and the adaptive cascade device for a video processor described below and the adaptive cascade method for a video processor described above may be referred to correspondingly.
Referring to fig. 5, fig. 5 is a structural diagram of an adaptive cascade apparatus for a video processor according to an embodiment of the present invention, in a specific implementation manner, based on a signal cascade apparatus, including:
a data sending module 501, configured to send a test data stream to a video processor through a first port;
a feedback data obtaining module 502, configured to obtain data information sent by a target video processor in a video processor side, where the data information includes identification information of the target video processor;
the correspondence setting module 503 is configured to determine a correspondence between the first port and the target video processor according to the data information, so as to complete configuration of a correspondence between the cascade channel scheduling logic and the physical connection link.
Optionally, in this embodiment of the present invention, the correspondence setting module 503 may detect each input port for polling, and determine that a first input port with valid data exists, where the valid data is a test data stream carrying identification information of the target video processor, the input port, and the output port; and the target video processor at the video processor end copies the test data stream added with the local identification information to an output port for outputting after receiving the test data stream sent by the first port output end.
In addition, the correspondence setting module 503 may also decode the valid data to obtain the identification information of the target video processor, for example; and the module determines the corresponding relation between the output end of the first port and the input end of the target video processor and the corresponding relation between the output end of the target video processor and the output end of the first port according to the identification information.
In another embodiment, the correspondence setting module 503 may further determine whether there is a valid signal in each input channel; if so, binding the first port with the target video processor; the video processor end comprises a plurality of video processors with preset and unique IP address information; each video processor and each signal cascade device are respectively connected with the switch; the target video processor is a video processor which receives the test data stream in the video processor end, and when the target video processor detects that the signal of the input port is effective, the target video processor copies the received signal out and sends a response packet to the local area network.
In this embodiment of the present invention, the feedback data obtaining module 502 may be a module that obtains a response packet sent by the target video processor to the local area network from the local area network, where the response packet includes IP address information of the target video processor.
Referring to fig. 6, fig. 6 is a structural diagram of an adaptive cascade device of a video processor according to another embodiment of the present invention, which is based on the video processor and includes:
the data receiving module 601 is configured to receive a test data stream sent by the signal cascade through the first port output end.
An identification information adding module 602, configured to add local identification information to the test data stream, and generate valid data; the valid data carries input port information and output port information for receiving the test data stream.
And a data sending module 603, configured to copy the valid data to the output port, and send the valid data to the signal cascade.
Finally, referring to fig. 7, fig. 7 is a structural diagram of an adaptive cascade device of a video processor according to an embodiment of the present invention in another specific implementation, where the adaptive cascade device includes, based on the video processor:
a judging module 701, configured to judge whether a signal swing of an input port exceeds a preset threshold;
the data copying module 702 is configured to copy the received signal data to loop out when the signal swing of the input port exceeds a preset threshold.
The response packet sending module 703 is configured to send a response packet to the local area network, so as to feed back information that the received signal concatenator sends the test data stream signal through the first port.
The signal cascade device and the video processor are respectively connected with the switch, and the video processor is provided with a preset and unique IP address; the reply packet contains the IP address information of the target video processor.
The functions of the functional modules of the video processor adaptive cascade device according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the description related to the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention effectively improves the accuracy and efficiency of the corresponding relation between the configuration cascade channel scheduling logic and the physical wiring link.
An embodiment of the present invention further provides an adaptive cascade system of a video processor, which is shown in fig. 8 and includes a video processor 801, a switch 802, and a signal cascade 803.
With reference to the system structure block diagram shown in fig. 9, the video processor 801 outputs the video signal to the corresponding mosaic wall, and the mosaic wall is composed of a plurality of video processors having preset and unique IP address information, and each video processor and the signal cascade 803 are respectively connected to the switch 802, so that each video processor and the signal cascade 803 can freely access through the local area network.
The signal cascade 803 is configured to send a test data stream through the first port, and set other ports other than the first port to be in a closed state; and after receiving a response packet sent by the target video processor through the network, judging whether effective signals exist in each input channel, and if so, binding the first port with the target video processor.
Each video processor is used for copying and looping out received signal data when detecting that the signal of the input port is effective, and sending a response packet to the local area network.
The functions of each functional module of the video processor adaptive cascade system according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the related description of the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention effectively improves the accuracy and efficiency of the corresponding relation between the configuration cascade channel scheduling logic and the physical wiring link.
The embodiment of the present invention further provides a video processor adaptive cascade device, which specifically includes:
a memory for storing a computer program;
a processor for executing a computer program to implement the steps of the video processor adaptive cascade method according to any of the above embodiments.
The functions of the functional modules of the video processor adaptive cascade device according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the description related to the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention effectively improves the accuracy and efficiency of the corresponding relation between the configuration cascade channel scheduling logic and the physical wiring link.
An embodiment of the present invention further provides a computer-readable storage medium, in which a video processor adaptive cascade program is stored, and when the video processor adaptive cascade program is executed by a processor, the steps of the video processor adaptive cascade method according to any one of the above embodiments are performed.
The functions of the functional modules of the computer-readable storage medium according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the related description of the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention effectively improves the accuracy and efficiency of the corresponding relation between the configuration cascade channel scheduling logic and the physical wiring link.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The present invention provides a method, an apparatus and a system for adaptive cascade connection of video processors. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (9)
1. A method for adaptive cascading of video processors, based on a signal cascade, comprising:
sending the test data stream to a video processor end through a first port;
acquiring data information sent by a target video processor in the video processor end, wherein the data information comprises identification information of the target video processor;
and determining the corresponding relation between the first port and the target video processor according to the data information so as to complete the configuration of the corresponding relation between the cascade channel scheduling logic and the physical wiring link.
2. The video processor adaptive cascade method of claim 1, wherein the determining the correspondence between the first port and the target video processor according to the data information comprises:
after receiving the test data stream sent by the output end of the first port, a target video processor at the video processor end copies the test data stream added with the local identification information to an output port for outputting;
polling and detecting each input port, and determining a first input port with valid data, wherein the valid data is a test data stream carrying identification information of the target video processor, the input port and the output port;
and obtaining the corresponding relation between the output end of the first port of the signal cascade device and the input port of the target video processor, the first input port and the output port of the target video processor according to the effective data.
3. The adaptive cascade method of claim 2, wherein the obtaining the corresponding relationship between the first port output of the signal cascade and the target video processor input port, the first input port, and the target video processor output port according to the valid data comprises:
decoding the effective data to obtain the identification information of the target video processor;
and determining the corresponding relation between the output end of the first port and the input port of the target video processor and the corresponding relation between the output end of the target video processor and the output end of the first port according to the identification information.
4. The adaptive cascade method for video processors according to claim 1, wherein when the signal cascade device sends the test data stream through the first port, setting other ports other than the first port to be in a closed state, and the acquiring the data information sent by the target video processor in the video processor includes:
and acquiring a response packet sent to the local area network by the target video processor from the local area network, wherein the response packet comprises the IP address information of the target video processor.
5. The video processor adaptive cascading method of claim 4, wherein the determining the correspondence between the first port and the target video processor according to the data information comprises:
judging whether effective signals exist in each input channel or not;
if so, binding the first port with the target video processor;
the video processor end comprises a plurality of video processors with preset and unique IP address information; each video processor and each signal cascade device are respectively connected with the switch; and the target video processor is the video processor which receives the test data stream in the video processor end, and copies and loops out the received signal and sends a response packet to the local area network when the target video processor detects that the signal of the input port is effective.
6. An adaptive cascade apparatus of video processors, based on a signal cascade, comprising:
the data sending module is used for sending the test data stream to the video processor end through the first port;
a feedback data acquisition module, configured to acquire data information sent by a target video processor in the video processor, where the data information includes identification information of the target video processor;
and the corresponding relation setting module is used for determining the corresponding relation between the first port and the target video processor according to the data information so as to complete the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link.
7. A video processor adaptive cascade method is characterized in that the method is based on a video processor and comprises the following steps:
receiving a test data stream sent by a signal cascade device through a first port output end;
adding local identification information to the test data stream to generate valid data;
copying the valid data to an output port and sending the valid data to the signal cascade device;
wherein the valid data carries input port information and output port information for receiving the test data stream; the signal cascade device polls and detects each input port and determines a first input port with the valid data;
and obtaining the corresponding relation between the output end of the first port of the signal cascade device and the input port of the target video processor, the first input port and the output port of the target video processor according to the effective data.
8. A video processor self-adaptive cascade system is characterized by comprising a plurality of video processors with preset and unique IP address information, a switch and a signal cascade device; each video processor and the signal cascade are respectively connected with the switch so as to realize free access of each video processor and the signal cascade through a local area network;
the signal cascade device is used for sending a test data stream through a first port and setting other ports which are not the first port to be in a closed state; after receiving a response packet sent by a target video processor through a network, judging whether effective signals exist in each input channel, if so, binding the first port with the target video processor to complete the configuration of the corresponding relation between the scheduling logic of the cascade channel and the physical wiring link; the response packet contains the IP address information of the target video processor;
each video processor is used for copying and looping out received signal data when detecting that the signal of the input port is effective, and sending a response packet to the local area network.
9. The adaptive cascade system of claim 8, wherein each video processor is configured to loop out the received signal data copy when detecting that the signal swing at the input port exceeds a predetermined threshold.
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