CN109584815A

CN109584815A - Display device

Info

Publication number: CN109584815A
Application number: CN201811138057.2A
Authority: CN
Inventors: 郑光哲; 金玄俊; 金成润; 梁贤锡; 李斗烈
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2017-09-28
Filing date: 2018-09-28
Publication date: 2019-04-05
Also published as: KR20190037389A; US10483341B2; US20190096978A1; KR102397411B1

Abstract

Provide a kind of display device.The display device includes: the first pixel, is located in the first pixel region and in conjunction with the first scan line；First scanning stage circuit in the first peripheral region outside the first pixel region, and is configured to supply the first scanning signal to the first scan line；Second pixel, in the second pixel region with the width smaller than the width of the first pixel region, and in conjunction with the second scan line；Second scanning stage circuit in the second peripheral region outside the second pixel region, and is configured to generate the second scanning signal；And the first load matched unit, it is located between the second scanning stage circuit, and be configured to make the second scanning signal delay and to the second scanning signal of the second scan line supply delay.

Description

Display device

This application claims in the preferential of the 10-2017-0126275 South Korea patent application submitted on the 28th of September in 2017 Power and equity, the complete disclosure of the South Korea patent application are incorporated herein by quoting entire contents.

Technical field

The various embodiments of the disclosure are related to a kind of display device.

Background technique

With the development of information technology, the display device as the connection medium between user and information is focused on Importance.Recently, liquid crystal display device, organic light-emitting display device etc. is widely used.

Such display device includes multiple pixels and driver used to drive pixels.To each pixel formed it is wired with And line is integrated to drive multiple transistors of display element.These lines can have different load values according to its length.By In the difference of load value, so image to be shown can be had non-uniform brightness.

Summary of the invention

The various embodiments of the disclosure are related to a kind of display device that can show the image with uniform luminance.

The various embodiments of the disclosure are related to a kind of display device with the structure that can effectively utilize idle space.

Embodiment of the disclosure can provide a kind of display device, and the display device includes: the first pixel, be located at first In pixel region and in conjunction with the first scan line；First scanning stage circuit, the first periphery outside the first pixel region In region, and it is configured to supply the first scanning signal to the first scan line；Second pixel, being located at has than the first pixel region In second pixel region of the small width of the width in domain, and in conjunction with the second scan line；Second scanning stage circuit is located at second In the second peripheral region outside pixel region, and it is configured to generate the second scanning signal；And the first load matched list Member is located between the second scanning stage circuit, and is configured to make the second scanning signal delay and be supplied to the second scan line Answer the second postponed scanning signal.

At least one angle in second pixel region can have curved shape.

The number of the second pixel on every horizontal line can reduce on the direction far from the first pixel region.

Each first load matched unit may include: the first delay pattern；And second delay pattern, be located at and first Postpone on the pattern different layer of layer disposed thereon, wherein insulating layer setting the first delay pattern with second postpone pattern it Between.

First delay pattern may include: input terminal, corresponding second scanning being integrated in the second scanning stage circuit The output terminal of grade circuit；And output terminal, corresponding second scan line being electrically coupled in the second scan line.

First delay pattern and the second delay pattern can form delay capacitor.

First load matched unit can make the second scanning signal delay and first postpones pattern and the second delay pattern pair The time constant answered.

Time constant can be with the first peripheral region and corresponding first load matched in the first load matched unit The increase of the distance between unit and increase.

The distance between second scanning stage circuit can be bigger than the distance between first scanning stage circuit.

The display device can also include: third pixel, positioned at the third pixel region being spaced apart with the second pixel region In domain, and in conjunction with third scan line；Third scanning stage circuit, positioned at the third periphery being arranged in outside third pixel region In region, and it is configured to generate third scanning signal；And the second load matched unit, it is located at third scanning stage electricity Between road, and it is configured to make third scanning signal delay and supplies postponed third scanning signal to third scan line.

Third pixel region can have the width smaller than the width of the first pixel region, and be located on every horizontal line Third pixel number can far from the first pixel region direction on reduce.

The distance between third scanning stage circuit can be bigger than the distance between first scanning stage circuit.

Each second load matched unit may include: the first delay pattern；And second delay pattern, be located at and first Postpone on the different layer of pattern layer disposed thereon, the second delay pattern is configured to form delay electric capacity with the first delay pattern Device.

Second load matched unit can make third scanning signal delay and first postpones pattern and the second delay pattern pair The time constant answered.

Time constant can be with the first peripheral region and corresponding second load matched in the second load matched unit The increase of the distance between unit and increase.

The display device can also include: the first antistatic circuit, in conjunction with the first scan line；And second is antistatic Circuit, in conjunction with the second scan line.

Detailed description of the invention

Fig. 1 is the figure for showing the pixel region of display device according to an embodiment of the present disclosure.

Fig. 2 is the figure for showing display device according to an embodiment of the present disclosure.

Fig. 3 is the figure for being shown specifically the construction of display device according to an embodiment of the present disclosure.

Fig. 4 and Fig. 5 is the figure for being shown specifically scanner driver shown in Fig. 3 and emitting driver.

Fig. 6 is the figure for the arragement construction for showing scanner driver according to an embodiment of the present disclosure and emitting driver.

Fig. 7 is the plan view for showing the construction of load matched unit shown in Fig. 4 and Fig. 5.

Fig. 8 is the cross-sectional view intercepted along the line I-I ' of Fig. 7.

Fig. 9 is the figure for showing the embodiment of display device shown in Figure 2.

Figure 10 is the figure for showing display device according to an embodiment of the present disclosure.

Specific embodiment

By referring to accompanying drawing with the detailed description of the following examples, can be more easily to understand inventive concept feature and The method for realizing the feature of the inventive concept.Hereinafter, embodiment is more fully described with reference to the accompanying drawings.However, of the invention It can be implemented in the form of a variety of different, and should not be construed as limited to embodiments shown herein.On the contrary, conduct Example provides these embodiments, so that the displosure will be thorough and complete, and will be to those skilled in the art fully Convey aspect and feature of the invention.Therefore, it will not describe to those skilled in the art to be understood completely this The aspect and feature of invention are without necessary technique, element and technology.Unless otherwise noted, it otherwise in entire attached drawing and written retouches In stating, same appended drawing reference indicates same element, therefore descriptions thereof will not be repeated.It, can be in addition, clear in order to make to describe The part unrelated with the description of embodiment is not shown.In the accompanying drawings, for the sake of clarity, element, layer and region can be exaggerated Relative size.

In the following description, for illustrative purposes, many specifically details are elaborated, to provide to various embodiments Thorough understanding.It will, however, be evident that in these no details or can have one or more equivalent arrangements In the case where practice various embodiments.In other cases, in order to avoid unnecessarily obscuring various embodiments, in form of a block diagram Show known features and device.

It will be appreciated that although term " first ", " second ", " third " etc. may be used herein describe various elements, Component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part and another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present invention, first element described below, component, region, layer or part It can be named as second element, component, region, layer or part.

For ease of explaining, can be used herein such as " ... under ", " in ... lower section ", "lower", " ... Under ", " in ... top ", "upper" etc. spatially relative term, with describe elements or features as illustrated in the diagram with it is another The relationship of (other) elements or features.It will be appreciated that spatially relative term alsos attempt to other than the orientation described in figure Different direction comprising device in use or in operation.For example, it is other to be described as " " if the device in figure is reversed Elements or features " below " or " under " or the elements or features of "lower" will then be positioned as " " described other elements or features " top ".Therefore, exemplary term " in ... lower section " and " ... under " may include above and below two kinds of orientation.Device (for example, being rotated by 90 ° or in other orientation) in addition can be positioned, and space used herein should be interpreted accordingly Opposite description language.Similarly, when first part is described as arranging " " second part "upper", this indicates first part's arrangement In the upside or downside of second part, and it is not limited to its upside based on gravity direction.

It will be appreciated that when element, layer, area, or component be referred to as " " another element, layer, area, or component "upper", When " being connected to " or " being integrated to " another element, layer, area, or component, the element, layer, area, or component can be directly described On another element, layer, area, or component, it is directly connected to or is bonded directly to another element, layer, area, or component, or Person may exist one or more intermediary elements, layer, area, or component.However, " be directly connected to/bind directly " refers to a group Part is directly connected to or combines another component without intermediate module.Meanwhile other statements of the relationship between description component are (all Such as, " ... between ", " between directly existing ... " or " with ... it is neighbouring " and " directly with ... neighbouring ") can be similar It explains on ground.In addition, it will be further understood that when element or layer be referred to " " two elements or layer " between " when, the element or layer Can be the sole component or layer between described two elements or layer, or there may also be one or more intermediary elements or Layer.

Term used herein is only and to be not intended to limit the present invention for for the purpose of describing particular embodiments.As here Used, singular " one (kind, person) " is also intended to include plural form, unless in addition context is expressly noted that.To also Understand, when using term "comprising", " having ", " comprising " and their modification in this description, illustrates that there are institutes Feature, entirety, step, operation, the element and/or component of statement, but do not preclude the presence or addition of one or more other spies Sign, entirety, step, operation, element, component and/or their group.As used herein, term "and/or" include one or Any combination and all combinations of more related institute lists.

When can differently implement some embodiment, it is suitable specific technique can be differently carried out with described sequence Sequence.For example, can be performed simultaneously substantially or execute two techniques continuously described with the sequence opposite with described sequence.

Referring herein to describing various embodiments as the cross-sectional view of embodiment and/or the schematic diagram of intermediate structure.In this way, By the variation of the expected such as shape of the diagram as caused by manufacturing technology and/or tolerance.In addition, in order to describe according to the disclosure The purpose of the embodiment of design, specific structure disclosed herein or functional descriptions are only illustrative.Therefore, reality disclosed herein Applying example should not be construed as being limited to the shape specifically illustrated in region, and will include in shape inclined caused by for example manufacturing Difference.Usually will have rounding or curved feature and/or injection dense in its edge for example, being shown as the injection zone of rectangle The gradient of degree, rather than the binary variation from injection zone to non-implanted region.It similarly, can be with by injecting the buried district domain that is formed Cause in buried district domain and some injections injected in the region between passed through surface occur.Therefore, area shown in the accompanying drawings Domain is actually schematical, their shape unexpectedly illustrates the true form in the region of device, and is not intended to be limited System.Therefore, as it would be recognized by those skilled in the art that described embodiment can modify in a variety of different ways, and Without departure from the spirit or scope of the disclosure.

It can use any suitable hardware, firmware (such as specific integrated circuit), software or software, firmware and hardware Combination realize the electronics or electric device and/or any other relevant apparatus of embodiment according to the present invention described herein Or component.For example, the various of these devices can be formed on integrated circuit (IC) chip or in separated IC chip Component.Furthermore, it is possible to be realized on flexible printed circuit film, carrier package part (TCP), printed circuit board (PCB) or can be with The various assemblies of these devices are formed on a substrate.In addition, in order to execute various functions as described herein, these devices Various assemblies can be process or thread, the process or thread are one or more in one or more computing devices It is run on a processor, executes computer program instructions, and interact with other system components.Computer program instructions are stored in It can use the storage that standard memory devices (such as, by taking random access memory (RAM) as an example) are realized in computing device In device.Computer program instructions can also be stored in other non-transitory computer-readable mediums (such as, with CD-ROM, sudden strain of a muscle For depositing driver etc.) in.In addition, one skilled in the art would recognize that not departing from exemplary embodiment of the present invention Spirit and scope in the case where, the function of various computing devices can be combined or integrated into single computing device, or The function of particular computing device can be distributed throughout one or more other computing devices.

Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have and this The those of ordinary skill of field that the present invention belongs to the normally understood meaning equivalent in meaning.It will be further understood that term (such as exists Term defined in the general dictionary) it should be interpreted as having and they are in the background of related fields and/or this specification It looks like the consistent meaning, and should not be to idealize or excessively the meaning that formalize explains them, unless here clearly such as This definition.

Fig. 1 is the figure for showing pixel region AA1, AA2 and AA3 of display device 10 according to an embodiment of the present disclosure.

It referring to Fig.1, may include pixel region AA1, AA2 and AA3, peripheral region according to the display device of the present embodiment 10 NA1, NA2 and NA3 and pixel PXL1, PXL2 and PXL3.

Pixel PXL1, PXL2 and PXL3 can be located in pixel region AA1, AA2 and AA3, so as in pixel region Each of AA1, AA2 and AA3 are upper to show image.Therefore, each of pixel region AA1, AA2 and AA3 can refer to viewing area Domain.

For driving the component (for example, driver and line) of pixel PXL1, PXL2 and PXL3 that peripheral region can be located at In NA1, NA2 and NA3.Because pixel is not located in peripheral region NA1, NA2 and NA3, peripheral region NA1, NA2 and NA3 Each of can refer to non-display area.

For example, peripheral region NA1, NA2 and NA3 can be formed in the outside of pixel region AA1, AA2 and AA3, and can To have at least part of shape for surrounding pixel region AA1, AA2 and AA3.

Pixel region AA1, AA2 and AA3 may include the first pixel region AA1, the second pixel region AA2 and third pixel Region AA3.

Second pixel region AA2 and third pixel region AA3 can be on the side of the first pixel region AA1.Second Pixel region AA2 and third pixel region AA3 can be separated from each other.

First pixel region AA1 can have bigger than the surface area of the second pixel region AA2 or third pixel region AA3 Surface area.

For example, the width W1 of the first pixel region AA1 can width W2 and third pixel region than the second pixel region AA2 The width W3 of domain AA3 is big.The length L1 of first pixel region AA1 can length L2 and third picture than the second pixel region AA2 The length L3 of plain region AA3 is big.

In addition, each of the second pixel region AA2 and third pixel region AA3 can have than the first pixel region The small surface area of the surface area of AA1, and the second pixel region AA2 and third pixel region AA3 can have it is mutually the same Surface area or with different surface areas.

For example, the width W2 of the second pixel region AA2 can be equal to or different from that the width W3 of third pixel region AA3. The length L2 of second pixel region AA2 can be equal to or different from that the length L3 of third pixel region AA3.

Peripheral region NA1, NA2 and NA3 may include the first peripheral region NA1, the second peripheral region NA2 and third periphery Region NA3.

First peripheral region NA1 can be located at around the first pixel region AA1, and can have and surround the first pixel At least part of shape of region AA1.

First peripheral region NA1 generally can have constant width.However, the present disclosure is not limited thereto.For example, first The width of peripheral region NA1 can change according to the position in display device 10.

Second peripheral region NA2 can be located at around the second pixel region AA2, and can have and surround the second pixel At least part of shape of region AA2.

Second peripheral region NA2 generally can have constant width.The present disclosure is not limited thereto.For example, the second periphery The width of region NA2 can change according to the position in display device 10.

Third peripheral region NA3 can be located at the outside of third pixel region AA3, and can have and surround third pixel At least part of shape of region AA3.

Third peripheral region NA3 generally can have constant width.The present disclosure is not limited thereto.For example, third is peripheral The width of region NA3 can change according to the position in display device 10.

Second peripheral region NA2 and third peripheral region NA3 can be bonded to each other or each other according to the shape of substrate 100 It does not combine.

First peripheral region NA1, the second peripheral region NA2 and third peripheral region NA3 generally can have identical Width.The present disclosure is not limited thereto.For example, the width of the first peripheral region NA1, the second peripheral region NA2 and third peripheral region NA3 Degree can change according to the position in display device 10.

Pixel PXL1, PXL2 and PXL3 may include the first pixel PXL1, the second pixel PXL2 and third pixel PXL3.

For example, the first pixel PXL1 can be located in the first pixel region AA1, the second pixel PXL2 can be located at the second picture In plain region AA2, third pixel PXL3 can be located in third pixel region AA3.

In the control for the driver being located in the first peripheral region NA1, the second peripheral region NA2 and third peripheral region NA3 Under system, the first pixel PXL1, the second pixel PXL2 and third pixel PXL3 can be with given brightness emission light.For the behaviour Make, each of the first pixel PXL1, the second pixel PXL2 and third pixel PXL3 may include light-emitting component (for example, organic Light emitting diode).

First pixel region AA1, the second pixel region AA2 and third pixel region AA3 and the first peripheral region NA1, Second peripheral region NA2 and third peripheral region NA3 can be limited in the substrate 100 of display device 10.

Substrate 100 can be made of the insulating materials of such as glass or resin.In addition, substrate 100 can be by having flexibility Material be made to become flexible or folding, and can have single layer structure or multilayered structure.

For example, substrate 100 may include at least one of the following: polystyrene, polyvinyl alcohol, poly-methyl methacrylate Ester, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenyl Thioether, polyarylate, polyimides, polycarbonate, Triafol T and cellulose acetate propionate.

However, constituting the material of substrate 100 can be changed in various ways, and substrate 100 can also be by glass Fibre reinforced plastics (FRP) etc. are made.

Substrate 100 can be formed with variously-shaped formation, as long as the first pixel region AA1, the second pixel region AA2 and third picture Plain region AA3 and the first peripheral region NA1, the second peripheral region NA2 and third peripheral region NA3 can be limited to substrate On 100.

For example, substrate 100 may include flat base substrate 101 and from the end of base substrate 101 outstanding One accessory plate 102 and the second accessory plate 103.

First accessory plate 102 and the second accessory plate 103 can be integrally formed with base substrate 101.Recess or recess 104 It can reside between the first accessory plate 102 and the second accessory plate 103.

Recess 104 can be the region formed by a part for removing substrate 100.First accessory plate 102 and second Accessory plate 103 can be separated from each other by recess 104.

Each of first accessory plate 102 and the second accessory plate 103 can have smaller than the surface area of base substrate 101 Surface area.First accessory plate 102 and the second accessory plate 103 can have mutually the same surface area, or can have difference Surface area.

First accessory plate 102 and the second accessory plate 103 can have various shape, as long as the second pixel region AA2 and Three pixel region AA3 and the second peripheral region NA2 and third peripheral region NA3 can be limited at 102 He of the first accessory plate On second accessory plate 103.

First pixel region AA1 and the first peripheral region NA1 can be limited on base substrate 101.Second pixel region Domain AA2 and the second peripheral region NA2 can be limited on the first accessory plate 102.Third pixel region AA3 and third external zones Domain NA3 can be limited on the second accessory plate 103.

Base substrate 101 can have various shape.For example, base substrate 101 can have such as polygonal shape or The shape of circular shape.In addition, at least part of base substrate 101 can have curved shape.

For example, base substrate 101 can have the shape of general rectangular.Optionally, the angle of base substrate 101 can have There are tilted shape or curved shape.

Although base substrate 101 can have the same or similar shape of shape with the first pixel region AA1, it is not It is limited to this, and can have the variform shape with the first pixel region AA1.

First accessory plate 102 and the second accessory plate 103 also can have various shape.

For example, each of the first accessory plate 102 and the second accessory plate 103 can have polygonal shape or round shape Shape.In addition, can have curved shape at least partially in each of the first accessory plate 102 and the second accessory plate 103.

Recess 104 can have various shape.For example, recess 104 can have such as polygonal shape or circular shape Shape.In addition, at least part of recess 104 can have curved shape.

First pixel region AA1 to third pixel region AA3 can have various shape.First pixel region AA1 to Each of three pixel region AA3 can have polygonal shape or circular shape.

In fig. 1 it is shown that wherein the first pixel region AA1 has the example of rectangular shape.The present disclosure is not limited thereto.Example Such as, at least part of the first pixel region AA1 can have curved shape.For example, the angle of the first pixel region AA1 can have There is curved shape, which has curvature.

In fig. 1 it is shown that wherein at least one in each of the second pixel region AA2 and third pixel region AA3 Divide the example with curved shape.The present disclosure is not limited thereto, and in the second pixel region AA2 and third pixel region AA3 It each can have rectangular shape.

In this case, the second peripheral region NA2 can have and the second pixel region AA2 at least a portion Corresponding curved shape.

In response to the change in shape of the second pixel region AA2, it is located at the second pixel PXL2's on every line (row or column) Number can change according to its position.

In addition, third peripheral region NA3 can be at least a portion with corresponding with third pixel region AA3 curved Curved shape.

In response to the change in shape of third pixel region AA3, it is located at the third pixel PXL3's on every line (row or column) Number can change according to its position.

Fig. 2 is the figure for showing display device 10 according to an embodiment of the present disclosure.

Referring to Fig. 2, the display device 10 according to the present embodiment may include substrate 100, the first pixel PXL1, the second pixel PXL2, third pixel PXL3, the first scanner driver 210, the second scanner driver 220, third scanner driver 230, first Emit driver 310, second and emits driver 320 and third transmitting driver 330.

First pixel PXL1 can be located in the first pixel region AA1, and each first pixel PXL1 can be incorporated into First scan line S1, the first launch-control line E1 and the first data line D1.

First scanner driver 210 can supply the first scanning signal to the first pixel PXL1 by the first scan line S1.

For example, the first scanner driver 210 can sequentially supply the first scanning signal to the first scan line S1.

First scanner driver 210 can be located in the first peripheral region NA1.

For example, the first scanner driver 210 can be located at the side for being present in the first pixel region AA1 (for example, in Fig. 2 Left side) on the first peripheral region NA1 in.

First scanning line route can be in conjunction between the first scanner driver 210 and the first scan line S1.

First scanner driver 210 can pass through the first scanning line route and first in the first pixel region AA1 Scan line S1 is electrically coupled.

First transmitting driver 310 can be believed by the first launch-control line E1 to the first transmitting of the first pixel PXL1 supply Number.

For example, the first transmitting driver 310 can sequentially supply the first transmitting signal to the first launch-control line E1.

First transmitting driver 310 can be located in the first peripheral region NA1.

For example, the first transmitting driver 310 can be located at the side for being present in the first pixel region AA1 (for example, in Fig. 2 Left side) on the first peripheral region NA1 in.

In fig. 2 it is shown that wherein the first transmitting driver 310 is located at showing on the outside of the first scanner driver 210 Example, but in other embodiments, the first transmitting driver 310 can be located on the inside of the first scanner driver 210.

First transmitting line route can be in conjunction between the first transmitting driver 310 and the first launch-control line E1.

First transmitting driver 310 can pass through the first transmitting line route and first in the first pixel region AA1 Launch-control line E1 is electrically coupled.

On the other hand, in the case where the first pixel PXL1 is not needed using the first transmitting signal, it is convenient to omit the first hair It penetrates driver 310, first and emits line route and the first launch-control line E1.

In fig. 1 it is shown that wherein the first scanner driver 210 and the first transmitting driver 310 are located at the first pixel region Example on the left side of domain AA1, but the present disclosure is not limited thereto.For example, the first scanner driver 210 and the first transmitting driver 310 can be on the right side of the first pixel region AA1, or can be located in the left and right side of the first pixel region AA1 Either side or two sides on.

Second pixel PXL2 can be located in the second pixel region AA2, and each second pixel PXL2 can be incorporated into Second scan line S2, the second launch-control line E2 and the second data line D2.

Second scanner driver 220 can supply the second scanning signal to the second pixel PXL2 by the second scan line S2.

For example, the second scanner driver 220 can sequentially supply the second scanning signal to the second scan line S2.

Second scanner driver 220 can be located in the second peripheral region NA2.

For example, the second scanner driver 220 can be located at the side for being present in the second pixel region AA2 (for example, in Fig. 2 Left side) on the second peripheral region NA2 in.

Second scanning line route can be in conjunction between the second scanner driver 220 and the second scan line S2.

The second scanner driver 220 can be by the second scanning line route and in the second pixel region AA2 as a result, Second scan line S2 is electrically coupled.

Second transmitting driver 320 can be believed by the second launch-control line E2 to the second transmitting of the second pixel PXL2 supply Number.

For example, the second transmitting driver 320 can sequentially supply the second transmitting signal to the second launch-control line E2.

Second transmitting driver 320 can be located in the second peripheral region NA2.

For example, the second transmitting driver 320 can be located at the side for being present in the second pixel region AA2 (for example, in Fig. 2 Left side) on the second peripheral region NA2 in.

In fig. 2 it is shown that wherein the second transmitting driver 320 is located at showing on the outside of the second scanner driver 220 Example.However, in other embodiments, the second transmitting driver 320 can be located on the inside of the second scanner driver 220.

Second transmitting line route can be in conjunction between the second transmitting driver 320 and the second launch-control line E2.

Second transmitting driver 320 can pass through the second transmitting line route and second in the second pixel region AA2 Launch-control line E2 is electrically coupled.

On the other hand, in the case where the second pixel PXL2 is not needed using the second transmitting signal, it is convenient to omit the second hair It penetrates driver 320, second and emits line route and the second launch-control line E2.

Because the surface area of the first pixel region of surface area ratio AA1 of the second pixel region AA2 is small, the second scan line The length of S2 and the second launch-control line E2 can length respectively than the first scan line S1 and the first launch-control line E1 it is small.

In addition, being integrated to the number of the second pixel PXL2 of every second scan line S2 can sweep than being integrated to every first The number for retouching the first pixel PXL1 of line S1 is few.The number for being integrated to the second pixel PXL2 of every second launch-control line E2 can It is few with the number than the first pixel PXL1 for being integrated to every first launch-control line E1.

Third pixel PXL3 can be located in third pixel region AA3, and each third pixel PXL3 can be incorporated into Third scan line S3, third launch-control line E3 and third data line D3.

Third scanner driver 230 can supply third scanning signal to third pixel PXL3 by third scan line S3.

For example, third scanner driver 230 can sequentially supply third scanning signal to third scan line S3.

Third scanner driver 230 can be located in third peripheral region NA3.

For example, third scanner driver 230 can be located at the side for being present in third pixel region AA3 (for example, in Fig. 2 Right side) on third peripheral region NA3 in.

Third scans line route can be in conjunction between third scanner driver 230 and third scan line S3.

Third scanner driver 230 can scan line route by third and be located in third pixel region AA3 as a result, Third scan line S3 is electrically coupled.

Third, which emits driver 330, can supply third transmitting letter to third pixel PXL3 by third launch-control line E3 Number.

For example, third transmitting driver 330 can sequentially supply third transmitting signal to third launch-control line E3.

Third, which emits driver 330, to be located in third peripheral region NA3.

For example, third transmitting driver 330 can be located at the side for being present in third pixel region AA3 (for example, in Fig. 2 Right side) on third peripheral region NA3 in.

In fig. 2 it is shown that wherein third transmitting driver 330 is located at showing on the outside of third scanner driver 230 Example.However, in other embodiments, third, which emits driver 330, to be located on the inside of third scanner driver 230.

Third emits line route and can emit between driver 330 and third launch-control line E3 in conjunction in third.

Therefore, third transmitting driver 330 can emit line route by third and be located in third pixel region AA3 Third launch-control line E3 is electrically coupled.

On the other hand, in the case where third pixel PXL3 is not needed using third transmitting signal, it is convenient to omit third hair Penetrate driver 330, third transmitting line route and third launch-control line E3.

Because the surface area of the first pixel region of surface area ratio AA1 of third pixel region AA3 is small, third scan line The length of S3 and third launch-control line E3 can length respectively than the first scan line S1 and the first launch-control line E1 it is small.

In addition, being integrated to the number of the third pixel PXL3 of every third scan line S3 can sweep than being integrated to every first The number for retouching the first pixel PXL1 of line S1 is few.The number for being integrated to the third pixel PXL3 of every third launch-control line E3 can It is few with the number than the first pixel PXL1 for being integrated to every first launch-control line E1.

Transmitting signal is for controlling the time, and the first pixel PXL1, the second pixel PXL2 or third pixel PXL3 are when described Between during emit light.In embodiment, transmitting signal can be set with the width bigger than the width of scanning signal.

For example, transmitting signal can be set to grid cut-off voltage (for example, high level voltage), so that being included in first Transistor in pixel PXL1, the second pixel PXL2 or third pixel PXL3 can end.Scanning signal can be set to grid Pole conducting voltage (for example, low level voltage), so that being included in the first pixel PXL1, the second pixel PXL2 or third pixel PXL3 In transistor can be connected.

Data driver 400 can be by the first data line D1, the second data line D2 and third data line D3 to the first picture Plain PXL1, the second pixel PXL2 and third pixel PXL3 supply data-signal.For example, the second data line D2 can be incorporated into first Some first data line D1 in data line D1, third data line D3 can be incorporated into the first data line D1 other first Data line D1.

Data driver 400 can be located in the first peripheral region NA1, and can reside at such position: number It is stacked not with the first scanner driver 210 at this location according to driver 400.For example, data driver 400 can be located at first In part on the downside for being present in the first pixel region AA1 of peripheral region NA1.

Data driver 400 can pass through core on such as chip on glass method, chip-on-plastic method, carrier package method and film Any one of the various methods of piece method method is installed.

For example, data driver 400 can be directly installed in substrate 100, or individual component (example can be passed through Such as, flexible printed circuit board) it is integrated to substrate 100.

In other embodiments, display device 10 can also include sequence controller, the sequence controller be configured to First scanner driver 210, the second scanner driver 220 and third scanner driver 230, first emit driver 310, second Emit driver 320 and third transmitting driver 330 and data driver 400 provides control signal.

Fig. 3 is the figure for being shown specifically the construction of display device 10 according to an embodiment of the present disclosure.

First scanner driver 210 can by first scanning line route R11 to R1k and the first scan line S11 to S1k to First pixel PXL1 supplies the first scanning signal.

First scanning line route R11 to R1k can be scanned in conjunction in the output terminal of the first scanner driver 210 and first Line S11 is between S1k.

For example, the first scanning line route R11 to R1k and the first scan line S11 to S1k can be located on different layers, and And it in such a case, it is possible to is bonded to each other by contact hole.

Optionally, the first scanning line route R11 to R1k and the first scan line S11 to S1k may be integrally formed same On layer.In other words, the first scanning line route R11 to R1k can be the part of the first scan line S11 to S1k.

First transmitting driver 310 can be by the first transmitting line route R31 to R3k and the first launch-control line E11 extremely E1k emits signal to the first pixel PXL1 supply first.

First transmitting line route R31 to R3k can emit in conjunction with the output terminal and first in the first transmitting driver 310 Control line E11 is between E1k.

For example, the first transmitting line route R31 to R3k and the first launch-control line E11 to E1k can be located at different layers On, and in this case, it can be bonded to each other by contact hole.

Optionally, the first transmitting line route R31 to R3k and the first launch-control line E11 to E1k may be integrally formed On same layer.In other words, the first transmitting line route R31 to R3k can be the part of the first launch-control line E11 to E1k.

First scanner driver 210 and the first transmitting driver 310 can be respectively responsive to the first scan control signals SCS1 and the first emissioning controling signal ECS1 is operated.

Data driver 400 can supply data-signal to the first pixel PXL1 by the first data line D11 to D1o.

First pixel PXL1 can be incorporated into the first pixel power ELVDD and the second pixel power ELVSS.When suitable, First pixel PXL1 can additionally be integrated to initialization power supply Vint.

When supplying the first scanning signal to the first scan line S11 to S1k, the first pixel PXL1 can be supplied with from the The data-signal of one data line D11 to D1o.Each of the first pixel PXL1 for being supplied with data-signal can control through The magnitude of current of the second pixel power ELVSS is flowed to by Organic Light Emitting Diode.

Second scanner driver 220 can by second scanning line route R21 to R2j and the second scan line S21 to S2j to Second pixel PXL2 supplies the second scanning signal.

Second scanning line route R21 to R2j can be scanned in conjunction in the output terminal of the second scanner driver 220 and second Line S21 is between S2j.

For example, the second scanning line route R21 to R2j and the second scan line S11 to S2j can be located on different layers, and And it in such a case, it is possible to is bonded to each other by contact hole.

Optionally, the second scanning line route R21 to R2j and the second scan line S21 to S2j may be integrally formed same On layer.In this case, the second scanning line route R21 to R2j can be the part of the second scan line S21 to S2j.

Second transmitting driver 320 can be by the second transmitting line route R41 to R4j and the second launch-control line E21 extremely E2j emits signal to the second pixel PXL2 supply second.

Second transmitting line route R41 to R4j can emit in conjunction with the output terminal and second in the second transmitting driver 320 Control line E21 is between E2j.

For example, the second transmitting line route R41 to R4j can be located at different layers from the second launch-control line E21 to E2j On, and in this case, it can be bonded to each other by contact hole.

Optionally, second transmitting line route R41 to R4j and the second launch-control line E21 to E2j can be located on the same floor On.In this case, the second transmitting line route R41 to R4j can be the part of the second launch-control line E21 to E2j.

Second scanner driver 220 and the second transmitting driver 320 can be respectively responsive to the second scan control signals SCS2 and the second emissioning controling signal ECS2 is operated.

Data driver 400 can supply data-signal to the second pixel PXL2 by the second data line D21 to D2p.

For example, the second data line D21 to D2p can be combined with some first data line D11 to D1 (m-1).

Second pixel PXL2 can be incorporated into the first pixel power ELVDD and the second pixel power ELVSS.When suitable, Second pixel PXL2 can additionally be integrated to initialization power supply Vint.

When supplying the second scanning signal to the second scan line S21 to S2j, the second pixel PXL2 can be supplied with from the The data-signal of two data line D21 to D2p.Each of the second pixel PXL2 for being supplied with data-signal can control through The magnitude of current of the second pixel power ELVSS is flowed to by Organic Light Emitting Diode.

In addition, the number for the second pixel PXL2 being located on every line (row or column) can change according to its position.

Since the surface area of the first pixel region of surface area ratio AA1 of the second pixel region AA2 is small, so the second pixel The number of PXL2 can be fewer than the number of the first pixel PXL1.Second scan line S21 to S2j and the second launch-control line E21 are extremely The length and number of E2j can be respectively than the length sum number of the first scan line S11 to S1k and the first launch-control line E11 to E1k Mesh is small.

The number for being integrated to any one second pixel PXL2 of the second scan line S21 into S2j can be than being integrated to The number of any one first pixel PXL1 of the first scan line S11 into S1k is few.

The number for being integrated to any one second pixel PXL2 of the second launch-control line E21 into E2j can be than knot The number for closing any one the first pixel PXL1 to the first launch-control line E11 into E1k is few.

Third scanner driver 230 can by third scan line route R51 to R5h and third scan line S31 to S3h to Third pixel PXL3 supplies third scanning signal.

Third scans line route R51 to R5h and can scan in conjunction with the output terminal and third in third scanner driver 230 Line S31 is between S3h.

For example, third scanning line route R51 to R5h and third scan line S31 to S3h can be located on different layers, In this case, it can be bonded to each other by contact hole.

Optionally, third scanning line route R51 to R5h and third scan line S31 to S3h may be integrally formed same On layer.In this case, third scanning line route R51 to R5h can be the part of third scan line S31 to S3h.

Third scanner driver 230 can be operated in response to third scan control signal SCS3.

Third, which emits driver 330, can emit line route R61 to R6h and third launch-control line E31 extremely by third E3h emits signal to third pixel PXL3 supply third.

Third emits line route R61 to R6h and can emit in conjunction with the output terminal and third in third transmitting driver 330 Control line E31 is between E3h.

For example, third transmitting line route R61 to R6h and third launch-control line E31 to E3h can be located at different layers On, in such a case, it is possible to be bonded to each other by contact hole.

Optionally, third transmitting line route R61 to R6h and third launch-control line E31 to E3h may be integrally formed On same layer.In this case, third transmitting line route R61 to R6h can be the portion of third launch-control line E31 to E3h Point.

Third transmitting driver 330 can be operated in response to third emissioning controling signal ECS3.

Data driver 400 can supply data-signal to third pixel PXL3 by third data line D31 to D3q.

Third data line D31 to D3q can be incorporated into some first data line D1 (n+1) to D1o.

Third pixel PXL3 can be incorporated into the first pixel power ELVDD and the second pixel power ELVSS.When suitable, Third pixel PXL3 can additionally be integrated to initialization power supply Vint.

When supplying third scanning signal to third scan line S31 to S3h, third pixel PXL3 can be supplied with from the The data-signal of three data line D31 to D3q.Each of the third pixel PXL3 for being supplied with data-signal can control through The magnitude of current of the second pixel power ELVSS is flowed to by Organic Light Emitting Diode.

In addition, the number for the third pixel PXL3 being located on every line (row or column) can change according to its position.

Since the surface area of the first pixel region of surface area ratio AA1 of third pixel region AA3 is small, so third pixel The number of PXL3 can be fewer than the number of the first pixel PXL1.Third scan line S31 to S3h and third launch-control line E31 are extremely The length of E3h can length respectively than the first scan line S11 to S1k and the first launch-control line E11 to E1k it is small.

The number for being integrated to any one third pixel PXL3 of the third scan line S31 into S3h can be than being integrated to The number of any one first pixel PXL1 of the first scan line S11 into S1k is few.

The number for being integrated to any one third pixel PXL3 of the third launch-control line E31 into E3h can be than knot The number for closing any one the first pixel PXL1 to the first launch-control line E11 into E1k is few.

Data driver 400 can be operated in response to data controlling signal DCS.

Sequence controller 270 can control the first scanner driver 210, the second scanner driver 220, third turntable driving Device 230, data driver 400, first emit driver 310, second and emit driver 320 and third transmitting driver 330.

For the operation, sequence controller 270 can be respectively to the first scanner driver 210, the second scanner driver 220 The first scan control signal SCS1, the second scan control signal SCS2 and third scanning control are supplied with third scanner driver 230 Signal SCS3 processed.In addition, sequence controller 270 can emit 320 and of driver to the first transmitting driver 310, second respectively Third emits driver 330 and supplies the first emissioning controling signal ECS1, the second emissioning controling signal ECS2 and third emission control Signal ECS3.

Here, the first scan control signal SCS1, the second scan control signal SCS2 and third scan control signal SCS3 And each of the first emissioning controling signal ECS1, the second emissioning controling signal ECS2 and third emissioning controling signal ECS3 can To include at least one clock signal and initial pulse.

Initial pulse can control the timing of the first scanning signal or the first transmitting signal.Clock signal may be used to Initial pulse displacement.

Sequence controller 270 can supply data controlling signal DCS to data driver 400.

Data controlling signal DCS may include source electrode initial pulse and at least one clock signal.Source electrode initial pulse can To control the sampling initial time of data, clock signal can be used for controlling sampling operation.

Fig. 4 and Fig. 5 is the figure for being shown specifically scanner driver shown in Fig. 3 and emitting driver.For example, Fig. 4 is shown First scanner driver 210, second scanner driver 220, first transmitting driver 310 and the second transmitting driver 320.Figure 5 show third scanner driver 230 and third transmitting driver 330.

Referring to Fig. 4, the first scanner driver 210 may include multiple first scanning stage circuit SST11 to SST1k.

Each of first scanning stage circuit SST11 to SST1k can be incorporated into the first scanning line route R11 into R1k One end of corresponding first scanning line route, allows the first scanning signal to be supplied to the first scan line S11 corresponding into S1k The first scan line.

Here, the first scanning stage circuit SST11 to SST1k can believe in response to the clock supplied from sequence controller 270 Number CLK1 and CLK2 is operated.First scanning stage circuit SST11 to SST1k can be formed by identical circuit.

Each of first scanning stage circuit SST11 to SST1k can be supplied with the output signal of previous scanning stage circuit (for example, scanning signal) or it is supplied with initial pulse SSP1.

For example, the one the first scanning stage circuit SST11 can be supplied with initial pulse SSP1, and other first scanning stages Each of circuit SST12 to SST1k can be supplied with the output signal of previous scanning stage circuit.

In another embodiment, the one the first scanning stage circuit SST11 of the first scanner driver 210 can will be from second The signal of the last scanning stage circuit SST2j output of scanner driver 220 is used as initial pulse.

Each of first scanning stage circuit SST11 to SST1k can be supplied with the first driving power VDD1 and second and drive Dynamic power supply VSS1.

Here, the first driving power VDD1 can be set as grid cut-off voltage (for example, high level voltage).Second driving Power supply VSS1 can be set as gate-on voltage (for example, low level voltage).

Second scanner driver 220 may include the second scanning stage circuit SST21 to SST2j and multiple first load matcheds Unit LM21 to LM2j.

Each of second scanning stage circuit SST21 to SST2j can be incorporated into the first load matched unit LM21 extremely One end of corresponding first load matched unit in LM2j.Each of first load matched unit LM21 to LM2j can be tied One end for closing the corresponding second scanning line route to the second scanning line route R21 into R2j, so that the second scanning signal can be with It is supplied to the second scan line S21 corresponding second scan line into S2j.

Each of first load matched unit LM21 to LM2j can will be from the second scanning stage circuit SST21 to SST2j In corresponding second scanning stage circuit output the second scanning signal delay given value.

Each of first load matched unit LM21 to LM2j can be the circuit formed by resistor and capacitor, and And it may be constructed such that the output signal of corresponding second scanning stage circuit is prolonged into SST2j by the second scanning stage circuit SST21 The time constant (RC retardation ratio value) of slow circuit.

For example, the one the first load matched unit LM21 can make the letter exported from the one the second scanning stage circuit SST21 Number delay, and the signal of delay can be supplied to the one the second scanning line route R21.

For the operation, input terminal in each of the first load matched unit LM21 to LM2j can be with the second scanning The output terminal of corresponding second scanning stage circuit of the grade circuit SST21 into SST2j is electrically coupled.First load matched unit Output terminal in each of LM21 to LM2j can be with corresponding second scanning road of the second scanning line route R21 into R2j It is combined by one end of line.

Each of first load matched unit LM21 to LM2j can be located at the second scanning stage circuit SST21 to SST2j In corresponding the second neighbouring scanning stage circuit between.

Here, the second scanning stage circuit SST21 to SST2j can believe in response to the clock supplied from sequence controller 270 Number CLK1 and CLK2 is operated.Each of second scanning stage circuit SST21 to SST2j can be formed by identical circuit.

Each of second scanning stage circuit SST21 to SST2j can be supplied with the output signal of previous scanning stage circuit (for example, scanning signal) or it is supplied with initial pulse SSP2.

For example, the one the second scanning stage circuit SST21 can be supplied with initial pulse SSP2, and other second scanning stages Each of circuit SST22 to SST2j can be supplied with the output signal of previous scanning stage circuit.

In addition, the last scanning stage circuit SST2j of the second scanner driver 220 can be to the first scanner driver 210 In the one the first scanning stage circuit SST11 supply output signal.

Each of second scanning stage circuit SST21 to SST2j can be supplied with the first driving power VDD1 and second and drive Dynamic power supply VSS1.

First clock line 241 and second clock line 242 can be incorporated into the first scanner driver 210 and the second turntable driving Device 220.

In addition, the first clock line 241 and second clock line 242 can be combined with sequence controller 270, so that from timing control The first clock signal clk 1 and second clock signal CLK2 that device 270 processed is supplied can be for transmission to 210 Hes of the first scanner driver Second scanner driver 220.

For the operation, the first clock line 241 and second clock line 242 can be located at the first peripheral region NA1 and second In peripheral region NA2.

First clock signal clk 1 and second clock signal CLK2 can have different phases.For example, second clock is believed Number CLK2 can have 180 ° of phase difference relative to the first clock signal clk 1.

In fig. 4 it is shown that the first scanner driver 210 and the second scanner driver 220 share same first clock line 241 and the case where same second clock line 242, but the present disclosure is not limited thereto.For example, the first scanner driver 210 and second is swept Retouching driver 220 can be in conjunction with each clock lines being separated from each other.

In addition, in fig. 4 it is shown that each of the first scanner driver 210 and the second scanner driver 220 use two The case where a clock signal (the first clock signal clk 1 and second clock signal CLK2), but in 210 He of the first scanner driver In each of second scanner driver 220 by the number of clock signal to be used can according to the structure of scanning stage circuit and Change.

First clock line 241 and second clock line 242 of the present embodiment are not bonded to the first load matched unit LM21 extremely LM2j。

First transmitting driver 310 may include multiple first emitting stage circuit EST11 to EST1k.

Each of first emitting stage circuit EST11 to EST1k can be incorporated into the first transmitting line route R31 into R3k It is corresponding first transmitting line route one end, allow first transmitting signal be supplied to the first launch-control line E11 to E1k In corresponding first launch-control line.

Here, the first emitting stage circuit EST11 to EST1k can believe in response to the clock supplied from sequence controller 270 Number CLK3 and CLK4 is operated.First emitting stage circuit EST11 to EST1k can be formed by identical circuit.

Each of first emitting stage circuit EST11 to EST1k can be supplied with the output signal of previous emitting stage circuit (for example, transmitting signal) or it is supplied with initial pulse SSP3.

For example, the one the first emitting stage circuit EST11 can be supplied with initial pulse SSP3, and other first emitting stages Each of circuit EST12 to EST1k can be supplied with the output signal of previous emitting stage circuit.

In another embodiment, the one the first emitting stage circuit EST11 in the first transmitting driver 310 can will be from the The signal of the last emitting stage circuit EST2j output of two transmitting drivers 320 is used as initial pulse.

Each of first emitting stage circuit EST11 to EST1k can be supplied with third driving power VDD2 and 4 wheel driven Dynamic power supply VSS2.

Here, third driving power VDD2 can be set as grid cut-off voltage (for example, high level voltage).4th driving Power supply VSS2 can be set as gate-on voltage (for example, low level voltage).

Third driving power VDD2 can have voltage identical with the voltage of the first driving power VDD1.4th driving electricity Source VSS2 can have voltage identical with the voltage of the second driving power VSS1.

Second transmitting driver 320 may include multiple second emitting stage circuit EST21 to EST2j.

Each of second emitting stage circuit EST21 to EST2j can be incorporated into the second transmitting line route R41 into R4j It is corresponding second transmitting line route one end, allow second transmitting signal be supplied to the second launch-control line E21 to E2j In corresponding second launch-control line.

Here, the second emitting stage circuit EST21 to EST2j can believe in response to the clock supplied from sequence controller 270 Number CLK3 and CLK4 is operated.Second emitting stage circuit EST21 to EST2j can be formed by identical circuit.

Each of second emitting stage circuit EST21 to EST2j can be supplied with the output signal of previous emitting stage circuit (for example, transmitting signal) or it is supplied with initial pulse SSP4.

For example, the one the second emitting stage circuit EST21 can be supplied with initial pulse SSP4, and other second emitting stages Each of circuit EST22 to EST2j can be supplied with the output signal of previous emitting stage circuit.

In addition, in another embodiment, the last emitting stage circuit EST2j of the second transmitting driver 320 can be to the The one the first emitting stage circuit EST11 of one transmitting driver 310 supply output signal.

Each of second emitting stage circuit EST21 to EST2j can be supplied with third driving power VDD2 and 4 wheel driven Dynamic power supply VSS2.

Third clock line 243 and the 4th clock line 244 can be incorporated into the first transmitting driver 310 and the second transmitting driving Device 320.

In addition, third clock line 243 and the 4th clock line 244 can be combined with sequence controller 270, so that from timing control The third clock signal clk 3 and the 4th clock signal clk 4 that device 270 processed is supplied can be for transmission to the first transmitting 310 Hes of driver Second transmitting driver 320.

For the operation, third clock line 243 and the 4th clock line 244 can be located at the first peripheral region NA1 and second In peripheral region NA2.

Third clock signal clk 3 and the 4th clock signal clk 4 can have different phases.For example, third clock is believed Number CLK3 can have 180 ° of phase difference relative to the 4th clock signal clk 4.

In fig. 4 it is shown that the first transmitting driver 310 and the second transmitting driver 320 share same third clock line 243 and the case where same 4th clock line 244, but the present disclosure is not limited thereto.For example, the first transmitting driver 310 and the second hair Penetrating driver 320 can be in conjunction with each clock lines being separated from each other.

In addition, in fig. 4 it is shown that each of the first transmitting driver 310 and the second transmitting driver 320 use two The case where a clock signal (third clock signal clk 3 and the 4th clock signal clk 4), but in other embodiments, first Emitting can be according to hair by the number of clock signal to be used in each of driver 310 and the second transmitting driver 320 It penetrates the structure of grade circuit and changes.

Referring to Fig. 5, third scanner driver 230 may include multiple third scanning stage circuit SST31 to SST3h and multiple Second load matched unit LM31 to LM3h.

Each of third scanning stage circuit SST31 to SST3h can be incorporated into the second load matched unit LM31 extremely One end of corresponding second load matched unit in LM3h.Each of second load matched unit LM31 to LM3h can be tied One end for closing corresponding third scanning line route of the third scanning line route R51 into R5h, so that third scanning signal can be with It is supplied to corresponding third scan line of the third scan line S31 into S3h.

Each of second load matched unit LM31 to LM3h can will be from third scanning stage circuit SST31 to SST3h In corresponding third scanning stage circuit output third scanning signal delay given value.Second load matched unit LM31 is extremely Each of LM3h can be the circuit formed by resistor and capacitor, and may be constructed such that third scanning stage circuit The time constant of the output signal delay circuit of corresponding third scanning stage circuit of the SST31 into SST3h.

For example, the one the second load matched unit LM31 can make the letter exported from the first third scanning stage circuit SST31 Number delay, and the signal of delay can be supplied to the first third scanning line route R51.

For the operation, input terminal in each of the second load matched unit LM31 to LM3h can be scanned with third The output terminal of corresponding third scanning stage circuit of the grade circuit SST31 into SST3h is electrically coupled.Second load matched unit Output terminal in each of LM31 to LM3h can scan corresponding third of the line route R51 into R5h with third and scan road It is combined by one end of line.

Each of second load matched unit LM31 to LM3h can be located at third scanning stage circuit SST31 to SST3h In corresponding neighbouring third scanning stage circuit between.

Here, third scanning stage circuit SST31 to SST3h can believe in response to the clock supplied from sequence controller 270 Number CLK5 and CLK6 is operated.Third scanning stage circuit SST31 to SST3h can be formed by identical circuit.

Each of third scanning stage circuit SST31 to SST3h can be supplied with the output signal of previous scanning stage circuit (for example, scanning signal) or it is supplied with initial pulse SSP5.

For example, the first third scanning stage circuit SST31 can be supplied with initial pulse SSP5, and other third scanning stages Each of circuit SST32 to SST3h can be supplied with the output signal of previous scanning stage circuit.

Each of third scanning stage circuit SST31 to SST3h can be supplied with the first driving power VDD1 and second and drive Dynamic power supply VSS1.

5th clock line 245 and the 6th clock line 246 can be incorporated into third scanner driver 230.

In addition, the 5th clock line 245 and the 6th clock line 246 can be combined with sequence controller 270, so that from timing control The 5th clock signal clk 5 and the 6th clock signal clk 6 that device 270 processed is supplied can be for transmission to third scanner drivers 230.

For the operation, the 5th clock line 245 and the 6th clock line 246 can be located at the first peripheral region NA1 and third In peripheral region NA3.

5th clock signal clk 5 and the 6th clock signal clk 6 can have different phases.For example, the 6th clock is believed Number CLK6 can have 180 ° of phase difference relative to the 5th clock signal clk 5.

5th clock line 245 of the present embodiment and the 6th clock line 246 are not joined to the second load matched unit LM31 extremely LM3h。

In fig. 5 it is shown that third scanner driver 230 uses two clock signals (the 5th clock signal clk 5 and the Six clock signal clks 6) the case where, but in other embodiments, clock to be used is believed in third scanner driver 230 Number number can be changed according to the structure of scanning stage circuit.

Third scanning stage circuit SST31 to SST3h can have and the first scanning stage circuit SST11 to SST1k and second The identical circuit structure of the circuit structure of scanning stage circuit SST21 to SST2j.

It may include multiple third emitting stage circuit EST31 to EST3h that third, which emits driver 330,.

Each of third emitting stage circuit EST31 to EST3h can be incorporated into third transmitting line route R61 into R6h Corresponding third transmitting line route one end, allow third transmitting signal be supplied to third launch-control line E31 to E3h In corresponding third launch-control line.

Here, third emitting stage circuit EST31 to EST3h can believe in response to the clock supplied from sequence controller 270 Number CLK7 and CLK8 is operated.Third emitting stage circuit EST31 to EST3h can be formed by identical circuit.

Each of third emitting stage circuit EST31 to EST3h can be supplied with the output signal of previous emitting stage circuit (for example, transmitting signal) or it is supplied with initial pulse SSP6.

For example, the first third emitting stage circuit EST31 can be supplied with initial pulse SSP6, and other third emitting stages Each of circuit EST32 to EST3h can be supplied with the output signal of previous emitting stage circuit.

Each of third emitting stage circuit EST31 to EST3h can be supplied with third driving power VDD2 and 4 wheel driven Dynamic power supply VSS2.

7th clock line 247 and the 8th clock line 248 can be incorporated into third transmitting driver 330.

In addition, the 7th clock line 247 and the 8th clock line 248 can be combined with sequence controller 270, so that from timing control The 7th clock signal clk 7 and the 8th clock signal clk 8 that device 270 processed is supplied can emit driver 330 for transmission to third.

For the operation, the 7th clock line 247 and the 8th clock line 248 can be located at the first peripheral region NA1 and third In peripheral region NA3.

7th clock signal clk 7 and the 8th clock signal clk 8 can have different phases.For example, the 8th clock is believed Number CLK8 can have 180 ° of phase difference relative to the 7th clock signal clk 7.

In fig. 5 it is shown that third transmitting driver 330 uses two clock signals (the 7th clock signal clk 7 and the Eight clock signal clks 8) the case where, but in other embodiments, clock to be used is believed in third transmitting driver 330 Number number can be changed according to the structure of emitting stage circuit.

Third emitting stage circuit EST31 to EST3h can have and the first emitting stage circuit EST11 to EST1k and second The identical circuit structure of the circuit structure of emitting stage circuit EST21 to EST2j.

Fig. 6 is the figure for the arragement construction for showing scanner driver according to an embodiment of the present disclosure and emitting driver.Example Such as, in fig. 6 it is shown that wherein the second scanning stage circuit SST21 to SST25, the first load matched unit LM21 to LM25 with And second emitting stage circuit EST21 to EST25 be located at the example in the second peripheral region NA2.

Referring to Fig. 6, the angle of the second peripheral region NA2 can have curved shape.For example, as shown in Figure 6, the second periphery The region that the second scanning stage circuit SST21 to SST25 and the second emitting stage circuit EST21 to EST25 of region NA2 are located at can With with curved shape, the curved shape is with curvature.

Corresponding to the second peripheral region NA2, the angle of the second pixel region AA2 also can have curved shape.

In order to enable the angle of the second pixel region AA2 has curved shape, each picture in the second pixel region AA2 The number of pixel PXL2 on plain row can reduce on the direction far from the first pixel region AA1.

Although the length for each pixel column being arranged in the second pixel region AA2 is separate first pixel region AA1's Reduce on direction, but do not need to fix length reduction rate, and the number including the pixel PXL2 in each pixel column It can be changed in various ways according to the bent curvature of a curve at the angle for limiting the second pixel region AA2.

First peripheral region NA1 can have linearity configuration.In this case, the first pixel region AA1 can have Rectangular shape.

Therefore, the different pixels row of the first pixel region AA1 can have equal number of pixel PXL1.

It can have curved shape different from the first peripheral region NA1, the second peripheral region NA2.Therefore, in order to effectively Using as the second peripheral region NA2, the second scanning stage circuit SST21 to SST25 of idle space and the second emitting stage circuit The suitable arragement construction of EST21 to EST25 can emit with the first scanning stage circuit and first in the first peripheral region NA1 The arragement construction of grade circuit is different.

For example, the distance between first scanning stage circuit can be set as fixed value, and the second scanning stage circuit SST21 is extremely The distance between SST25 can be set as than the distance between the first scanning stage circuit big value.

In addition, the distance between second scanning stage circuit SST21 to SST25 can change according to its position.

For example, a pair of neighbouring the distance between the second scanning stage circuit SST23 and SST24 can be neighbouring with another pair The distance between second scanning stage circuit SST21 and SST22 is different.

In addition, being different from the first scanning stage circuit although the first scanning stage circuit, which is orientated, is nearly parallel to pixel column Orientation, the second scanning stage circuit SST21 to SST25 can be oriented relative to pixel column with angle.For example, the second scanning Each of grade circuit SST21 to SST25 can be on the direction far from the first peripheral region NA1 relative to the angle of pixel column Increase.

Each of first load matched unit LM21 to LM25 can be located at the second scanning stage circuit SST21 to SST25 In corresponding the second neighbouring scanning stage circuit between.

For example, the one the first load matched unit LM21 can be located at the one the second scanning stage circuit SST21 and the two the Between two scanning stage circuit SST22.

The two the first load matched unit LM22 can be located at the two the second scanning stage circuit SST22 and scan with the three the second Between grade circuit SST23.

As described above with reference to FIG. 1, the width W1 of the first pixel region AA1 can be than the width W2 of the second pixel region AA2 Greatly.Therefore, in the case where the first scan line S11 to S1k and the second scan line S21 to S2j extend in a lateral direction, first Scan line S11 to S1k can be than the second scan line S21 to S2j long.

In this case, the load value of the first scan line S11 to S1k can be than the load value of the second scan line S21 to S2j Greatly.The difference of load value will lead to luminance difference.It can be in the first pixel region AA1 and the second pixel for example, can have horizontal line Visible problem on boundary between the AA2 of region.

However, display device 10 according to an embodiment of the present disclosure may include described load matched unit LM21 extremely LM25 is to compensate the difference of load value, to solve the above problems.

In addition, load matched unit LM21 to LM25, which can be set, is being formed in the second scanning stage circuit SST21 to SST25 Between exceptional space in, so as to improve the space utilization rate of the second peripheral region NA2.

Second emitting stage circuit EST21 to EST25 can also be in a manner of with the second scanning stage circuit SST21 to SST25 Identical mode is arranged.

For example, the distance between first emitting stage circuit can be set as fixed value, and the second emitting stage circuit EST21 is extremely The distance between EST25 can be set as than the distance between the first emitting stage circuit big value.

In addition, the distance between second emitting stage circuit EST21 to EST25 can change according to its position.

For example, a pair of neighbouring the distance between the second emitting stage circuit EST23 and EST24 can be neighbouring with another pair The distance between second emitting stage circuit EST21 and EST22 is different.

In detail, a pair of neighbouring the distance between the second emitting stage circuit EST21 and EST22 can be more neighbouring than another pair The distance between the second emitting stage circuit EST23 and EST24 it is big.

Although being different from the first emitting stage circuit in addition, the first emitting stage circuit is orientated and is nearly parallel to pixel column Orientation, the second emitting stage circuit EST21 to EST25 can be oriented relative to pixel column with angle.For example, the second transmitting Each of grade circuit EST21 to EST25 can be on the direction far from the first peripheral region NA1 relative to the angle of pixel column Increase.

In other embodiments, illusory emitting stage circuit can be set the second emitting stage circuit EST21 to EST25 it Between.

For example, each illusory emitting stage circuit can be located at corresponding neighbour of the second emitting stage circuit EST21 into EST25 Between the second close emitting stage circuit.The number of illusory emitting stage circuit between the second neighbouring emitting stage circuit can be with Changed according to its position.

Illusory emitting stage circuit can have structure identical with the structure of the second emitting stage circuit EST21 to EST25, but It is not combined with third clock line 243 and the 4th clock line 244.Therefore, output transmitting signal is not executed to illusory emitting stage circuit Operation.Third scanning stage circuit SST31 to SST3h, the second load matched unit LM31 in third peripheral region NA3 It can be with the second scanning stage electricity in the second peripheral region NA2 to LM3h and third emitting stage circuit EST31 to EST3h Road SST21 to SST2j, the first load matched unit LM21 to LM2j and the second emitting stage circuit EST21 are to the two sides pair EST2j Claim.

Illusory emitting stage circuit also can be set in third emitting stage circuit EST31 between EST3h.

Fig. 7 is the plan view for showing the construction of load matched unit shown in Fig. 4 and Fig. 5.Fig. 8 is the line I- along Fig. 7 The cross-sectional view of I ' interception.

Referring to Fig. 7 and Fig. 8, the first load matched unit LM21 to LM2j and the second load matched unit LM31 into LM3h Each of may include the first delay pattern DR and second delay pattern DP.

First delay pattern DR can be located on the first insulating layer IL1.At least part of first delay pattern DR can be with With curved shape.First delay pattern DR can be located at the second scan line S21 to S2j and third scan line S31 to S3h's On the identical layer of layer.

First delay pattern DR may be used as the first load matched unit LM21 to LM2j and the second load matched unit The postponing resistance of corresponding load matched unit of the LM31 into LM3h.

First delay pattern DR may include input terminal INT and output terminal OPT.Input terminal INT can be incorporated into The corresponding scanning stage circuit of second scanning stage circuit SST21 to SST2j and third scanning stage circuit SST31 into SST3h Output terminal.Output terminal OPT can scan line route R51 into R5h by the second scanning line route R21 to R2j and third Corresponding scanning line route be electrically coupled to corresponding into S3h of the second scan line S21 to S2j and third scan line S31 and sweep Retouch line.

Second delay pattern DP can be located on the layer different from the first delay layer of pattern DR, and can have rectangle Plate shape.For example, second insulating layer IL2 can be located on the first delay pattern DR, the second delay pattern DP can be located at second On insulating layer IL2.In addition, third insulating layer IL3 can be located on the second delay pattern DP.

First delay pattern DR and the second delay pattern DP can be stacked on top of each other on different layers.Therefore, the first delay The delay of pattern DR and second pattern DP can form delay capacitor Cd.

Delay capacitor Cd is formed in order to make the first delay pattern DR and second postpone pattern DP, it can be to the second delay figure Case DP supplies the first driving power VDD1 or the second driving power VSS1.

Second delay pattern DP can be to provide a part of the power line for supplying the first driving power VDD1.It is optional Ground, the second delay pattern DP can be by being electrically coupled to provide the power line for supplying the first driving power VDD1 to alignment.

Alternately, the second delay pattern DP can be to provide the power line for supplying the second driving power VSS1 A part.Alternately, the second delay pattern DP can be driven by being electrically coupled to provide to alignment for supplying second The power line of dynamic power supply VSS1.

Due to postponing resistance and delay capacitor Cd, the first load matched unit LM21 to LM2j and the second load matched list Each of first LM31 to LM3h can make the second scanning stage circuit SST21 to SST2j and third scanning stage circuit SST31 extremely The output signal of corresponding scanning stage circuit in SST3h postpones RC retardation ratio value.

The length for being arranged in each pixel column in the second pixel region AA2 can be separate first pixel region AA1's Reduce on direction.In addition, the length for each pixel column being arranged in third pixel region AA3 can be far from the first pixel region Reduce on the direction of domain AA1.

In other words, the length of the one the second scan line S21 can be smaller than the length of the second last scan line S2j.At this In the case of kind, the RC retardation ratio value of the one the first load matched unit LM21 can be set to than the first last load matched list The big value of the RC retardation ratio value of first LM2j.

In addition, the length of the first third scan line S31 can be smaller than the length of last third scan line S3h.This In the case of, the RC retardation ratio value of the one the second load matched unit LM31 can be set to than the second last load matched unit The big value of the RC retardation ratio value of LM3h.

In other words, the first load matched unit LM21 to LM2j and the second load matched unit LM31 to LM3h can be set It is set to so that as each load matched unit and the distance between the first pixel region AA1 or the first peripheral region NA1 increase, RC retardation ratio value increases.

Can by control postponing resistance and delay capacitor Cd value come adjust the first load matched unit LM21 to RC retardation ratio value in each of LM2j and the second load matched unit LM31 to LM3h.

For example, the first load matched unit LM21 can be adjusted by changing length or the thickness of the first delay pattern DR To postponing resistance in each of LM2j and the second load matched unit LM31 to LM3h.

Furthermore, it is possible to be adjusted by changing the first delay pattern DR and the second delay pattern DP surface area stacked on top of each other The capacitance of delay capacitor Cd.

Fig. 9 is the figure for showing the embodiment of display device 10 shown in Figure 2.

The description of Fig. 9 will focus on and the difference of above-described embodiment (for example, embodiment of Fig. 3), and if it is considered to superfluous It is remaining, then it will omit some descriptions.Here, it is described below and will focus on antistatic circuit 510,520 and 530.

Referring to Fig. 9, display device 10 according to an embodiment of the present disclosure can also include antistatic circuit 510,520 and 530。

First antistatic circuit 510 can be between the first scanner driver 210 and the first pixel PXL1, and can be with In conjunction with the first scan line S11 to S1k.

When high voltage (for example, electrostatic) moment being applied to the line being arranged in display device 10, the first antistatic circuit 510 high voltages that may be used to apply are distributed to entire first scan line S11 to S1k.

Second antistatic circuit 520 can be between the second scanner driver 220 and the second pixel PXL2, and can be with In conjunction with the second scan line S21 to S2j.

When high voltage (for example, electrostatic) moment being applied to the line being arranged in display device 10, the second antistatic circuit 520 high voltages that may be used to apply are distributed to entire second scan line S21 to S2j.

Second antistatic circuit 520 can be formed by circuit identical with the circuit of the first antistatic circuit 510.

Third antistatic circuit 530 can be between third scanner driver 230 and third pixel PXL3, and can be with In conjunction with third scan line S31 to S3h.

When high voltage (for example, electrostatic) moment being applied to the line being arranged in display device 10, third antistatic circuit 530 high voltages that may be used to apply are distributed to entire third scan line S31 to S3h.

Third antistatic circuit 530 can be formed by circuit identical with the circuit of the first antistatic circuit 510.

Figure 10 is the figure for showing display device 10 ' according to an embodiment of the present disclosure.

The description of Figure 10 will focus on and the difference of above-described embodiment (for example, embodiment of Fig. 2), and if it is considered to superfluous It is remaining, then it will omit some descriptions.It is described below and will focus on the 4th pixel region AA4 and fourth peripheral region NA4.

Referring to Fig.1 0, display device 10 ' according to an embodiment of the present disclosure may include the first pixel region AA1, second Pixel region AA2, third pixel region AA3 and the 4th pixel region AA4, the first peripheral region NA1, the second peripheral region NA2, Third peripheral region NA3 and fourth peripheral region NA4 and pixel PXL1, PXL2, PXL3 and PXL4.

4th pixel region AA4 can be located on the side of the first pixel region AA1, and can be with the second pixel region AA2 and third pixel region AA3 is spaced apart and the first pixel region AA1 is placed in therebetween.

4th pixel region AA4 can have the surface area smaller than the surface area of the first pixel region AA1.For example, the 4th The length L4 of pixel region AA4 can be smaller than the length L1 of the first pixel region AA1.

Fourth peripheral region NA4 can be located at the outside of the 4th pixel region AA4, and can have and surround the 4th pixel At least part of shape of region AA4.

According to the shape of substrate 100 ', fourth peripheral region NA4 and the first peripheral region NA1 can be bonded to each other or not In conjunction with.

First peripheral region NA1, the second peripheral region NA2, third peripheral region NA3 and fourth peripheral region NA4 are overall On can have identical width.However, the present disclosure is not limited thereto.For example, the first peripheral region NA1, the second peripheral region Width in each of NA2, third peripheral region NA3 and fourth peripheral region NA4 can change according to its position.

Pixel PXL1, PXL2, PXL3 and PXL4 may include the first pixel PXL1, the second pixel PXL2, third pixel PXL3 and the 4th pixel PXL4.

For example, the first pixel PXL1 can be located in the first pixel region AA1.Second pixel PXL2 can be located at the second picture In plain region AA2.Third pixel PXL3 can be located in third pixel region AA3.4th pixel PXL4 can be located at the 4th picture In plain region AA4.

4th pixel PXL4 can be in the 4th scanner driver 240 being located in the NA4 of fourth peripheral region and the 4th transmitting Transmitting has the light of corresponding brightness under the control of driver 340.For the operation, each 4th pixel PXL4 may include shining Element (for example, Organic Light Emitting Diode).

Substrate 100 ' can be formed with variously-shaped formation, as long as the first pixel region AA1, the second pixel region AA2, third picture Plain region AA3 and the 4th pixel region AA4 and the first peripheral region NA1, the second peripheral region NA2, third peripheral region NA3 It can be limited in substrate 100 ' with fourth peripheral region NA4.

For example, substrate 100 ' may include: flat base substrate 101；First accessory plate 102 and the second accessory plate 103, It is protruded in one direction from the first end of base substrate 101；And the 4th accessory plate 105, from the second end of base substrate 101 Extend.

The angle of 4th accessory plate 105 can have tilted shape or curved shape.In response to this, the 4th pixel region AA4 At least part can have curved shape.For example, the angle of the 4th pixel region AA4 can have curved shape, the bending Shape has curvature.

In this case, fourth peripheral region NA4 can have and the 4th pixel region AA4 at least a portion Corresponding curved shape.

In response to the change in shape of the 4th pixel region AA4, it is located at the 4th pixel PXL4's on every line (row or column) Number can change according to its position.For example, the number for the 4th pixel PXL4 being located on every line can be far from first Reduce on the direction of pixel region AA1.

4th scanner driver 240 may include and be arranged in the second scanner driver 220 or third scanner driver 230 In the identical load matched unit of load matched unit.

Each load matched unit in the 4th scanner driver 240, which is arranged in, to be located in the 4th scanning stage circuit Between corresponding the 4th neighbouring scanning stage circuit.Here, load matched unit can be set such that with each load The distance between matching unit and the first pixel region AA1 increase, and RC retardation ratio value increases.

The various embodiments of the disclosure can provide the display device that can show the image with uniform luminance.

The various embodiments of the disclosure can provide the display device with the structure that can effectively utilize idle space.

There has been disclosed example embodiments, although use specific term, using they and will be only with general Property and descriptive sense explain them, rather than the purpose for limitation.In some cases, for ordinary skill Personnel will be apparent that, from submitting the application, unless explicitly stated otherwise, otherwise describe in conjunction with specific embodiments Feature, characteristic and/or element can be used alone or can with combine other embodiments description feature, characteristic and/or Element is applied in combination.Therefore, it will be appreciated by those skilled in the art that not departing from as (including its function is equivalent for claim Object) in the case where the spirit and scope of the present disclosure that are illustrated, various change in form and details can be carried out.

Claims

1. a kind of display device, the display device include:

First pixel is located in the first pixel region and in conjunction with the first scan line；

First scanning stage circuit in the first peripheral region outside first pixel region, and is configured to institute It states the first scan line and supplies the first scanning signal；

Second pixel, in the second pixel region with the width smaller than the width of first pixel region, and with Second scan line combines；

Second scanning stage circuit in the second peripheral region outside second pixel region, and is configured to generate Second scanning signal；And

First load matched unit is located between the second scanning stage circuit, and is configured to make described second to sweep It retouches signal delay and supplies the second postponed scanning signal to second scan line.

2. display device according to claim 1, wherein at least one angle of second pixel region has Curved Shape.

3. display device according to claim 1, wherein the number of second pixel on every horizontal line exists It is reduced on direction far from first pixel region.

4. display device according to claim 1, wherein the load of each of described first load matched unit first Include: with unit

First delay pattern；And

Second delay pattern, on the layer different from the first delay layer of pattern is located thereon, wherein insulating layer is set It sets between the first delay pattern and the second delay pattern.

5. display device according to claim 4, wherein described first, which postpones pattern, includes:

Input terminal is integrated to the output terminal of the corresponding second scanning stage circuit in the second scanning stage circuit；And

Output terminal, corresponding second scan line being electrically coupled in second scan line.

6. display device according to claim 4, wherein the first delay pattern is formed with the second delay pattern Delay capacitor.

7. display device according to claim 6, wherein the first load matched unit makes second scanning signal Delay time constant corresponding with the first delay pattern and the second delay pattern.

8. display device according to claim 7, wherein the time constant with first peripheral region with it is described The increase of the distance between corresponding first load matched unit in first load matched unit and increase.

9. display device according to claim 1, wherein the distance between described second scanning stage circuit is than described first The distance between scanning stage circuit is big.

10. display device according to claim 1, the display device further include:

Third pixel scans knot in the third pixel region being spaced apart with second pixel region, and with third It closes；

Third scanning stage circuit in the third peripheral region being arranged in outside the third pixel region, and is constructed To generate third scanning signal；And

Second load matched unit is located between the third scanning stage circuit, and is configured to sweep the third It retouches signal delay and supplies postponed third scanning signal to the third scan line.

11. display device according to claim 10, wherein the third pixel region has than first pixel region The small width of the width in domain, and

Wherein, the number of the third pixel on every horizontal line subtracts on the direction far from first pixel region It is few.

12. display device according to claim 10, wherein the distance between described third scanning stage circuit is than described The distance between one scanning stage circuit is big.

13. display device according to claim 10, wherein each of described second load matched unit second loads Matching unit includes:

First delay pattern；And

Second delay pattern, on the layer different from the first delay layer of pattern is located thereon, second delay Pattern is configured to form delay capacitor with the first delay pattern.

14. display device according to claim 13, wherein the second load matched unit makes the third scanning letter Number delay postpones the corresponding time constant of pattern with the first delay pattern and described second.

15. display device according to claim 14, wherein the time constant is with first peripheral region and institute It states the increase of the distance between corresponding second load matched unit in the second load matched unit and increases.

16. display device according to claim 1, the display device further include:

First antistatic circuit, in conjunction with first scan line；And

Second antistatic circuit, in conjunction with second scan line.