CN109582618A - A kind of the data transmission matching circuit and method of 7816 smart card and CPU - Google Patents
A kind of the data transmission matching circuit and method of 7816 smart card and CPU Download PDFInfo
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- CN109582618A CN109582618A CN201811369686.6A CN201811369686A CN109582618A CN 109582618 A CN109582618 A CN 109582618A CN 201811369686 A CN201811369686 A CN 201811369686A CN 109582618 A CN109582618 A CN 109582618A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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Abstract
The invention discloses the data transmission matching circuits of a kind of 7816 smart cards and CPU, it includes that cpu clock generates unit, 7816 clock generating units, register interface unit, transmitting line and reception circuit, the data of transmitting line output are transmitted to 7816 smart cards, the data that 7816 smart cards are sent are transmitted to reception circuit, the data terminal of writing of register interface unit passes through the transmission FIFO being sequentially connected in series and sends the input terminal that caching is connected to transmitting line, the output end for receiving circuit passes through the reception caching being sequentially connected in series and receives the reading data terminal that FIFO is connected to register interface unit, cpu clock generates unit for providing cpu clock signal, 7816 clock generating units are for providing 7816 clock signals.Circuit structure of the present invention is simple, it is good to the applicability of communication protocol, message transmission rate can be improved, can be achieved across clocked data transfer.
Description
Technical field
The present invention relates to 7816 interfaces and cpu data transmission circuit, more particularly to a kind of data of 7816 smart cards and CPU
Transmit match circuit and method.
Background technique
About the developing history of IC card, 1970, Frenchman rowland De Moruinuo can be programmed setting for the first time
IC (Integrated Circuit) chip be put in card, make card have more functions.At that time, he was to this technology
Description be: be inlaid with the card that can carry out self-protection memory.Thus be born first IC card in the world.Hereafter
Three ten years, with the development of very large scale integration technology, computer technology and information security technology etc., IC card
Type is more abundant, and technology is also more mature, is at home and abroad widely used.According to the different IC of the chip of insertion
Card can divide are as follows:
1. storage card: chip is electrically erasable programmable read-only memory EEPROM (Electrically in blocking
Erasable Programmable Read-only Memory) and address decoding circuitry and instruction decoding circuit.In order to
It is encapsulated in the plastic clip base of 0.76mm, the special thin type structure at 0.3mm.It is this card convenient storage, cheap,
Do not have function of keeping secret, is generally used for the information that storage does not need secrecy.Such as the customer menu of medical first aid card, catering trade
Card；
2. logic encryption card: such card also has encryption logic other than the EEPROM with storage card, read every time/
Password authentification is first carried out before writing card.If continuous, password authentification mistake, card will be self-locking several times, become dead card.Logic
Encrypted card is also a kind of passive-type card, is communicated using the method for synchronization.Such card amount of storage is relatively small, and price is relatively just
Preferably, suitable for there is the occasion of certain security requirements, such as dining room dinning card, phonecard, public utilities rate card.They store key
And its ability of execution Modern cryptographic algorithms makes it possible to the safety that height is realized in offline electronic payment system；
3.CPU card: such chip interior include microprocessor unit (CPU), storage unit (RAM, ROM and EEPROM),
With input/output interface unit.Wherein, RAM is used to store the intermediate data in calculating process, and solidification has operation in piece in ROM
System COS (Chip Operating System), and EEPROM is used to store the personal information of holder and issues unit
For information about.The enciphering/deciphering of CPU management information and transmission, stringent to take precautions against unauthorized access card inside information, discovery is illegal for several times to visit
It asks, the corresponding information area (can also be unlocked with high level 1 command) will be locked.The capacity of CPU card varies, and price compares logic add
Close card wants high.But the good processing capacity and excellent security performance of CPU card become the Main way of IC card development.
CPU card is suitable for the extra high occasion of confidentiality requirement, such as fiscard, military secret order transmitting card；
4. supper-intelligent card: increasing keyboard, liquid crystal display, power supply on the basis of CPU card, become a supper-intelligent
Block, also there is fingerprint identification device on some cards.A kind of Hyper Card of VISA international credit card tissue test has 20 and is good for,
It can show 16 characters, in addition to having timing, computer currency exchange function, also be stored with personal information, medical treatment, travelling data
With telephone number etc..
Smart card needs are communicated with device end and data exchange, therefore define intelligence in international standard ISO7816
The basic electrical characteristic that can block, refers to following table:
| C1: supply voltage | C5: ground connection |
| C2: reset signal input | C6: program voltage |
| C3: clock signal input | C7: serial input/output |
| C4: reserved bit | C8: reserved bit |
Wherein, C2 is reset pin input, and what the contact C3 was supplied to card is input clock, it provides message transmission rate
Benchmark, the low-limit frequency of card clock are 1MHz, and maximum frequency 5MHz, C7 are bi-directional data mouth, and card and the data of terminal are transmitted
It is to be realized by this contact.ISO 7816-3 standard is referred to as ETU (elementary with the formal definition of chronomere
Time unit) the position time.Referring to Figure 1, it can transmit the effective of 8 bits to the structure of 7816 interface transmission characters
Data.
It can be seen that the transmission rate of 7816 interfaces is very slow, from several Khz to several hundred Khz, and in CPU card and intelligence
In card, for the CPU working frequency of system generally in 10Mhz or more, some systems are even more than 100Mhz.Lead to 7816 interface rates
There are huge differences between CPU, this will bring two problems, firstly, 7816 interfaces will occupy a large amount of CPU in operation
Time drags slow whole system performance；Secondly, even thousands of times of frequency difference hundred times of two clock domains, data therebetween are passed
It is defeated to be easy to bring maloperation, as soon as the burr signal in Slow Clock domain, is easy to be sampled by quick clock domain, in turn result in
Transmit error in data.
Summary of the invention
The technical problem to be solved in the present invention is that in view of the deficiencies of the prior art, it is simple, anti-to provide a kind of circuit structure
Interference is strong, to the applicability and good compatibility of communication protocol, message transmission rate can be improved, achievable across clocked data transfer
7816 smart cards and CPU data transmission matching circuit and method.
In order to solve the above technical problems, the present invention adopts the following technical scheme that.
A kind of data transmission matching circuit of 7816 smart card and CPU comprising when thering is cpu clock to generate unit, 7816
Clock generates unit, register interface unit, transmitting line and receives circuit, and the register interface unit is interacted with the CPU
The data of communication, the transmitting line output are transmitted to 7816 smart card, the data transmission that 7816 smart card is sent
To the reception circuit, the data terminal of writing of the register interface unit passes through the transmission FIFO being sequentially connected in series and sends the company of caching
It is connected to the input terminal of the transmitting line, the output end for receiving circuit passes through the reception caching being sequentially connected in series and receives FIFO
It is connected to the reading data terminal of the register interface unit, the cpu clock generates unit and is used to connect for the CPU, register
Mouth unit sends FIFO, transmission caches, reception caches and receives FIFO offer cpu clock signal, the 7816 clock generation list
Member provides 7816 clock signals for caching for the transmitting line, transmission, receiving circuit and receive caching, in which: described to post
Storage interface unit is used for transmission FIFO write-in data, for reading data from the reception FIFO and for described
CPU carries out data access；The transmission FIFO is used to take out data from the register interface unit and be delayed by described send
It deposits and is transmitted to the transmitting line；The transmitting line is used to the data for sending caching output being packaged into 7816 agreement numbers
7816 smart card is sent to after；The data that circuit is received for exporting to 7816 smart card carry out the place that unpacks
After reason, FIFO is cached and received by the reception and is transmitted to the register interface unit；By the transmission FIFO and hair
The mating reaction and the mating reaction for receiving FIFO and the reception caching for sending caching, enable the CPU and described 7816
Smart card is realized across clocked data transfer.
Preferably, the CPU is connect with the register interface unit by data/address bus.
It preferably, include interface multiplexing circuit, the output end of the transmitting line and the input terminal for receiving circuit
It is all connected to the interface multiplexing circuit, the data that the common end of the interface multiplexing circuit is connected to 7816 smart card are drawn
Foot, the interface multiplexing circuit is for providing bidirectional data transfers channel, by described in the order of the bidirectional data transfers channel
7816 smart cards alternatively obtain data to the transmitting line and load data to the reception circuit.
A kind of data transmission matching method of 7816 smart card and CPU, this method is based on circuit realization, the circuit packet
Cpu clock has been included to generate unit, 7816 clock generating units, register interface unit, transmitting line and receive circuit, it is described to post
Storage interface unit is interactively communicated with the CPU, and the data of the transmitting line output are transmitted to 7816 smart card, described
The data that 7816 smart cards are sent are transmitted to the reception circuit, and the register interface unit writes data terminal by successively going here and there
The transmission FIFO and transmission caching that connect are connected to the input terminal of the transmitting line, and the output end for receiving circuit is by successively
The reception caching and reception FIFO of concatenation are connected to the reading data terminal of the register interface unit, and the cpu clock generates single
It is first to be used for as when the CPU, register interface unit, transmission FIFO, transmission cache, reception caches and reception FIFO provides CPU
Clock signal, 7816 clock generating unit are used to provide for the transmitting line, transmission caching, reception circuit and reception caching
7816 clock signals, which comprises data to be sent are loaded on the register by data sending step, the CPU
Interface unit, the transmission FIFO take out data from the register interface unit and are transmitted to by transmission caching described
Transmitting line, the transmitting line data for sending caching output are packaged into after 7816 protocol datas be sent to it is described
7816 smart cards；Data reception step, the data that export to 7816 smart card of circuit that receive unpack after processing,
FIFO is cached and received by the reception and is transmitted to the register interface unit, then is connect by the CPU from the register
Mouth unit takes out data；It is connect by the mating reaction and the reception FIFO of the transmission FIFO and transmission caching with described
The mating reaction for receiving caching enables the CPU and 7816 smart card carry out across clocked data transfer.
Preferably, the caching that sends is from the transmission FIFO data taken out and the reception FIFO from the reception
The data that caching takes out are 8 bit datas.
Preferably, during the data sending step, the CPU first reads the storage state for sending FIFO, and
When the transmission FIFO is non-full state, it is 8 ratios that bit wide, which is written, to the transmission FIFO by the register interface unit
Special data.
Preferably, 7816 clock generating unit is according to the calculating formula of 1ETU to 7816 clocks of 7816 smart card
Signal is divided, and provides tranmitting data register and reception clock, the 1ETU respectively for the transmitting line and the reception circuit
Calculating formula are as follows: 1ETU=(F/D) * (1/f)；Wherein, F is the clock division factor, and D is baud rate Dynamic gene, and f is frequency.
Preferably, transmission caching include 8 bit registers, buffer status monitoring unit and with door, 8 bit
The input terminal of register is connected to the transmission FIFO, and the output end of 8 bit register is connected to the transmitting line, institute
It states buffer status monitoring unit and is connected to 8 bit register, transmitting line and an input terminal with door, it is described
It is connected to the transmission FIFO with another input terminal and output end of door, the buffer status monitoring unit is for obtaining institute
The write state of 8 bit registers is stated, the implementation procedure for sending caching includes: when data enter 8 bit register
When, the buffer status monitoring unit sets 1 data cached effective marker signal to transmitting line transmission；When the transmission
Circuit is completed to transmit completion signal when data are sent to the buffer status monitoring unit feedback data, to enable the buffer status
0 data cached effective marker signal is set in monitoring unit generation；When 8 bit register is empty, the buffer status prison
Control unit sets 1 caching spacing wave to described and door the input terminal load；The transmission FIFO be used for when its non-empty to
1 not empty signal is set in described and door another input terminal load, and described and door exports reading FIFO to the transmission FIFO and enables to believe
Number, data action is read so that transmission caching executes the transmission FIFO；It is described to receive caching and the transmission caching
Implementation procedure is identical, and signal transmission direction is opposite.
Preferably, the caching is transmitted by synchronous circuit between the buffer status monitoring unit and the transmitting line
Data effective marker signal and the data transmit completion signal.
Preferably, the synchronous circuit is the synchronous circuit for including 2 d type flip flops or 3 d type flip flops.
The data transmission matching circuit of 7816 smart card and CPU disclosed by the invention is, it can be achieved that data transmit-receive, sends out in data
Send in step, first by the CPU data to be sent loaded on into the register interface unit, later the transmission FIFO from
The register interface unit takes out data, then is transmitted to the transmitting line by transmission caching, the last transmission
The data for sending caching output are carried out packing processing by circuit, are sent to 7816 intelligence after generating 7816 protocol datas
Card；In data reception step, the circuit that receives first unpack after processing to the data of 7816 smart card output, then
FIFO is cached and received by the reception and is transmitted to the register interface unit, finally by the CPU from the register
Interface unit takes out data.Compared to existing technologies, the present invention makes full use of the transmission FIFO and sends the cooperation of caching
Effect and the mating reaction for receiving FIFO and the reception caching, so that the CPU and 7816 smart card are realized
Across clocked data transfer, and then message transmission rate is improved, and only interference free performance with higher, in addition, of the invention
Circuit structure is simple, more preferable to the applicability and compatibility of communication protocol, therefore is suitably applied the electricity across clock data communication
Road environment.
Detailed description of the invention
Fig. 1 is the charcter topology figure of 7816 interfaces transmission；
Fig. 2 is the composition block diagram of data transmission matching circuit of the present invention；
Fig. 3 is the control flow chart of data transmission procedure；
Fig. 4 is the timing diagram in the excessive situation of the both ends FIFO timing differential；
Fig. 5 is the circuit block diagram for sending caching；
Fig. 6 is the circuit block diagram of two-stage synchronous circuit；
Fig. 7 is the circuit block diagram of three-level synchronous circuit；
Fig. 8 is the control flow chart of DRP data reception process.
Specific embodiment
The present invention is described in more detail with reference to the accompanying drawings and examples.
The invention discloses the data transmission matching circuits of a kind of 7816 smart cards and CPU, refer to Fig. 2 comprising have
Cpu clock generates unit 1,7816 clock generating units 2, register interface unit 3, transmitting line 4 and receives circuit 5, described
Register interface unit 3 is interactively communicated with the CPU6, and the data that the transmitting line 4 exports are transmitted to 7816 smart card
7, the data that 7816 smart card 7 is sent are transmitted to the reception circuit 5, and the register interface unit 3 writes data terminal
The input terminals of the transmitting line 4 are connected to by the transmission FIFO8 and transmission caching 9 that are sequentially connected in series, the reception circuit 5
Output end passes through the reception caching 10 being sequentially connected in series and receives the reading data that FIFO11 is connected to the register interface unit 3
End, it is the CPU6 that the cpu clock, which generates unit 1 and is used for, register interface unit 3, sends FIFO8, sends caching 9, connects
Receive caching 10 and receive FIFO11 provide cpu clock signal, 7816 clock generating unit 2 be used for for the transmitting line 4,
Caching 9 is sent, circuit 5 is received and receives caching 10,7816 clock signals is provided, in which:
The register interface unit 3 is used for transmission FIFO8 write-in data, for reading from the reception FIFO11
Access carries out data access accordingly and for the CPU6；
The transmission FIFO8 is used to take out data from the register interface unit 3 and by 9 transmission of transmission caching
To the transmitting line 4；
The transmitting line 4 is used to after the data for sending 9 output of caching are packaged into 7816 protocol datas be sent to
7816 smart card 7；
The reception circuit 5 is used to carry out unpacking to the data that 7816 smart card 7 exports after processing, is connect by described
It receives caching 10 and receives FIFO11 and be transmitted to the register interface unit 3；
Delay by the transmission FIFO8 with the mating reaction and the reception FIFO11 and described receive for sending caching 9
The mating reaction for depositing 10 enables the CPU6 and 7816 smart card 7 realize across clocked data transfer.
Above-mentioned data transmission matching circuit can realize data transmit-receive, first will be to by the CPU6 in data sending step
The data of transmission load on the register interface unit 3, and the transmission FIFO8 takes from the register interface unit 3 later
Data out, then the transmitting line 4 is transmitted to by transmission caching 9, the last transmitting line 4 caches the transmission
The data of 9 outputs carry out packing processing, are sent to 7816 smart card 7 after generating 7816 protocol datas；It is walked in data receiver
In rapid, the circuit 5 that receives first unpack after processing to the data of 7816 smart card 7 output, then passes through the reception
It caching 10 and receives FIFO11 and is transmitted to the register interface unit 3, finally by the CPU6 from the register interface list
Member 3 takes out data.Compared to existing technologies, the present invention makes full use of the transmission FIFO8 with transmission caching 9 with cooperation
With and it is described receive FIFO11 and the mating reaction for receiving caching 10 so that the CPU6 and 7816 smart card 7
It realizes across clocked data transfer, and then improves message transmission rate, and only interference free performance with higher, in addition, this
Invention circuit structure is simple, more preferable to the applicability and compatibility of communication protocol, therefore is suitably applied across clock data communication
Circuit environment.
In the present embodiment, the CPU6 is connect with the register interface unit 3 by data/address bus.The register connects
Mouth unit 3 works in CPU clock domain.
The present embodiment includes interface multiplexing circuit 12, the output end of the transmitting line 4 and it is described receive circuit 5 it is defeated
Enter end and be all connected to the interface multiplexing circuit 12, the common end of the interface multiplexing circuit 12 is connected to 7816 smart card
7 data pin, the interface multiplexing circuit 12 are logical by the bidirectional data transfers for providing bidirectional data transfers channel
Road enables 7816 smart card 7 alternatively obtain data to the transmitting line 4 and load data to the reception circuit 5.
Wherein, interface multiplexing circuit 12 summarizes the data line of transmitting line and reception circuit, forms a bidirectional data transfers
Channel, and then establish connection with 7816 smart card C7 data pins.
In order to better describe technical solution of the present invention, the invention also discloses the numbers of a kind of 7816 smart cards and CPU
According to transmission matching process, referring to figure 2., this method be based on a circuit realize, the circuit include cpu clock generation unit 1,
7816 clock generating units 2, register interface unit 3, transmitting line 4 and receive circuit 5, the register interface unit 3 with
The CPU6 is interactively communicated, and the data that the transmitting line 4 exports are transmitted to 7816 smart card 7,7816 smart card 7
The data of transmission are transmitted to the reception circuit 5, and the data terminal of writing of the register interface unit 3 passes through the transmission being sequentially connected in series
FIFO8 and transmission caching 9 are connected to the input terminals of the transmitting line 4, and the output end for receiving circuit 5 is by being sequentially connected in series
Reception caching 10 and receive FIFO11 and be connected to the reading data terminals of the register interface unit 3, the cpu clock generates single
Member 1 is used for as the CPU6, register interface unit 3, sends FIFO8, sends caching 9, reception caching 10 and receive FIFO11
Cpu clock signal is provided, 7816 clock generating unit 2 is used for as the transmitting line 4, transmission caching 9, receives circuit 5
7816 clock signals are provided with caching 10 is received, which comprises
Data to be sent are loaded on the register interface unit 3, the transmission by data sending step, the CPU6
FIFO8 takes out data from the register interface unit 3 and is transmitted to the transmitting line 4 by transmission caching 9, described
The data for sending 9 output of caching are packaged into after 7816 protocol datas and are sent to 7816 smart card 7 by transmitting line 4；
Data reception step, the data that export to 7816 smart card 7 of circuit 5 that receive unpack after processing,
It is transmitted to the register interface unit 3 by reception caching 10 and reception FIFO11, then is posted by the CPU6 from described
Storage interface unit 3 takes out data；
Delay by the transmission FIFO8 with the mating reaction and the reception FIFO11 and described receive for sending caching 9
The mating reaction for depositing 10 enables the CPU6 and 7816 smart card 7 carry out across clocked data transfer.
In the above method, it is described send caching 9 from it is described transmission FIFO8 take out data and the reception FIFO11 from
The data for receiving 10 taking-up of caching are 8 bit datas.Wherein, it sends caching and takes out a word from transmission FIFO every time
The data of 8 bits are saved, then are sent by transmitting line, take next byte data again after to be sent.Similarly, it connects
After receiving the reception that the circuit to be received such as caching completes a byte, from the data for taking out 8 bit of byte in circuit are received, send
Enter into reception FIFO.
In actual application, referring to figure 3., the data bit width for sending FIFO is 8 bits, and the depth of FIFO can basis
Resource and the demand of application selection 8,16,32 etc..The data of common cross clock domain, which are transmitted, can directly select asynchronous FIFO, and two
Side inputs the reading clock of different clock-domains and writes clock.But the strategy is in the read-write clock frequency difference mistake at the both ends FIFO
There are problems when big, and referring to figure 4., the clock frequency of 7816 interfaces is very low, under this clock domain, due to the competition of combinational logic
Venture generates burr, will not accidentally be sampled when 7816 clock domains are unsatisfactory for establishing the timing condition of retention time, but due to
7816 clocks and cpu clock frequency difference are huge, when the burr on data line being caused to fully meet foundation holding under cpu clock
Between, therefore can be sampled by CPU, lead to the generation of accidentally sampling situations, seriously affects the accuracy and reliability of data transmission.
In this regard, the present embodiment is accidentally adopted using synchronization fifo and cache unit to handle between CPU and 7816 interface circuits
Sample problem.For sending FIFO and send caching design realization: firstly, the clock for sending FIFO is the cpu clock of high speed, with
It can guarantee that CPU is quickly completed toward FIFO and insert datamation, will not influence system speed.When FIFO is write in CPU generation to be enabled,
First to read the state for sending FIFO, it is ensured that transmission FIFO is non-full, and data are just inserted into FIFO, and the bit wide of data is 8 bits.
It can be seen that the CPU6 first reads the transmission during the embodiment of the present invention data sending step
The storage state of FIFO8, and when the transmission FIFO8 is non-full state, by the register interface unit 3 to the hair
Sending FIFO8 write-in bit wide is the data of 8 bits.
In the present embodiment, 7816 clock generating unit 2 is according to the calculating formula of 1ETU to 7816 smart card 7
7816 clock signals are divided, when providing tranmitting data register and reception respectively for the transmitting line 4 and the receptions circuit 5
Clock, the calculating formula of the 1ETU are as follows:
1ETU=(F/D) * (1/f)；
Wherein, F is the clock division factor, and D is baud rate Dynamic gene, and f is frequency.When the length of one ETU is 1 position
Between, it is to be codetermined by F and D, the two values are provided in the reset answer of communication, and the size of ETU is F/D clock
Period, clock here refer to the clocks of C3 mouthfuls of 7816 smart card inputs, frequency f, Frequency Dividing Factor can be 16,32,
64,128,256,512,31,93,186,372.Default frequency division value divides after 7816 agreements provide interface reset for 372, in 7816
Character is made of 10 continuous ETU, and before the 1st ETU, data line I/O should be in high level, and the 1st ETU should be low
Level, this is the starting bit flag of character, and the 2nd to the 9th ETU is the coding of a byte, and the 10th ETU is this byte
Parity check bit, after the 10th ETU data I/O be still to maintain a period of time high level, the length of high level time
It will be by being provided in reset answer.
In the present embodiment, referring to figure 5., the transmission caching 9 includes 8 bit registers 13, buffer status monitoring list
Member 14 and with door 15, the input terminal of 8 bit register 13 is connected to the transmission FIFO8,8 bit register 13
Output end is connected to the transmitting line 4, the buffer status monitoring unit 14 be connected to 8 bit register 13,
Transmitting line 4 and an input terminal with door 15, another input terminal and output end with door 15 are connected to described
FIFO8 is sent, the buffer status monitoring unit 14 is used to obtain the write state of 8 bit register 13, the transmission
Caching 9 implementation procedure include:
When data enter 8 bit register 13, the buffer status monitoring unit 14 is sent out to the transmitting line 4
Send set 1 data cached effective marker signal；
When the transmitting line 4 is completed to be sent completely when data are sent to 14 feedback data of buffer status monitoring unit
Signal, to enable the generation of buffer status monitoring unit 14 set 0 data cached effective marker signal；
When 8 bit register 13 is empty, the buffer status monitoring unit 14 is defeated to described one with door 15
Enter the caching spacing wave that end load sets 1；
The not empty signal for sending FIFO8 and being used to set 1 to described and door 15 another input terminal load when its non-empty,
Described export with door 15 to the transmission FIFO8 reads FIFO enable signal, so that the transmission caches 9 couples of transmission FIFO8
It executes and reads data action；
Fig. 6 is please referred to, the caching 10 that receives is identical as the implementation procedure for sending caching 9, signal transmission direction phase
Instead.Specifically, the clock for receiving FIFO is that the cpu clock of high speed will first read when CPU generation reading FIFO is enabled and receive FIFO
State, it is ensured that receive FIFO non-empty, just read data from FIFO, the bit wide of data is 8 bits, when receiving caching with CPU
Clock synchronizes the data and data valid bit of 7816 reception circuit outputs, the non-full letter of data valid bit and FIFO after synchronizing
It number carries out generating after with operation writing FIFO enable signal, 8 bit datas after then synchronizing, which are sent into, to be received in FIFO
Complete data transmission.
Referring to figs. 7 and 8, by synchronizing electricity between the buffer status monitoring unit 14 and the transmitting line 4
The data cached effective marker signal is transmitted on road and the data transmit completion signal.Further, the synchronous circuit
It is the synchronous circuit for including 2 d type flip flops 16 or 3 d type flip flops 16.Wherein, the data valid bit of buffer status monitoring
Work will do it signal under CPU clock domain, therefore after transmitting completion signal from the C7 pin under 7816 clock domains and synchronize, synchronous
Circuit is as shown in Figure 7 and Figure 8, two-stage synchronous circuit or three-level synchronous circuit may be selected, sampling clock is cpu clock, above-mentioned
Synchronous circuit can eliminate the metastable state of signal.Likewise, when the data valid bit of buffer status monitoring unit also will be by 7816
Clock signal is sent into 7816 transmitting lines after synchronizing, synchronized using above-mentioned synchronous circuit, and sampling clock is 7816 clocks at this time.
In the data transmission matching circuit and method of a kind of 7816 smart card and CPU disclosed by the invention, using transmission
FIFO and transmission caching, and receive FIFO and receive and cache to realize the data transmission across clock.Wherein, FIFO is worked in
Under the cpu clock of high speed and it is used to improve efficiency of transmission, a data effective monitoring position logic is designed in buffer circuit, is used to
The logic and hair for generating read-write FIFO receive 7816 data controlling signals.Meanwhile the cross clock domain of signal is synchronous in buffer circuit
It is middle to be realized using two-stage or three-level synchronous circuit, it effectively avoids when directlying adopt asynchronous FIFO, read-write both ends clock frequency
Error in data problem caused by rate difference is excessive.Compared to existing technologies, circuit structure of the present invention realizes simple, anti-interference
By force, good to the applicability of agreement and compatibility, it is suitably applied the circuit environment across clock data communication.
The above is preferred embodiments of the present invention, is not intended to restrict the invention, all in technology model of the invention
Interior done modification, equivalent replacement or improvement etc. are enclosed, should be included in the range of of the invention protect.
Claims (10)
1. a kind of data transmission matching circuit of 7816 smart cards and CPU, which is characterized in that include that cpu clock generates unit
(1), 7816 clock generating units (2), register interface unit (3), transmitting line (4) and reception circuit (5), the register
Interface unit (3) is interactively communicated with the CPU (6), and the data of transmitting line (4) output are transmitted to 7816 smart card
(7), the data that 7816 smart card (7) sends are transmitted to the reception circuit (5), the register interface unit (3)
Data terminal is write to pass through the transmission FIFO (8) being sequentially connected in series and send the input terminal that caching (9) is connected to the transmitting line (4),
The output end for receiving circuit (5), which passes through the reception caching (10) being sequentially connected in series and receives FIFO (11), is connected to the deposit
The reading data terminal of device interface unit (3), the cpu clock generate unit (1) and are used to be the CPU (6), register interface unit
(3), FIFO (8) are sent, caching (9), reception caching (10) are sent and receive FIFO (11), cpu clock signal is provided, it is described
7816 clock generating units (2) are used for as the transmitting line (4), send caching (9), receive circuit (5) and receive caching
(10) 7816 clock signals are provided, in which:
The register interface unit (3) is used for the transmission FIFO (8) write-in data, is used for from the reception FIFO (11)
It reads data and carries out data access for the CPU (6)；
The transmission FIFO (8) is used to take out data from the register interface unit (3) and be passed by transmission caching (9)
Transport to the transmitting line (4)；
The transmitting line (4) is used to after the data for sending caching (9) output are packaged into 7816 protocol datas be sent to
7816 smart card (7)；
Reception circuit (5) is used to carry out unpacking to the data that 7816 smart card (7) exports after processing, is connect by described
It receives caching (10) and receives FIFO (11) and be transmitted to the register interface unit (3)；
By the mating reaction of transmission FIFO (8) and transmission caching (9) and the reception FIFO (11) and the reception
The mating reaction for caching (10) enables the CPU (6) and 7816 smart card (7) realize across clocked data transfer.
2. the data transmission matching circuit of 7816 smart card as described in claim 1 and CPU, which is characterized in that the CPU
(6) it is connect with the register interface unit (3) by data/address bus.
3. the data transmission matching circuit of 7816 smart card as described in claim 1 and CPU, which is characterized in that include to connect
Mouth multiplex circuit (12), the output end of the transmitting line (4) and the input terminal for receiving circuit (5) are all connected to described connect
Mouth multiplex circuit (12), the common end of the interface multiplexing circuit (12) are connected to the data pin of 7816 smart card (7),
The interface multiplexing circuit (12) is for providing bidirectional data transfers channel, by described in the order of the bidirectional data transfers channel
7816 smart cards (7) alternatively obtain data to the transmitting line (4) and load data to the reception circuit (5).
4. a kind of data transmission matching method of 7816 smart cards and CPU, which is characterized in that this method is based on circuit realization,
The circuit includes that cpu clock generates unit (1), 7816 clock generating units (2), register interface unit (3), sends electricity
Road (4) and reception circuit (5), the register interface unit (3) interactively communicate with the CPU (6), the transmitting line (4)
The data of output are transmitted to 7816 smart card (7), and the data that 7816 smart card (7) sends are transmitted to the reception electricity
The data terminal of writing on road (5), the register interface unit (3) passes through the transmission FIFO (8) being sequentially connected in series and sends caching (9) even
It is connected to the input terminal of the transmitting line (4), the output end for receiving circuit (5) passes through the reception caching (10) being sequentially connected in series
The reading data terminal of the register interface unit (3) is connected to reception FIFO (11), the cpu clock generates unit (1) and uses
(10) and reception are cached in caching (9) for the CPU (6), register interface unit (3), transmission FIFO (8), transmission, receiving
FIFO (11) provides cpu clock signal, and 7816 clock generating unit (2) is used for as the transmitting line (4), sends caching
(9), circuit (5) are received and receive caching (10), 7816 clock signals are provided, which comprises
Data to be sent are loaded on the register interface unit (3), the transmission by data sending step, the CPU (6)
FIFO (8) takes out data from the register interface unit (3) and is transmitted to the transmitting line by transmission caching (9)
(4), the transmitting line (4) data for sending caching (9) output are packaged into after 7816 protocol datas be sent to it is described
7816 smart cards (7)；
Data reception step, described circuit (5) data that export to 7816 smart card (7) that receive unpack after processing,
It is transmitted to the register interface unit (3) by reception caching (10) and reception FIFO (11), then by the CPU (6)
Data are taken out from the register interface unit (3)；
By the mating reaction of transmission FIFO (8) and transmission caching (9) and the reception FIFO (11) and the reception
The mating reaction for caching (10) enables the CPU (6) and 7816 smart card (7) carry out across clocked data transfer.
5. the data transmission matching method of 7816 smart card as claimed in claim 4 and CPU, which is characterized in that the transmission
The data and the reception FIFO (11) that caching (9) takes out from transmission FIFO (8) cache (10) from the reception and take out
Data be 8 bit datas.
6. the data transmission matching method of 7816 smart card as claimed in claim 4 and CPU, which is characterized in that the data
During sending step, the CPU (6) first reads the storage state for sending FIFO (8), and in the transmission FIFO (8)
When for non-full state, the data that bit wide is 8 bits are written to transmission FIFO (8) by the register interface unit (3).
7. the data transmission matching method of 7816 smart card as claimed in claim 4 and CPU, which is characterized in that described 7816
Clock generating unit (2) divides 7816 clock signals of 7816 smart card (7) according to the calculating formula of 1ETU, for institute
Transmitting line (4) and the reception circuit (5) is stated tranmitting data register is provided respectively and receives clock, the calculating formula of the 1ETU are as follows:
1ETU=(F/D) * (1/f)；
Wherein, F is the clock division factor, and D is baud rate Dynamic gene, and f is frequency.
8. the data transmission matching method of 7816 smart card as claimed in claim 4 and CPU, which is characterized in that the transmission
Caching (9) includes 8 bit registers (13), buffer status monitoring unit (14) He Yumen (15), 8 bit register
(13) input terminal is connected to the transmission FIFO (8), and the output end of 8 bit register (13) is connected to the transmission electricity
Road (4), the buffer status monitoring unit (14) be connected to 8 bit register (13), transmitting line (4) and with
One input terminal of door (15), another input terminal and output end with door (15) are connected to the transmission FIFO (8),
The buffer status monitoring unit (14) is used to obtain the write state of 8 bit register (13), and the transmission caches (9)
Implementation procedure include:
When data enter 8 bit register (13), buffer status monitoring unit (14) the Xiang Suoshu transmitting line (4)
1 data cached effective marker signal is set in transmission；
It is sent completely when data are sent to buffer status monitoring unit (14) feedback data when the transmitting line (4) are completed
Signal, to enable buffer status monitoring unit (14) generation set 0 data cached effective marker signal；
When 8 bit register (13) is empty, the buffer status monitoring unit (14) is to one with door (15)
1 caching spacing wave is set in input terminal load；
The not empty signal for sending FIFO (8) and being used to set 1 to described and door (15) another input terminal load when its non-empty,
Described export with door (15) to the transmission FIFO (8) reads FIFO enable signal, so that transmission caching (9) is to the transmission
FIFO (8), which is executed, reads data action；
The reception caching (10) is identical as the transmission caching implementation procedure of (9), and signal transmission direction is opposite.
9. the data transmission matching method of 7816 smart card as claimed in claim 4 and CPU, which is characterized in that the caching
The data cached effective marker signal is transmitted by synchronous circuit between condition monitoring unit (14) and the transmitting line (4)
And the data transmit completion signal.
10. the data transmission matching method of 7816 smart card as claimed in claim 9 and CPU, which is characterized in that the synchronization
Circuit is the synchronous circuit for including 2 d type flip flops (16) or 3 d type flip flops (16).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811369686.6A CN109582618A (en) | 2018-11-17 | 2018-11-17 | A kind of the data transmission matching circuit and method of 7816 smart card and CPU |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811369686.6A CN109582618A (en) | 2018-11-17 | 2018-11-17 | A kind of the data transmission matching circuit and method of 7816 smart card and CPU |
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Application publication date: 20190405 |