CN109558170B - 一种支持数据级并行和多指令融合的二维数据通路架构 - Google Patents
一种支持数据级并行和多指令融合的二维数据通路架构 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
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Citations (9)
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CN103019656B (zh) * | 2012-12-04 | 2016-04-27 | 中国科学院半导体研究所 | 可动态重构的多级并行单指令多数据阵列处理系统 |
US9712185B2 (en) * | 2012-05-19 | 2017-07-18 | Olsen Ip Reserve, Llc | System and method for improved fractional binary to fractional residue converter and multipler |
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2018
- 2018-11-06 CN CN201811314543.5A patent/CN109558170B/zh active Active
Patent Citations (9)
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US5237667A (en) * | 1987-06-05 | 1993-08-17 | Mitsubishi Denki Kabushiki Kaisha | Digital signal processor system having host processor for writing instructions into internal processor memory |
WO2001009717A1 (en) * | 1999-08-02 | 2001-02-08 | Morton Steven G | Video digital signal processor chip |
US8725990B1 (en) * | 2004-11-15 | 2014-05-13 | Nvidia Corporation | Configurable SIMD engine with high, low and mixed precision modes |
CN101174200B (zh) * | 2007-05-18 | 2010-09-08 | 清华大学 | 一种具有五级流水线结构的浮点乘加融合单元 |
CN102508643A (zh) * | 2011-11-16 | 2012-06-20 | 刘大可 | 一种多核并行数字信号处理器及并行指令集的运行方法 |
CN102707931A (zh) * | 2012-05-09 | 2012-10-03 | 刘大可 | 一种基于并行数据通道的数字信号处理器 |
US9712185B2 (en) * | 2012-05-19 | 2017-07-18 | Olsen Ip Reserve, Llc | System and method for improved fractional binary to fractional residue converter and multipler |
CN103019656B (zh) * | 2012-12-04 | 2016-04-27 | 中国科学院半导体研究所 | 可动态重构的多级并行单指令多数据阵列处理系统 |
CN105468335A (zh) * | 2015-11-24 | 2016-04-06 | 中国科学院计算技术研究所 | 流水级运算装置、数据处理方法及片上网络芯片 |
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Title |
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High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4;Per Karlstrom 等;《2006 NORCHIP》;20070312;第31-34页 * |
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