CN1095570C - Extending method for interconnect network of large-scale parallel processing computer systems - Google Patents
Extending method for interconnect network of large-scale parallel processing computer systems Download PDFInfo
- Publication number
- CN1095570C CN1095570C CN 98120058 CN98120058A CN1095570C CN 1095570 C CN1095570 C CN 1095570C CN 98120058 CN98120058 CN 98120058 CN 98120058 A CN98120058 A CN 98120058A CN 1095570 C CN1095570 C CN 1095570C
- Authority
- CN
- China
- Prior art keywords
- node
- network
- port
- super
- interconnection network
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Multi Processors (AREA)
Abstract
The present invention relates to a network expanding method of a novel interconnection network of a massively parallel processing computer system, which is characterized in that super nodes in the interconnection network are interconnected by using routers instead of high-speed buses; each of 2n ports of the routers making the super nodes interconnected needs to be connected with other 2n-1 ports.
Description
The invention provides a kind of large-scale parallel processing computer systems interconnection network, be meant a kind of new interconnection network of large-scale parallel processing computer systems especially.
The inventor has applied for patent " the new interconnection network technology of large-scale parallel processing computer systems " (number of patent application is 97116994.2) before this; The new interconnection network of being invented is to put forward on the basis of the advantage of comprehensive inverted graph interconnection network and cross bar switch (or high-speed bus), and its principle is 4 yuan of known two-dimentional new interconnection network block diagrams as shown in Figure 1.Network among the figure is 4 yuan of two-dimentional new interconnection networks, and horizontal line and vertical line are represented network channel, for example CC.The stain at the place, point of crossing of horizontal network channel and perpendicular network channel is router, for example R03.Router can be delivered to the destination with received data according to routing algorithm and routing mechanism.
Each router among Fig. 1 has four ports, links to each other with the network channel of its upper and lower, left and right respectively.The processor node that circle among Fig. 1 is represented, for example N000, N331.The processor node is called for short node.Node is connected on the network channel.Dotted line among Fig. 1 represents that 4 nodes of delegation or row are by cross bar switch (or high-speed bus) interconnection, for example CSX0 or CSY0.Node has 3 ports, as shown in Figure 21,2,3, Fig. 2 is three known port node synoptic diagram.Port one connects cross bar switch (or high-speed bus), and port 2 and port 3 be the network channel CC of binding place both sides respectively.
Patent " the new interconnection network technology of large-scale parallel processing computer systems " not only the network delay time short, and the n of the node quantity that interconnected for the conventional K n of unit cube interconnection network of the node quantity that is interconnected is doubly.
The K n of a unit cube new interconnection network can be considered a super node, and a plurality of super nodes can be formed larger new interconnection network, and the nodal point number that is interconnected can increase more.Making 4 yuan of two-dimentional new interconnection networks among Fig. 1 is a super node, 16 super nodes can be formed 16 yuan of two-dimentional new interconnection networks, corresponding node in the super node can interconnect with high-speed bus, as shown in Figure 3, be the schematic block diagram of the corresponding node in the known super node by the high-speed bus interconnection.Dotted line grid among the figure is represented super node (for example SN00), and 32 nodes (delegation and a row node, totally 8 nodes only draw) are arranged in each super node.The high-speed bus that connects super node represents with thick line, for example HSBX0.Node in the super node represents with small circle, for example N301.The cross bar switch (or high-speed bus) that connects 4 nodes of super node inside represents with fine rule, for example CSX3.The nodal point number that new interconnection network connected after the expansion rises to original 16 times, promptly expands to 512 from 32.
As can be seen, in this super node interconnecting scheme, in order to connect the high-speed bus between the super node, node need increase a port, promptly is increased to 4 ports from 3 ports, thereby the complexity of node is increased, in addition, the interconnection between the super node also needs to increase a lot of high-speed buses.
The objective of the invention is to, a kind of new interconnection network of large-scale parallel processing computer systems is provided, make the interconnect simplification between the super node in " the new interconnection network technology of large-scale parallel processing computer systems ".
The invention provides a kind of new interconnection network of large-scale parallel processing computer systems, comprise a plurality of super nodes; Each super node comprises a plurality of processor nodes, and these processor nodes are connected on the network channel, uses K * K cross bar switch or high-speed bus interconnection respectively with K processor node on delegation and the same row network channel; It is characterized in that: the super node in the interconnection network is by interconnection of routers; Router has 2n port, and n represents the dimension of interconnection network, and each port can link to each other with other 2n-1 port; Router can be realized by cross bar switch.
Below in conjunction with accompanying drawing the present invention is made a detailed description for further specifying principle of the present invention, feature and implementation method, wherein:
Fig. 1 is 4 yuan of known two-dimentional new interconnection network block diagrams;
Fig. 2 is three known port node synoptic diagram;
Fig. 3 is the synoptic diagram of corresponding node by the high-speed bus interconnection in the known super node;
Fig. 4 is the arrangement synoptic diagram of known 4 super nodes;
Fig. 5 is the synoptic diagram of the interconnection of 4 super nodes of the present invention;
Fig. 6 is the router feature synoptic diagram of the super node inside of known two-dimentional new interconnection network;
Fig. 7 is the router feature synoptic diagram between the super node of two-dimentional new interconnection network of the present invention;
Fig. 8 is 64 known new interconnection network synoptic diagram that super node is formed.
The present invention is the improvement of the interconnection technique of the super node in the patent " the new interconnection network technology of large-scale parallel processing computer systems " (number of patent application is 97116994.2) in first to file.Make super node in the patent " the new interconnection network technology of large-scale parallel processing computer systems " by interconnection of routers, rather than interconnect by high-speed bus.For two-dimentional new interconnection network, the arrangement of 4 super nodes can be as shown in Figure 4, and the SN00 among the figure, SN01, SN10 and SN11 are super node.
The connection of 4 super nodes of the present invention as shown in Figure 5.Circle among the figure is represented node (for example N000), and thick line is represented cross bar switch (for example CSX00).Pore is represented the router (for example R62) of super node inside, its functional schematic as shown in Figure 6, it need only finish the transmission of data between horizontal network channel X and perpendicular network channel Y.Big stain among Fig. 5 is represented the router (for example SR73) between the super node, its functional schematic as shown in Figure 7, it can make data transmit in any direction.
Just the super node in the interconnection network is by interconnection of routers, rather than by high-speed bus interconnection, and each port need in 2n the port of router of super node interconnecting be linked to each other with other 2n-1 port.
If super node is a K unit cube new interconnection network, a plurality of so super nodes can be formed a larger cube new interconnection network.Fig. 8 is interconnection network of being made up of 64 super nodes, and each small cubes among the figure is represented super node, for example a SN030.
The port number of router is 2n, and n represents the dimension of interconnection network.For the router of super node inside, its individual port of each port and 2 (n-1) links to each other; For the router between the super node, its each port links to each other with 2n-1 port.
The port number of the router of two dimension new interconnection network is 4, and for the router of super node inside, each port only needs the port adjacent with two other to link to each other; For the router between the super node, each port will link to each other with other 3 ports.
The port number of the router of three-dimensional new interconnection network is 6, and for the router of super node inside, each port will link to each other with other 4 ports; For the router between the super node, each port will link to each other with other 5 ports.
The router of three-dimensional new interconnection network is complicated more a lot of than two dimension, can be realized by cross bar switch.
Claims (1)
1, a kind of new interconnection network of large-scale parallel processing computer systems comprises a plurality of super nodes; Each super node comprises a plurality of processor nodes, and these processor nodes are connected on the network channel, uses K * K cross bar switch or high-speed bus interconnection respectively with K processor node on delegation and the same row network channel; It is characterized in that: the super node in the interconnection network is by interconnection of routers; Router has 2n port, and n represents the dimension of interconnection network, and each port can link to each other with other 2n-1 port; Router can be realized by cross bar switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98120058 CN1095570C (en) | 1998-09-29 | 1998-09-29 | Extending method for interconnect network of large-scale parallel processing computer systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98120058 CN1095570C (en) | 1998-09-29 | 1998-09-29 | Extending method for interconnect network of large-scale parallel processing computer systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1249472A CN1249472A (en) | 2000-04-05 |
| CN1095570C true CN1095570C (en) | 2002-12-04 |
Family
ID=5226581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 98120058 Expired - Fee Related CN1095570C (en) | 1998-09-29 | 1998-09-29 | Extending method for interconnect network of large-scale parallel processing computer systems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1095570C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330413B (en) * | 2007-06-22 | 2012-08-08 | 上海红神信息技术有限公司 | Method for expanding mixed multi-stage tensor based on around network and ultra-cube network structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102404409B (en) * | 2011-12-12 | 2015-02-04 | 东南大学 | Equivalent cloud network system based on optical packet switch |
-
1998
- 1998-09-29 CN CN 98120058 patent/CN1095570C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330413B (en) * | 2007-06-22 | 2012-08-08 | 上海红神信息技术有限公司 | Method for expanding mixed multi-stage tensor based on around network and ultra-cube network structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1249472A (en) | 2000-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bertsekas et al. | Optimal communication algorithms for hypercubes | |
| Wittie | Communication structures for large networks of microcomputers | |
| US5521591A (en) | Switching networks with expansive and/or dispersive logical clusters for message routing | |
| US5715391A (en) | Modular and infinitely extendable three dimensional torus packaging scheme for parallel processing | |
| Kesavan et al. | Multicast on irregular switch-based networks with wormhole routing | |
| CN101335704B (en) | Adaptive routing method without dead lock in three-dimensional torus network | |
| KR20140139032A (en) | A packet-flow interconnect fabric | |
| CN101232456A (en) | Distributed type testing on-chip network router | |
| EP1222557B1 (en) | Network topology for a scalable multiprocessor system | |
| Libeskind-Hadas et al. | Tree-based multicasting in wormhole-routed irregular topologies | |
| Minkenberg et al. | Performance benefits of optical circuit switches for large-scale dragonfly networks | |
| Obaidat et al. | Learning automata-based bus arbitration for shared-medium ATM switches | |
| CN1095570C (en) | Extending method for interconnect network of large-scale parallel processing computer systems | |
| Boppana et al. | Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks | |
| Ni | Issues in Designing Truly Scalable Interconnection Networks. | |
| CN114116596A (en) | Dynamic relay-based infinite routing method and architecture for neural network on chip | |
| CN108768864B (en) | Data center network topology system easy to expand and high in fault tolerance | |
| Leighton et al. | Empirical evaluation of randomly-wire multistage networks | |
| CN1085361C (en) | Interconnection network technology for large scale parallel processing computer system | |
| CN1431808A (en) | Large capacity and expandable packet switching network structure | |
| CN1047743A (en) | Processor unit networks | |
| KR19980020693A (en) | Broadcast transmission method in multi-tag hierarchical interconnection network | |
| CN104579786A (en) | Server design method based on fusion and 2D Torus network topology framework | |
| Valerio et al. | Fault-tolerant orthogonal fat-trees as interconnection networks | |
| Arruabarrena et al. | A performance evaluation of adaptive routing in bidimensional cut-through networks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |