CN109547146A - A kind of Wireless clock synchronous method and device based on super broad band radio communication - Google Patents
A kind of Wireless clock synchronous method and device based on super broad band radio communication Download PDFInfo
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- CN109547146A CN109547146A CN201910032800.4A CN201910032800A CN109547146A CN 109547146 A CN109547146 A CN 109547146A CN 201910032800 A CN201910032800 A CN 201910032800A CN 109547146 A CN109547146 A CN 109547146A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0611—PN codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
Abstract
This application provides a kind of Wireless clock synchronous method and device based on super broad band radio communication, belong to field of communication technology, the method is applied to the slave node in the wireless sensor network based on Ultra-wideband Communication Technology, the wireless sensor network further includes host node, the described method includes: when receiving the synchronization packets of host node transmission, receiving time stamp is generated, synchronization packets carry sending time stamp；Obtain the signal expression of the reference clock signal of host node, and according to receiving time stamp, sending time stamp, the signal expression of reference clock signal and the clock signal from node signal expression, calculate the phase difference between the clock signal of node and the reference clock signal of host node；According to phase difference and preset compensating controller, control amount is calculated；According to control amount, the frequency from the clock signal of node is adjusted.Using the application, the synchronization accuracy of each network node in wireless sensor network can be improved.
Description
Technical field
This application involves fields of communication technology, synchronous more particularly to a kind of Wireless clock based on super broad band radio communication
Method and device.
Background technique
In wireless sensor network, had differences between the crystal oscillator for including due to different network node and vulnerable to environmental factor
Influence therefore can have frequency and phase between the clock signal that the crystal oscillator of different network node generates and reference clock signal
Position drift, for guarantee wireless sensor network effective work, need to network node each in wireless sensor network when
Clock signal synchronizes.
In the prior art, it can be synchronized, be had based on clock signal of the Bluetooth wireless technology to each network node
Body treatment process includes: the synchronization packets that each of wireless sensor network can receive host node transmission from node, together
Step data packet carries sending time stamp；Then, receiving time stamp can be generated after receiving synchronization packets from node；It
Afterwards, it can be stabbed from node according to sending time and receiving time is stabbed, calculate the compensation rate of clock signal, and according to the compensation rate tune
The frequency for saving clock signal, hereby it is achieved that the synchronization of the clock signal of each network node.
However, the bandwidth of Bluetooth wireless technology is limited, can not accurate recording synchronism data packet sending time stamp
It is stabbed with receiving time, causes the synchronization accuracy of each network node in wireless sensor network low.
Summary of the invention
The embodiment of the present application be designed to provide a kind of Wireless clock synchronous method based on super broad band radio communication and
Device, to realize the synchronization accuracy for improving each network node in wireless sensor network.Specific technical solution is as follows:
In a first aspect, providing a kind of Wireless clock synchronous method based on super broad band radio communication, the method application
Slave node in the wireless sensor network based on Ultra-wideband Communication Technology, the wireless sensor network further include main section
Point, which comprises
When receiving the synchronization packets that the host node is sent, receiving time stamp is generated, the synchronization packets are taken
It is stabbed with sending time；
The signal expression of the reference clock signal of the host node is obtained, and according to receiving time stamp, the hair
The signal expression of timestamp, the signal expression of the reference clock signal and the clock signal from node is sent, is counted
Calculate the phase difference between the clock signal from node and the reference clock signal of the host node；
According to the phase difference and preset compensating controller, control amount is calculated, the compensating controller includes ratio tune
Section and integral adjustment PI controller；
According to the control amount, the frequency of the clock signal from node is adjusted.
Optionally, the expression formula of the phase difference are as follows:
Wherein, describedTo be described from node
Phase when kth time receives the synchronization packets, between the clock signal and the reference clock signal from node
Difference, the k0For voltage-controlled coefficient, the u (k) receives the control generated after the synchronization packets from node kth time to be described
Amount, the TsynFor preset synchronizing cycle, the Δ f be the clock signal from node and the reference clock signal it
Between difference on the frequency；
The expression formula of the control amount are as follows:Wherein, described
kpFor preset proportionality coefficient, the kiFor preset integral coefficient.
Optionally, when the sending time stamp stabs for the sending time of the last synchronization packets received, described
According to receiving time stamp, sending time stamp, the signal expression of the reference clock signal and described from node
The signal expression of clock signal calculates between the clock signal from node and the reference clock signal of the host node
Phase difference includes:
According to sending time stamp, the receiving time stamp, the benchmark of the synchronization packets that the last time receives
The signal expression of the signal expression of clock signal and the clock signal from node, calculate it is described from node when
Phase difference between clock signal and the reference clock signal of the host node.
Optionally, the expression formula of the phase difference are as follows:
Its
In, it is describedFor it is described receive the synchronization packets from node kth time when, the clock signal from node with
Phase difference between the reference clock signal, the k0For voltage-controlled coefficient, the u (k-1) is described to connect for -1 time from node kth
Receive the control amount generated after the synchronization packets, the TsynFor preset synchronizing cycle, the Δ f is described from node
Clock signal and the reference clock signal between difference on the frequency, the τ is delay time, and the delay time includes described
Time needed for calculating the control amount after receiving synchronization packets from node.
Optionally, it is described according to the phase difference and preset when the packet loss of the synchronization packets is default value
Compensating controller, calculating control amount includes:
According to the phase difference, the packet loss and preset compensating controller, control amount is calculated.
Optionally, the expression formula of the control amount isWherein, institute
State kpFor preset proportionality coefficient, the kiIt is described for preset integral coefficientIt is describedS (k)=0
It indicates described and does not receive the synchronization packets from node, the s (k)=1 indicates described and receives the synchronization from node
Data packet.
Optionally, the method also includes:
Based on the phase difference and the control amount, synchronous feedback system M is established, the expression formula of the M is
Wherein, described
It is describedIt is describedThe u (k) is described
When receiving synchronization packets from node kth time, the control amount being calculated, the s (k) for indicate it is described from node whether
Synchronization packets are received, the w (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, the W
For preset scalar matrix；
Judging whether there is meets the synchronous feedback system M's
Scalar matrix
If there is the scalar matrix, it is determined that the synchronous feedback system is stablized.
Second aspect provides a kind of Wireless clock synchronizing device based on super broad band radio communication, described device application
Slave node in the wireless sensor network based on Ultra-wideband Communication Technology, the wireless sensor network further include main section
Point, described device include:
Generation module, it is described for when receiving the synchronization packets that the host node is sent, generating receiving time stamp
Synchronization packets carry sending time stamp；
First computing module, the signal expression of the reference clock signal for obtaining the host node, and according to described
Receiving time stamp, the sending time stamp, the reference clock signal signal expression and it is described from the clock of node believe
Number signal expression, calculate the phase between the clock signal from node and the reference clock signal of the host node
Difference；
Second computing module, for calculating control amount, the compensation according to the phase difference and preset compensating controller
Controller includes proportion adjustment and integral adjustment PI controller；
Adjustment module, for adjusting the frequency of the clock signal from node according to the control amount.
Optionally, the expression formula of the phase difference are as follows:
Wherein, describedTo be described from node
Phase when kth time receives the synchronization packets, between the clock signal and the reference clock signal from node
Difference, the k0For voltage-controlled coefficient, the u (k) receives the control generated after the synchronization packets from node kth time to be described
Amount, the TsynFor preset synchronizing cycle, the Δ f be the clock signal from node and the reference clock signal it
Between difference on the frequency；
The expression formula of the control amount are as follows:Wherein, described
kpFor preset proportionality coefficient, the kiFor preset integral coefficient.
Optionally, sending time stamp for the last synchronization packets received sending time stamp when, described the
One computing module includes:
The sending time of first computational submodule, the synchronization packets for being received according to the last time stabs, is described
The signal expression of receiving time stamp, the signal expression of the reference clock signal and the clock signal from node,
Calculate the phase difference between the clock signal from node and the reference clock signal of the host node.
Optionally, the expression formula of the phase difference are as follows:
Wherein,
It is describedFor it is described receive the synchronization packets from node kth time when, the clock signal from node with it is described
Phase difference between reference clock signal, the k0For voltage-controlled coefficient, the u (k-1) is described to receive for -1 time from node kth
The control amount generated after the synchronization packets, the TsynFor preset synchronizing cycle, the Δ f be it is described from node when
Difference on the frequency between clock signal and the reference clock signal, the τ are delay time, and the delay time includes described from section
Put the time needed for calculating the control amount after receiving synchronization packets.
Optionally, when the packet loss of the synchronization packets is default value, second computing module includes:
Second computational submodule, for according to the phase difference, the packet loss and preset compensating controller, meter
Calculate control amount.
Optionally, the expression formula of the control amount isWherein, institute
State kpFor preset proportionality coefficient, the kiIt is described for preset integral coefficientIt is describedS (k)=0
It indicates described and does not receive the synchronization packets from node, the s (k)=1 indicates described and receives the synchronization from node
Data packet.
Optionally, described device further include:
Module is established, for being based on the phase difference and the control amount, establishes synchronous feedback system M, the expression of the M
Formula is
Wherein, describedIt is described
It is describedThe u (k) is
Described when receiving synchronization packets from node kth time, the control amount being calculated, the s (k) is for indicating described from node
Whether synchronization packets are received, and the w (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, institute
Stating W is preset scalar matrix；
Judgment module meets the synchronous feedback system M for judging whether there is
Scalar matrix
Determining module, for when there are the scalar matrix, determining that the synchronous feedback system is stablized.
The third aspect provides a kind of electronic equipment, including processor, communication interface, memory and communication bus,
In, processor, communication interface, memory completes mutual communication by communication bus；
Memory, for storing computer program；
Processor when for executing the program stored on memory, realizes method and step described in any first aspect.
Fourth aspect provides a kind of computer readable storage medium, which is characterized in that the computer-readable storage medium
Computer program is stored in matter, the computer program realizes that method described in any first aspect walks when being executed by processor
Suddenly.
A kind of Wireless clock synchronous method and device based on super broad band radio communication provided by the embodiments of the present application, can be with
When receiving the synchronization packets of host node transmission, receiving time stamp is generated；Then, according to receiving time stamp, synchrodata
The signal expression of sending time stamp, the signal expression of reference clock signal and the clock signal from node that packet carries,
Calculate the phase difference between the clock signal of node and the reference clock signal of host node；Later, according to phase difference and compensation
Controller calculates control amount, finally according to control amount, adjusts the frequency from the clock signal of node.Due to being based on ultra-wide band logical
Letter technology carries out clock and synchronizes, and can be stabbed with accurate recording sending time and receiving time is stabbed, therefore, can be improved wireless sensor
The synchronization accuracy of each network node in network.
Certainly, implement the application any product or method it is not absolutely required to and meanwhile reach all the above excellent
Point.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of method of the Wireless clock synchronous method based on super broad band radio communication provided by the embodiments of the present application
Flow chart；
Fig. 2 is a kind of schematic diagram of markovian state transition diagram provided by the embodiments of the present application；
Fig. 3 is a kind of method of the Wireless clock synchronous method based on super broad band radio communication provided by the embodiments of the present application
Flow chart；
Fig. 4 a be a kind of Wireless clock synchronous method based on super broad band radio communication provided by the embodiments of the present application when
Sequence schematic diagram；
Fig. 4 b is a kind of system framework schematic diagram of indoor distribution node provided by the embodiments of the present application；
Fig. 5 is a kind of structure of the Wireless clock synchronizing device based on super broad band radio communication provided by the embodiments of the present application
Schematic diagram；
Fig. 6 is the structural schematic diagram of a kind of electronic equipment provided by the embodiments of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
The embodiment of the present application provides a kind of Wireless clock synchronous method based on super broad band radio communication, this method application
Slave node in the wireless sensor network based on Ultra-wideband Communication Technology, can be from node with sensing function, data
The electronic equipment of processing function and communication function may include vibrating sensor or temperature sensor from node.Wireless sensing
Device network further includes host node, and host node can be the electronic equipment with data processing function and communication function.It is used from node
In to collected data information carry out data processing and will treated that data information is sent to host node, then, main section
Point can dynamically manage entire wireless sensor network by receiving the data information respectively sent from node.
In the embodiment of the present application, wireless sensor network is the network using Ultra-wideband Communication Technology, ultra-wideband communications skill
Art is a kind of no-load communication techniques, transmits data using the extremely short pulse of non-sinusoidal waveform, the order magnitude range of pulse width is being received
Second and picosecond between, the bandwidth of pulse can achieve several GHz, therefore, can accurate logging timestamp.Ultra-wideband Communication Technology
Data are transmitted based on extremely short pulse, on the one hand, transmission power very little needed for transmitting extremely short pulse only sends continuous carry at present
More than one the percent of the transmission power of wave signal；On the other hand, message transmission rate can achieve 480Mbps (Mbit/s, million ratios
It is special per second), it is 159 times of the message transmission rate of Bluetooth wireless technology, is WI-FI (Wireless Fidelity, nothing
Gauze network) 18.5 times of standard data rate；Therefore, Ultra-wideband Communication Technology is highly suitable for the biography of mass data
It is defeated.
As shown in Figure 1, the concrete processing procedure of this method includes:
Step 101, when receiving the synchronization packets of host node transmission, receiving time stamp is generated.
In an implementation, host node can according to preset synchronizing cycle, at least one of wireless sensor network from
Node sends synchronization packets, and synchronization packets are the data packets for realizing clock signal synchronization, when can carry transmission
Between stab.Synchronization packets can be realized by the existing communication data packet for realizing inter-node communication.
Each of wireless sensor network can be while receiving the synchronization packets that host node is sent from node, note
Record receives the time of the synchronization packets, obtains the receiving time stamp of the synchronization packets.Same step number can also be obtained from node
The sending time stamp carried according to packet.
In the embodiment of the present application, host node generates sending time stamp and generates the specific mistake that receiving time is stabbed from node
Journey is the prior art, and details are not described herein again.
Step 102, when obtaining the signal expression of the reference clock signal of host node, and stabbing, send according to receiving time
Between stamp, the signal expression of reference clock signal and the clock signal from node signal expression, calculate from node when
Phase difference between clock signal and the reference clock signal of host node.
In an implementation, synchronization packets be can parse from node, determines the signal representation of the reference clock signal of host node
Formula.It in a kind of feasible implementation, can parse a certain synchronization packets from node, obtain the reference clock letter of host node
Number signal expression then the signal expression is being locally stored, and in subsequently received synchronization packets, obtain this
The signal expression of the reference clock signal of ground storage.
Then, can be stabbed from node according to the sending time of the receiving time of synchronization packets stamp, the synchronization packets,
The signal expression of reference clock signal and should from the signal expression of node current clock signal, calculate from node when
Phase difference between clock signal and the reference clock signal of host node.
The embodiment of the present application provide it is a kind of from node according to the receiving time of the synchronization packets stamp, the synchronization packets
Sending time stamp, reference clock signal signal expression and should be from the signal expression of node current clock signal, meter
Calculate the process of the phase difference between the clock signal of node and the reference clock signal of host node.
In one implementation, the reference clock signal y of the host node obtained from nodemSignal expression can be with
Are as follows:
ym(t)=A1cos(2πfmt) (1)
Wherein, A1For the signal amplitude of benchmark clock signal, fmFor the frequency of the reference clock signal of host node, t is wireless
The runing time of sensor network.
From node current clock signal ysSignal expression are as follows:
Wherein, A1For from the signal amplitude of the clock signal of node, fsFor from the frequency of the clock signal of node, k0For pressure
Control coefficient, for reflect voltage controlled oscillator output clock signal frequency to the susceptibility of control amount,For initial phase, u
(z) input voltage of the voltage controlled oscillator changed over time is indicated.It can be calculated from node according to formula (1) and formula (2) from node
Clock signal and host node reference clock signal between phase differenceIt obtains:
Wherein, Δ f=fs-fmFor the difference on the frequency between the clock signal of node and the reference clock signal of host node.
It is T when synchronizing cyclesynWhen, when host node kth time sends synchronization packets, when transmission can be generated in host node
Between stab, by time TdIt can receive from node to the synchronization packets, and generate receiving time stamp.It is received from node kth time
Phase difference when to synchronization packets, between the clock signal of node and the reference clock signal of host nodeThat is formula (3)
It can be expressed as follows:
Wherein,The phase of corresponding reference clock signal is stabbed for sending time,It is stabbed for receiving time corresponding
The phase of clock signal.
Step 103, according to phase difference and preset compensating controller, control amount is calculated.
Wherein, compensating controller can be previously provided with from node, compensating controller includes PI (Proportion
Integration proportion adjustment and integral adjustment) controller.Compensating controller can also be PID (Proportion
Integration Differentiation, proportional integral differential are adjusted) controller.
In an implementation, phase difference can be input in compensating controller from node, calculates the control amount of compensating controller.
In a kind of feasible implementation, control amount can be the input voltage value of voltage controlled oscillator.
The embodiment of the present application is based on compensating controller and realizes that clock is synchronous, and the stationary problem of each node clock signal is converted
For control problem.It selects PI controller as compensating controller, there is very wide frequency lock-in range, and convenient for by existing
Control of the PI controller control software realization to PI controller.
In the embodiment of the present application, from node can the expression formula (3) based on phase difference, calculating receive+1 synchronization of kth
When data packet, it is added to the control amount at voltage controlled oscillator both ends.
The expression formula of control amount can also indicate are as follows:
Wherein, kpFor preset proportionality coefficient, kiFor preset integral coefficient.
When receiving synchronization packets from node kth+1 time, the reference clock of clock signal and host node from node is believed
Phase difference between numberExpression formula are as follows:
Wherein, u (k) is to receive the control amount generated after synchronization packets from node kth time.Based on formula (5) and formula
(6), a closed-loop control system can be constructed from node.
Step 104, according to control amount, the frequency from the clock signal of node is adjusted.
In an implementation, control amount can be set to the input voltage from the voltage controlled oscillator of node from node, by changing
The input voltage of voltage controlled oscillator adjusts the frequency from the clock signal of node.
It, can be when receiving the synchronization packets that host node is sent, when generating reception from node in the embodiment of the present application
Between stab；Then, according to receiving time stamp, synchronization packets carry sending time stamp, reference clock signal signal expression,
And the signal expression of the clock signal from node, calculate from the reference clock signal of the clock signal of node and host node it
Between phase difference；Later, according to phase difference and compensating controller, control amount is calculated, finally according to control amount, is adjusted from node
The frequency of clock signal.It is synchronized due to carrying out clock based on Ultra-wideband Communication Technology, can stab and connect with accurate recording sending time
Timestamp is received, so as to ensure the phase difference and corrected accuracy based on timestamp calculating clock signal.
In the prior art, uncomfortable due to limited from the memory space of node and computing capability in wireless sensor network
In the synchronized algorithm of storage mass data, the existing complexity of operation, lead to each network node in wireless sensor network synchronizes essence
Spend low, synchronization accuracy is only capable of reaching musec order.Clock synchronizing method provided by the embodiments of the present application can mention synchronization accuracy
Magnitude of subnanosecond is risen to, has the characteristics that structure is simple, low in energy consumption and with high accuracy, is highly suitable for wireless sensor network,
The performance of wireless sensor network can significantly be promoted.
Optionally, wireless sensor network is in the process of running, it is understood that there may be network delay.For example, it may be possible to can have number
According to transmission delay, in a kind of feasible implementation, since host node is after sending a certain synchronization packets, could generate should
The sending time of synchronization packets is stabbed, and next synchronization packets comprising sending time stamp can be generated in host node, and will
Next synchronization packets are sent to respectively from node.There is likely to be data processing delays, in a kind of feasible implementation,
From node after receiving synchronization packets, need through can just calculate control amount after a period of time.
Therefore, it can be based on network delay from node, to the reference clock signal of clock signal and host node from node
Between phase difference and control amount be modified.
Optionally, the sending time stamp that current sync data packet carries is the transmission of the last synchronization packets received
When timestamp, from the specific of the phase difference between the reference clock signal that node calculates the clock signal and host node from node
Process includes: the signal representation according to the sending time of upper synchronization packets stamp, receiving time stamp, reference clock signal
The signal expression of formula and the clock signal from node calculates and believes from the clock signal of node and the reference clock of host node
Phase difference between number.
In an implementation, the reception of current sync data packet can be generated when receiving current sync data packet from node
Timestamp, and it is stored in local；Then, the sending time stamp carried from the available current sync data packet of node, obtains
The sending time stamp of one synchronization packets.Later, connecing from the available pre-stored upper synchronization packets of node
Timestamp is received, and according to the signal representation of the receiving time of upper synchronization packets stamp, sending time stamp, reference clock signal
The signal expression of formula and the clock signal from node calculates and believes from the clock signal of node and the reference clock of host node
Phase difference between number.Correspondingly, the expression formula (6) of phase difference is corrected are as follows:
Wherein,The phase difference calculated when indicating to receive+1 synchronization packets of kth from node,Indicate that the corresponding phase difference of k-th of synchronization packets, τ are delay time, delay time includes receiving from node together
Time needed for calculating control amount after step data packet, u (k-1) are calculated when receiving -1 synchronization packets of kth from node
Control amount, u (k-2) are the corresponding control amount of -2 synchronization packets of kth, TsynFor synchronizing cycle.
Optionally, host node is when sending synchronization packets in wireless sensor network, it is possible that packet loss event, loses
The presence of packet event also will affect the synchronization accuracy that phase difference and control amount are calculated from node.When the packet loss of synchronization packets is
When default value, the concrete processing procedure that control amount is calculated from node includes: according to phase difference, packet loss and preset benefit
Controller is repaid, control amount is calculated.
In a kind of feasible implementation, can creating tool from node, there are two the Markov Chains of state, to indicate
State set S={ 0,1 } can be set from node in packet loss process in wireless sensor network, wherein 0 indicates not receive
A certain synchronization packets, 1 indicates to receive the synchronization packets.
Q={ s (k) can be expressed as from the Markov Chain of the state set value；K=1,2 ... }.As shown in Fig. 2,
For a kind of markovian state transition diagram provided by the embodiments of the present application, it is based on state transition diagram shown in Fig. 2, it can be true
Determine state-transition matrix P are as follows:
Wherein, r is the packet loss of a certain synchronization packets, and state-transition matrix P is for indicating to receive this from node together
The probability of next synchronization packets of step data packet.When receiving the synchronization packets, received from node next same
The Probability p of step data packet11=1-r does not receive the Probability p of next synchronization packets10=r；When not receiving this from node
When synchronization packets, the Probability p of next synchronization packets is received from node01=1-r does not receive next synchrodata
The Probability p of packet00=r.
The state-transition matrix for sending synchronization packets each time is all the same, receives k-th of synchronization packets from node
Probability are as follows:
Pk=P (9)
Therefore, synchronization packets are sent for host node kth time, sends the probability π of failure0For r, successful probability is sent
π1For 1-r.
The closed-loop control system established for ease of description based on Markov Chain, definition:
Optionally, it is based on formula (10) and formula (11), the expression formula of control amount u (k) can be determined from node are as follows:
Wherein, kpFor preset proportionality coefficient, kiFor preset integral coefficient.
Based on formula (7) and formula (12), closing comprising transmission delay, processing delay and packet loss can establish from node
Ring control system.
It is right based on transmission delay, processing delay and the packet loss in wireless sensor network in the embodiment of the present application
The expression formula of phase difference and control amount in closed-loop control system is corrected, and can further increase the synchronous essence of clock
Degree.
Optionally, the embodiment of the present application also provides a kind of modes of stability for judging synchronous method, specific processed
Journey includes:
Step 301, it is based on phase difference and control amount, establishes synchronous feedback system M；
In an implementation, from node can expression formula and control amount based on phase difference expression formula, establish synchronous feedback
System.
In a kind of feasible implementation, it can be expressed as follows with definition status vector X (k), X (k):
Wherein,For indicatingIt arrivesSum, be based on X
(k) expression formula (7) of phase difference and the expression formula (12) of control amount are indicated, the expression formula of synchronous feedback system M, M can be obtained
Are as follows:
Wherein,
W (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, W are preset scalar matrix.
Step 302, judging whether there is meets synchronous feedback system M
Scalar matrix
In an implementation, can be according to the expression formula of synchronous feedback system M from node, judging whether there is makes synchronous feedback system
The M that unites meetsScalar matrix
In a kind of feasible implementation, if synchronous feedback system M is for arbitrary initial conditions X (0)=X0,s(0)
=s0, exist and X0、s0Unrelated scalar matrixSo thatThen from section
Point can determine synchronous feedback system M mean square stability.Wherein, X0For indicating the original state of state variable, s0For indicating horse
The original state of Er Kefu random process, s0Value can be 0 or 1.
It may be defined that
Wherein, x is preset independent variable, χAIt (x) is indicative function, A is preset event sets, the embodiment of the present application
In, x can be s (k), and A can be state set S={ 0,1 }.
∏ (k)=E (X (k) X (k)T) (16)
∏j(k)=E (X (k) X (k)Tχ(s (k)=j)) (17)
Λi=Ai+BC (18)
Wherein, ∏ (k), ∏j(k) and ΛiFor preset intermediate variable, i and j are that the subscript that value is 0 or 1 becomes
Amount.AiIt is the A in formula (14)s(k)。
It can be derived by based on formula (15), formula (16), formula (17) and formula (18):
Π (k)=Π0(k)+Π1(k)(19)
Wherein, Π0(k) and Π1It (k) is preset intermediate variable, N is the maximum value of i, pijTurn for preset state
Move probability.
Based on the operation rule of vector quantities operation symbol, can obtain
Wherein,Indicate Kronecker Kronecker product, D, E and F be matrix dimensionality be respectively k*I, I*m and
The matrix of m*n, k, I, m and n can be any default value.
Based on formula (21), formula (20) can be indicated are as follows:
Wherein, r is packet loss.
If there is with X0、s0Unrelated scalar matrixSo that formula (22) is set up, then the side synchronous feedback system M is steady
It is fixed.
Define matrix
When the spectral radius of matrix Λ is less than 1, formula (22) is set up, i.e. synchronous feedback system M mean square stability, therefore, from section
Point can be with the spectral radius of calculating matrix Λ, and whether the spectral radius of judgment matrix Λ less than 1, if spectral radius less than 1, from section
Point can be based on matrix Λ calculation constant matrixObtain formula (24).
If the spectral radius of matrix Λ is greater than 1, it can determine that there is no scalar matrixes from node.
Step 303, if there is scalar matrix, it is determined that synchronous feedback system M stablizes.
In an implementation, if there is the scalar matrix, then fortune that synchronous feedback system can be stable can be determined from node
Row.
It, can not be common based on linear system although synchronous feedback system is similar with linear system in the embodiment of the present application
The mode of asymptotically stability determine the stability of system, therefore, mode of the embodiment of the present application based on mean square stability judges to synchronize
Whether feedback system is stable, and then is embodied as the status information that technical staff prompts the operation of synchronous feedback system.
It as shown in fig. 4 a, is a kind of Wireless clock side of synchronization based on super broad band radio communication provided by the embodiments of the present application
The time diagram of method.Wherein, host node generates the period of reference clock signal as Tm, the period of clock signal is generated from node
For Ts, the initial phase difference between the clock signal of node and the reference clock signal of host node isHost node is according to same
Step period TsynSynchronization packets are sent, and generate the corresponding sending time stamp of synchronization packets；By time TdAfterwards, from node
The synchronization packets can be received, and generate receiving time stamp；Then, it can be stabbed from node according to sending time, receiving time
The signal expression of stamp, the signal expression of reference clock signal and the clock signal from node determines currently from node
Phase difference between clock signal and reference clock signal；Later, corresponding control amount can be calculated from node, to reduce from section
Phase difference between the clock signal and reference clock signal of point.It after a period of time, can will be from the clock signal of node
Phase difference between reference clock signal is down to 0, realizes that the Wireless clock of wireless sensor network is synchronous.
It as shown in Figure 4 b, is a kind of system framework schematic diagram of indoor distribution node provided by the embodiments of the present application, the room
Interior distribution node can execute a kind of Wireless clock synchronous method based on super broad band radio communication provided by the embodiments of the present application.
The component that dotted portion includes in figure can choose addition or not add.
The embodiment of the present application also provides a kind of the Wireless clock synchronizing device based on super broad band radio communication, described device
Applied to the slave node in the wireless sensor network based on Ultra-wideband Communication Technology, the wireless sensor network further includes master
Node, as shown in figure 5, described device includes:
Generation module 510, for when receiving the synchronization packets that the host node is sent, generating receiving time stamp,
The synchronization packets carry sending time stamp；
First computing module 520, for obtaining the signal expression for the reference clock signal that the host node includes, and root
According to receiving time stamp, sending time stamp, the signal expression of the reference clock signal and described from node
The signal expression of clock signal calculates between the clock signal from node and the reference clock signal of the host node
Phase difference；
Second computing module 530, it is described for calculating control amount according to the phase difference and preset compensating controller
Compensating controller includes proportion adjustment and integral adjustment PI controller；
Adjustment module 540, for adjusting the frequency of the clock signal from node according to the control amount.
Optionally, the expression formula of the phase difference are as follows:
Wherein, describedTo be described from section
When point kth time receives the synchronization packets, the phase between the clock signal from node and the reference clock signal
Potential difference, the k0For voltage-controlled coefficient, the u (k) receives the control generated after the synchronization packets from node kth time to be described
Amount processed, the TsynFor preset synchronizing cycle, the Δ f is the clock signal from node and the reference clock signal
Between difference on the frequency；
The expression formula of the control amount are as follows:Wherein, described
kpFor preset proportionality coefficient, the kiFor preset integral coefficient.
Optionally, sending time stamp for the last synchronization packets received sending time stamp when, described the
One computing module includes:
The sending time of first computational submodule, the synchronization packets for being received according to the last time stabs, is described
The signal expression of receiving time stamp, the signal expression of the reference clock signal and the clock signal from node,
Calculate the phase difference between the clock signal from node and the reference clock signal of the host node.
Optionally, the expression formula of the phase difference are as follows:
Wherein,
It is describedFor it is described receive the synchronization packets from node kth time when, the clock signal from node with it is described
Phase difference between reference clock signal, the k0For voltage-controlled coefficient, the u (k-1) is described to receive for -1 time from node kth
The control amount generated after the synchronization packets, the TsynFor preset synchronizing cycle, the Δ f be it is described from node when
Difference on the frequency between clock signal and the reference clock signal, the τ are delay time, and the delay time includes described from section
Put the time needed for calculating the control amount after receiving synchronization packets.
Optionally, when the packet loss of the synchronization packets is default value, second computing module includes:
Second computational submodule, for according to the phase difference, the packet loss and preset compensating controller, meter
Calculate control amount.
Optionally, the expression formula of the control amount isWherein, institute
State kpFor preset proportionality coefficient, the kiIt is described for preset integral coefficientIt is describedS (k)=0
It indicates described and does not receive the synchronization packets from node, the s (k)=1 indicates described and receives the synchronization from node
Data packet.
Optionally, described device further include:
Module is established, for being based on the phase difference and the control amount, establishes synchronous feedback system M, the expression of the M
Formula is
Wherein, describedIt is describedIt is describedThe u (k) is described from section
When point kth time receives synchronization packets, whether the control amount being calculated, the s (k) is received for indicating described from node
To synchronization packets, the w (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, the W are pre-
If scalar matrix；
Judgment module meets the synchronous feedback system M for judging whether there isScalar matrix
Determining module, for when there are the scalar matrix, determining that the synchronous feedback system is stablized.
A kind of Wireless clock synchronizing device based on super broad band radio communication provided by the embodiments of the present application, can receive
To host node send synchronization packets when, generate receiving time stamp；Then, it is carried according to receiving time stamp, synchronization packets
Sending time stamp, the signal expression of reference clock signal and the clock signal from node signal expression, calculate from
Phase difference between the clock signal of node and the reference clock signal of host node；Later, according to phase difference and compensating controller,
Control amount is calculated, finally according to control amount, adjusts the frequency from the clock signal of node.Due to based on Ultra-wideband Communication Technology into
Row clock is synchronous, can be stabbed with accurate recording sending time and therefore receiving time stamp can be improved each in wireless sensor network
The synchronization accuracy of network node.
The embodiment of the present application also provides a kind of electronic equipment, as shown in fig. 6, include processor 601, communication interface 602,
Memory 603 and communication bus 604, wherein processor 601, communication interface 602, memory 603 are complete by communication bus 604
At mutual communication,
Memory 603, for storing computer program；
Processor 601 when for executing the program stored on memory 603, realizes following steps:
When receiving the synchronization packets that the host node is sent, receiving time stamp is generated, the synchronization packets are taken
It is stabbed with sending time；
The signal expression of the reference clock signal of the host node is obtained, and according to receiving time stamp, the hair
The signal expression of timestamp, the signal expression of the reference clock signal and the clock signal from node is sent, is counted
Calculate the phase difference between the clock signal from node and the reference clock signal of the host node；
According to the phase difference and preset compensating controller, control amount is calculated, the compensating controller includes ratio tune
Section and integral adjustment PI controller；
According to the control amount, the frequency of the clock signal from node is adjusted.
Optionally, the expression formula of the phase difference are as follows:
Wherein, describedTo be described from section
When point kth time receives the synchronization packets, the phase between the clock signal from node and the reference clock signal
Potential difference, the k0For voltage-controlled coefficient, the u (k) receives the control generated after the synchronization packets from node kth time to be described
Amount processed, the TsynFor preset synchronizing cycle, the Δ f is the clock signal from node and the reference clock signal
Between difference on the frequency；
The expression formula of the control amount are as follows:Wherein, described
kpFor preset proportionality coefficient, the kiFor preset integral coefficient.
Optionally, when the sending time stamp stabs for the sending time of the last synchronization packets received, described
According to receiving time stamp, sending time stamp, the signal expression of the reference clock signal and described from node
The signal expression of clock signal calculates between the clock signal from node and the reference clock signal of the host node
Phase difference includes:
According to sending time stamp, the receiving time stamp, the benchmark of the synchronization packets that the last time receives
The signal expression of the signal expression of clock signal and the clock signal from node, calculate it is described from node when
Phase difference between clock signal and the reference clock signal of the host node.
Optionally, the expression formula of the phase difference are as follows:
Wherein,
It is describedFor it is described receive the synchronization packets from node kth time when, the clock signal from node with it is described
Phase difference between reference clock signal, the k0For voltage-controlled coefficient, the u (k-1) is described to receive for -1 time from node kth
The control amount generated after the synchronization packets, the TsynFor preset synchronizing cycle, the Δ f be it is described from node when
Difference on the frequency between clock signal and the reference clock signal, the τ are delay time, and the delay time includes described from section
Put the time needed for calculating the control amount after receiving synchronization packets.
Optionally, it is described according to the phase difference and preset when the packet loss of the synchronization packets is default value
Compensating controller, calculating control amount includes:
According to the phase difference, the packet loss and preset compensating controller, control amount is calculated.
Optionally, the expression formula of the control amount isWherein, institute
State kpFor preset proportionality coefficient, the kiIt is described for preset integral coefficientIt is describedS (k)=0
It indicates described and does not receive the synchronization packets from node, the s (k)=1 indicates described and receives the synchronization from node
Data packet.
Optionally, the method also includes:
Based on the phase difference and the control amount, synchronous feedback system M is established, the expression formula of the M is
Wherein, describedIt is describedIt is describedThe u (k) is described from section
When point kth time receives synchronization packets, whether the control amount being calculated, the s (k) is received for indicating described from node
To synchronization packets, the w (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, the W are pre-
If scalar matrix；
Judging whether there is meets the synchronous feedback system MIt is normal
Moment matrix
If there is the scalar matrix, it is determined that the synchronous feedback system is stablized.
The communication bus that above-mentioned electronic equipment is mentioned can be Peripheral Component Interconnect standard (Peripheral Component
Interconnect, PCI) bus or expanding the industrial standard structure (Extended Industry Standard
Architecture, EISA) bus etc..The communication bus can be divided into address bus, data/address bus, control bus etc..For just
It is only indicated with a thick line in expression, figure, it is not intended that an only bus or a type of bus.
Communication interface is for the communication between above-mentioned electronic equipment and other equipment.
Memory may include random access memory (Random Access Memory, RAM), also may include non-easy
The property lost memory (Non-Volatile Memory, NVM), for example, at least a magnetic disk storage.Optionally, memory may be used also
To be storage device that at least one is located remotely from aforementioned processor.
Above-mentioned processor can be general processor, including central processing unit (Central Processing Unit,
CPU), network processing unit (Network Processor, NP) etc.；It can also be digital signal processor (Digital Signal
Processing, DSP), it is specific integrated circuit (Application Specific Integrated Circuit, ASIC), existing
It is field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete
Door or transistor logic, discrete hardware components.
In another embodiment provided by the present application, a kind of computer readable storage medium is additionally provided, which can
It reads to be stored with computer program in storage medium, the computer program realizes that any of the above-described one kind is based on when being executed by processor
The step of Wireless clock synchronous method of super broad band radio communication.
In another embodiment provided by the present application, a kind of computer program product comprising instruction is additionally provided, when it
When running on computers, when so that computer executing any wireless based on super broad band radio communication in above-described embodiment
Clock synchronous method.
In the above-described embodiments, can come wholly or partly by software, hardware, firmware or any combination thereof real
It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.The computer program
Product includes one or more computer instructions.When loading on computers and executing the computer program instructions, all or
It partly generates according to process or function described in the embodiment of the present application.The computer can be general purpose computer, dedicated meter
Calculation machine, computer network or other programmable devices.The computer instruction can store in computer readable storage medium
In, or from a computer readable storage medium to the transmission of another computer readable storage medium, for example, the computer
Instruction can pass through wired (such as coaxial cable, optical fiber, number from a web-site, computer, server or data center
User's line (DSL)) or wireless (such as infrared, wireless, microwave etc.) mode to another web-site, computer, server or
Data center is transmitted.The computer readable storage medium can be any usable medium that computer can access or
It is comprising data storage devices such as one or more usable mediums integrated server, data centers.The usable medium can be with
It is magnetic medium, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or semiconductor medium (such as solid state hard disk
Solid State Disk (SSD)) etc..
A kind of Wireless clock synchronous method and device based on super broad band radio communication provided by the embodiments of the present application, can be with
When receiving the synchronization packets of host node transmission, receiving time stamp is generated；Then, according to receiving time stamp, synchrodata
The signal expression of sending time stamp, the signal expression of reference clock signal and the clock signal from node that packet carries,
Calculate the phase difference between the clock signal of node and the reference clock signal of host node；Later, according to phase difference and compensation
Controller calculates control amount, finally according to control amount, adjusts the frequency from the clock signal of node.Due to being based on ultra-wide band logical
Letter technology carries out clock and synchronizes, and can be stabbed with accurate recording sending time and receiving time is stabbed, therefore, can be improved wireless sensor
The synchronization accuracy of each network node in network.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Each embodiment in this specification is all made of relevant mode and describes, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for device reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.
The foregoing is merely the preferred embodiments of the application, are not intended to limit the protection scope of the application.It is all
Any modification, equivalent replacement, improvement and so within spirit herein and principle are all contained in the protection scope of the application
It is interior.
Claims (10)
1. a kind of Wireless clock synchronous method based on super broad band radio communication, which is characterized in that the method is applied to be based on
Slave node in the wireless sensor network of Ultra-wideband Communication Technology, the wireless sensor network further includes host node, described
Method includes:
When receiving the synchronization packets that the host node is sent, receiving time stamp is generated, the synchronization packets carry
Sending time stamp；
Obtain the signal expression of the reference clock signal of the host node, and when according to receiving time stamp, the transmission
Between stamp, the signal expression of the reference clock signal and the clock signal from node signal expression, calculate institute
State the phase difference between the clock signal of node and the reference clock signal of the host node；
According to the phase difference and preset compensating controller, calculate control amount, the compensating controller include proportion adjustment and
Integral adjustment PI controller；
According to the control amount, the frequency of the clock signal from node is adjusted.
2. the method according to claim 1, wherein the expression formula of the phase difference are as follows:
Wherein, describedTo be described from node kth
It is secondary when receiving the synchronization packets, the phase difference between the clock signal and the reference clock signal from node,
The k0For voltage-controlled coefficient, the u (k) receives the control amount generated after the synchronization packets from node kth time to be described,
The TsynFor preset synchronizing cycle, the Δ f is described between the clock signal and the reference clock signal of node
Difference on the frequency；
The expression formula of the control amount are as follows:Wherein, the kpIt is pre-
If proportionality coefficient, the kiFor preset integral coefficient.
3. the method according to claim 1, wherein sending time stamp is the last same step number received
According to packet sending time stamp when, it is described according to the receiving time stamp, the sending time stamp, the reference clock signal letter
The signal expression of number expression formula and the clock signal from node, calculate the clock signal from node with it is described
Phase difference between the reference clock signal of host node includes:
According to sending time stamp, the receiving time stamp, the reference clock of the synchronization packets that the last time receives
The signal expression of the signal expression of signal and the clock signal from node calculates described from the clock of node letter
Phase difference number between the reference clock signal of the host node.
4. according to the method described in claim 3, it is characterized in that, the expression formula of the phase difference are as follows:
Wherein, institute
It statesFor it is described receive the synchronization packets from node kth time when, the clock signal from node and the base
Phase difference between clock signal, the k0For voltage-controlled coefficient, the u (k-1) receives institute from node kth -1 time to be described
State the control amount generated after synchronization packets, the TsynFor preset synchronizing cycle, the Δ f is the clock from node
Difference on the frequency between signal and the reference clock signal, the τ are delay time, and the delay time includes described from node
Receive the time needed for calculating the control amount after synchronization packets.
5. according to the method described in claim 3, it is characterized in that, the packet loss of the synchronization packets be default value when,
It is described according to the phase difference and preset compensating controller, calculating control amount includes:
According to the phase difference, the packet loss and preset compensating controller, control amount is calculated.
6. according to the method described in claim 5, it is characterized in that, the expression formula of the control amount isWherein, the kpFor preset proportionality coefficient, the kiFor preset product
Divide coefficient, it is describedIt is described
The s (k)=0 indicates described and does not receive the synchronization packets from node, and the s (k)=1 indicates described and receives from node
To the synchronization packets.
7. according to the method described in claim 5, it is characterized in that, the method also includes:
Based on the phase difference and the control amount, synchronous feedback system M is established, the expression formula of the M isWherein, describedIt is describedIt is describedThe u (k) is described from section
When point kth time receives synchronization packets, whether the control amount being calculated, the s (k) is received for indicating described from node
To synchronization packets, the w (k) is random noise vector, and has E (w (k))=0, E (w (k) w (k)T)=W, the W are pre-
If scalar matrix；
Judging whether there is meets the synchronous feedback system MConstant square
Battle array
If there is the scalar matrix, it is determined that the synchronous feedback system is stablized.
8. a kind of Wireless clock synchronizing device based on super broad band radio communication, which is characterized in that described device is applied to be based on
Slave node in the wireless sensor network of Ultra-wideband Communication Technology, the wireless sensor network further includes host node, described
Device includes:
Generation module, for when receiving the synchronization packets that the host node is sent, generating receiving time stamp, the synchronization
Data packet carries sending time stamp；
First computing module, the signal expression of the reference clock signal for obtaining the host node, and according to the reception
Timestamp, sending time stamp, the signal expression of the reference clock signal and the clock signal from node
Signal expression calculates the phase difference between the clock signal from node and the reference clock signal of the host node；
Second computing module, for calculating control amount, the compensation control according to the phase difference and preset compensating controller
Device includes proportion adjustment and integral adjustment PI controller；
Adjustment module, for adjusting the frequency of the clock signal from node according to the control amount.
9. a kind of electronic equipment, which is characterized in that including processor, communication interface, memory and communication bus, wherein processing
Device, communication interface, memory complete mutual communication by communication bus；
Memory, for storing computer program；
Processor when for executing the program stored on memory, realizes method and step as claimed in claim 1 to 7.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer in the computer readable storage medium
Program, the computer program realize method and step as claimed in claim 1 to 7 when being executed by processor.
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