CN109545927A - 发光二极管芯片 - Google Patents
发光二极管芯片 Download PDFInfo
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- CN109545927A CN109545927A CN201811461350.2A CN201811461350A CN109545927A CN 109545927 A CN109545927 A CN 109545927A CN 201811461350 A CN201811461350 A CN 201811461350A CN 109545927 A CN109545927 A CN 109545927A
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- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000008033 biological extinction Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
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Abstract
本发明涉及一种发光二极管芯片,发光二极管芯片从下向上依次包括:衬底、成核层、氮化物缓冲层、非掺杂GaN层、N型GaN层、多量子阱层、P型AlGaN层、P型GaN层、P型InGaN接触层,还包括与P型InGaN接触层电性导通的P电极,与N型GaN层电性导通的N电极,P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向递增。本发明中与金属接触的是P型InGaN接触层,P型InGaN接触层中掺杂有高浓度的Mg,In的摩尔浓度为逐渐递增的渐变层结构并在接触面上达到最高值,P型InGaN接触层的空穴浓度较高,减少了与金属接触电阻率,增加了载流子通过隧穿穿越金属与半导体接触势垒区的几率,可降低发光二极管芯片的工作电压,提高了发光二极管芯片的发光效率。
Description
技术领域
本发明涉及半导体发光器件技术领域,尤其涉及一种发光二极管芯片。
背景技术
发光二极管(LED)作为一种高效、环保和绿色新型固态照明光源,具有体积小、重量轻、寿命长、可靠性高及使用功耗低等优点,使其得以广泛应用。特别地,随着LED行业的迅猛发展,LED在照明领域的应用所占比例越来越高。随着大功率发光二极管芯片在照明领域广泛应用,对大功率发光二极管芯片发光效率要求与日俱增,要提升大功率发光二极管芯片发光效率,一方面要提高大功率发光二极管芯片的亮度,另外一方面要降低大功率发光二极管芯片在高电流密度下的工作电压。
现有发光二极管芯片在P型GaN层上设有P型GaN接触层和N型InGaN接触层,设置N型InGaN接触层虽然可以与芯片ITO工艺形成良好的接触,起到降低工作电压的作用,但N型InGaN接触层本身也是吸光的,影响发光亮度。
发明内容
针对上述现有技术中存在的问题,本发明的目的在于提供一种可避免出现上述技术缺陷的发光二极管芯片。
为了实现上述发明目的,本发明提供的技术方案如下:
一种发光二极管芯片,所述发光二极管芯片从下向上依次包括:
衬底;
位于衬底上的成核层;
位于成核层上的氮化物缓冲层;
位于氮化物缓冲层上的非掺杂GaN层;
位于非掺杂GaN层上的N型GaN层;
位于N型GaN层上的多量子阱层;
位于多量子阱层上的P型AlGaN层;
位于P型AlGaN层上的P型GaN层;
位于P型GaN层上的P型InGaN接触层,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向递增;
位于P型InGaN接触层上且与P型InGaN接触层电性导通的P电极,位于N型GaN层上且与N型GaN层电性导通的N电极。
进一步地,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向线性递增。
进一步地,所述P型InGaN接触层中Ga的摩尔浓度恒定且In和Ga的摩尔浓度比在0.6-2的区间内递增。
进一步地,所述P型InGaN接触层为Mg掺杂。
进一步地,所述P型InGaN接触层的Mg掺杂浓度为2~4×1E20atoms/cm3。
进一步地,所述P型InGaN接触层的厚度为5-10nm。
进一步地,所述氮化物缓冲层的厚度为0.5-1um。
本发明中与金属接触的是P型InGaN接触层,P型InGaN接触层中掺杂有高浓度的Mg,In的摩尔浓度为逐渐递增的渐变层结构并在接触面上达到最高值,P型InGaN接触层的空穴浓度较高,减少了与金属接触电阻率,增加了载流子通过隧穿穿越金属与半导体接触势垒区的几率,可以降低大功率发光二极管芯片的工作电压,同时减少吸光,从而提高了大功率发光二极管芯片的发光效率。
附图说明
图1为本发明的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合附图和具体实施例对本发明做进一步说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
如图1所示,一种发光二极管芯片,从下向上依次包括:衬底;
位于衬底上的成核层;
位于成核层上的氮化物缓冲层;
位于氮化物缓冲层上的非掺杂GaN层;
位于非掺杂GaN层上的N型GaN层;
位于N型GaN层上的多量子阱层;
位于多量子阱层上的P型AlGaN层;
位于P型AlGaN层上的P型GaN层;
位于P型GaN层上的P型InGaN接触层,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向递增;
位于P型InGaN接触层上且与P型InGaN接触层电性导通的P电极,位于N型GaN层上且与N型GaN层电性导通的N电极。
进一步地,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向线性递增。
进一步地,所述P型InGaN接触层中Ga的摩尔浓度恒定且In和Ga的摩尔浓度比在0.6-2的区间内递增。
进一步地,所述P型InGaN接触层为Mg掺杂。
进一步地,所述P型InGaN接触层的Mg掺杂浓度为2~4×1E20atoms/cm3。
进一步地,所述P型InGaN接触层的厚度为5-10nm。
进一步地,所述氮化物缓冲层的厚度为0.5-1um。
本发明中与金属接触的是P型InGaN接触层,P型InGaN接触层中掺杂有高浓度的Mg,In的摩尔浓度为逐渐递增的渐变层结构并在接触面上达到最高值,P型InGaN接触层的空穴浓度较高,减少了与金属接触电阻率,增加了载流子通过隧穿穿越金属与半导体接触势垒区的几率,可以降低大功率发光二极管芯片的工作电压,同时减少吸光,从而提高了大功率发光二极管芯片的发光效率。
以上所述实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (7)
1.一种发光二极管芯片,其特征在于,所述发光二极管芯片从下向上依次包括:
衬底;
位于衬底上的成核层;
位于成核层上的氮化物缓冲层;
位于氮化物缓冲层上的非掺杂GaN层;
位于非掺杂GaN层上的N型GaN层;
位于N型GaN层上的多量子阱层;
位于多量子阱层上的P型AlGaN层;
位于P型AlGaN层上的P型GaN层;
位于P型GaN层上的P型InGaN接触层,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向递增;
位于P型InGaN接触层上且与P型InGaN接触层电性导通的P电极,位于N型GaN层上且与N型GaN层电性导通的N电极。
2.根据权利要求1所述的发光二极管芯片,其特征在于,所述P型InGaN接触层中In的摩尔浓度向着远离所述P型GaN层的方向线性递增。
3.根据权利要求1或2所述的发光二极管芯片,其特征在于,所述P型InGaN接触层中Ga的摩尔浓度恒定且In和Ga的摩尔浓度比在0.6-2的区间内递增。
4.根据权利要求1所述的发光二极管芯片,其特征在于,所述P型InGaN接触层为Mg掺杂。
5.根据权利要求4所述的发光二极管芯片,其特征在于,所述P型InGaN接触层的Mg掺杂浓度为2~4×1E20atoms/cm3。
6.根据权利要求1所述的发光二极管芯片,其特征在于,所述P型InGaN接触层的厚度为5-10nm。
7.根据权利要求1所述的发光二极管芯片,其特征在于,所述氮化物缓冲层的厚度为0.5-1um。
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Cited By (1)
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CN116344689A (zh) * | 2023-05-26 | 2023-06-27 | 中诚华隆计算机技术有限公司 | 一种具有涂层的发光芯片及其制作方法 |
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Cited By (2)
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CN116344689A (zh) * | 2023-05-26 | 2023-06-27 | 中诚华隆计算机技术有限公司 | 一种具有涂层的发光芯片及其制作方法 |
CN116344689B (zh) * | 2023-05-26 | 2023-07-21 | 中诚华隆计算机技术有限公司 | 一种具有涂层的发光芯片及其制作方法 |
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