CN109545256B - Block memory splicing method, splicing module, storage device and field programmable gate array - Google Patents
Block memory splicing method, splicing module, storage device and field programmable gate array Download PDFInfo
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- CN109545256B CN109545256B CN201811308535.XA CN201811308535A CN109545256B CN 109545256 B CN109545256 B CN 109545256B CN 201811308535 A CN201811308535 A CN 201811308535A CN 109545256 B CN109545256 B CN 109545256B
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C8/00—Arrangements for selecting an address in a digital store
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
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Abstract
The invention discloses a block memory splicing method, which comprises the following steps: calculating the number of RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed; judging whether the first data bit width and the RAM block data bit width meet preset conditions, if so, storing the data address to be processed in the RAM block according to a first rule; and if not, storing the data address to be processed in the RAM block according to a second rule. According to the method, the number of the RAM blocks needing to be spliced is obtained through calculation according to the characteristics of the bit width, the depth and the like of the data to be processed, then distribution is carried out according to the specific rule provided by the invention, and the data storage and reading and writing of each RAM block are dispersed, so that the problems that some RAM blocks are frequently used and the use times of some RAM blocks are few when the data bit width is large are solved, and the frequently used bits are uniformly distributed to the plurality of RAM blocks, so that the operation speed is increased.
Description
Technical Field
The invention belongs to the field of data storage, and particularly relates to a block memory splicing method, a splicing module, a storage device and a field programmable gate array.
Background
At present, most Field Programmable Gate Arrays (FPGAs) integrate a certain amount of block memories, and when a single block memory (RAM) is used, the data bit width and the address depth are limited by the capacity of the single block RAM; when higher requirements are made on data bit width or depth, a multi-block RAM needs to be cascaded to form a larger RAM. For a fixed data bit width and address depth, there are many ways of splicing.
The prior art provides a method for allocating RAM resources, which allows the required number to exceed the limit of embedded memory blocks, can satisfy the use of RAM with larger data bit width and deeper address depth, automatically calculates the number of allocated embedded memory blocks, REG resource blocks and LUT resource blocks, and can obtain the number of required embedded memory blocks through certain operation. When the data written in a certain embedded memory block is smaller than half of the corresponding maximum bit width of the embedded memory block under the address depth, the partial data is realized by using a REG resource block and an LUT resource block, and the other data parts still use the embedded memory block; when the data written in the used embedded memory blocks are all larger than half of the maximum bit width corresponding to the embedded memory blocks under the address depth, the embedded memory blocks are used for splicing, and the required functions can be realized.
However, the data bit width of the data that can be completed by this prior art is limited, and the application range is not universal enough. His data bit width can only be an even multiple of 1, 2, 4, 8, 16, 32, and 8; 9. 18, 36 and 9. In some cases, the data bit width may be an odd number or outside the above individual data range, which cannot be realized, and in addition, the prior art only realizes the required functions by splicing the required bit width and depth, and the splicing manner is random, so the operation efficiency is low.
Disclosure of Invention
In order to solve the above problems in the prior art, the invention provides a block memory splicing method, a splicing module, a storage device and a field programmable gate array. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a method for splicing a block memory, which comprises the following steps:
calculating the number of RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
judging whether the first data bit width and the RAM block data bit width meet preset conditions, if so, storing the data address to be processed in the RAM block according to a first rule; and if not, storing the data address to be processed in the RAM block according to a second rule.
In one embodiment, the preset condition is that Data _ w/M is not more than DW/n,
data _ w is the first Data bit width, M is the number of RAM blocks used for splicing, DW is the Data bit width of a single RAM, and n is a condition parameter, and can take values of 2,3,4, and 5 … DW-1.
In one embodiment, the first rule is:
in the ith block of RAM block, the range of the stored Data to be processed is (i-1). times.D-i.times.D-1, and the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data.
In one embodiment, the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) × D/2 — (i × D)/2-1 and (M + i-1) × D/2 — (M + i) × D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
The invention also provides a block memory splicing module, comprising:
the RAM block number calculating unit is used for calculating the number of the RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
the RAM allocation unit is used for judging whether the first data bit width and the RAM block data bit width meet preset conditions or not, and if so, storing the data address to be processed in the RAM block according to a first rule; and if not, storing the data address to be processed in the RAM block according to a second rule.
In one embodiment, the preset condition is that Data _ w/M is not more than DW/n,
data _ w is the first Data bit width, M is the number of RAM blocks used for splicing, DW is the Data bit width of a single RAM, and n is a condition parameter, and can take values of 2,3,4, and 5 … DW-1.
In one embodiment, taking n-2 as an example, the first rule is:
in the ith block of RAM, the range of the stored Data to be processed is (i-1) D-i × D-1, and the Address range is 0-Address _ w-1, where D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data.
In a specific embodiment, taking n ═ 2 as an example, the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) D/2- (i × D)/2-1 and (M + i-1) × D/2- (M + i) × D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
The invention also provides a storage device which comprises the block memory splicing module.
The invention relates to a field programmable gate array, which comprises the storage device.
Compared with the prior art, the invention has the beneficial effects that:
according to the block memory splicing method, the number of the RAM blocks to be spliced is obtained through calculation according to the characteristics of the bit width, the depth and the like of data to be processed, then distribution is carried out according to the specific rule provided by the invention, and the data storage and reading and writing of each RAM block are dispersed, so that the problems that some RAM blocks are frequently used and the use times of some RAM blocks are few when the bit width of the data is large are avoided, and bits which are frequently used are uniformly distributed to a plurality of RAM blocks, so that the operation speed is increased.
Drawings
FIG. 1 is a flow chart of a method for splicing a block memory according to an embodiment of the present invention;
FIG. 2 is a flow chart of another block memory splicing method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating RAM allocation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of data and address range allocation provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of data and address range allocation according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic flow chart of a block memory splicing method according to an embodiment of the present invention, including:
calculating the number of RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
judging whether the first data bit width and the RAM block data bit width meet preset conditions, if so, storing the data address to be processed in the RAM block according to a first rule; and if not, storing the data address to be processed in the RAM block according to a second rule.
In a first embodiment, calculating the number of RAM blocks used for splicing according to a first data bit width and a first data depth of a data address to be processed includes:
calculating the total data according to the first data bit width and the first data depth;
and calculating the number of RAM blocks used for splicing according to the total data and the capacity of the single RAM.
According to the block memory splicing method, the number of the RAM blocks to be spliced is obtained through calculation according to the characteristics of the bit width, the depth and the like of data to be processed, then distribution is carried out according to the specific rule provided by the invention, and the data storage and reading and writing of each RAM block are dispersed, so that the problems that some RAM blocks are frequently used and the use times of some RAM blocks are few when the bit width of the data is large are avoided, and bits which are frequently used are uniformly distributed to a plurality of RAM blocks, so that the operation speed is increased.
It is assumed that the first Data bit width of the Data to be processed is indicated by the symbol Data _ w and the first Data depth is 2Address_wAnd representing that the first Address bit width is Address _ w, wherein the data total amount calculation method comprises the following steps: data _ w × 2Address_w。
The total required number M of RAMs can be obtained by dividing the data weight by the capacity of a single RAM, specifically, if the division is exactly divided and the result is an integer M, which indicates that the requirement is exactly met, the total required number M of RAMs is M, and if a partial remainder remains after the division, a block of RAM is required to be added to store redundant data, and at this time, the total required number M of RAMs is M + 1.
Referring to fig. 2, from a programming perspective,
firstly: calculate m ═ (Data _ w × 2)Address_w) C, and r ═ Data _ w × 2Address_w)mod C；
If r is more than 0, indicating that a remainder exists, and selecting M as M + 1; otherwise, the remainder is not present, and M is selected to be M. The above symbol "/" represents a rounding operation, i.e., an integer portion resulting from the division, and mod represents a remainder operation, i.e., a remainder portion resulting from the division.
In one embodiment, the preset condition is that Data _ w/M is not more than DW/n,
data _ w is the first Data bit width, M is the number of RAM blocks used for splicing, DW is the Data bit width of a single RAM, and n is a condition parameter, and can take values of 2,3,4, and 5 … DW-1.
In one embodiment, referring to fig. 3 and 4, the first rule is:
in the ith block of RAM, the range of the stored Data to be processed is (i-1) D-i × D-1, and the Address range is 0-Address _ w-1, where D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data.
In one embodiment, referring to fig. 3 and 5, the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) D/2- (i × D)/2-1 and (M + i-1) × D/2- (M + i) × D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
According to the scheme of the embodiment, when a plurality of RAMs are required to be spliced, a certain amount of FPGA resources must be used due to the limitation of data bit width and address depth, data bits are dispersedly configured in a data distribution mode, and in the later stage of layout and wiring, corresponding wiring distribution is changed, so that the wiring density is reduced, the pressure of data reading and writing can be dispersed, and the improvement of the running speed under the condition of using less block RAMs of the FPGA is ensured.
In addition, when data is set, the data bit width value of the prior art is relatively fixed, and the limitation conditions of the prior art are as follows: data bit width x 2Address bit widthThe present invention extends the constraint between data bit width and address depth to: data bit width x 2Address bit width<The capacity of the single-chip RAM greatly improves the range of data bit width during splicing.
The invention also provides a block memory splicing module, comprising:
the RAM block number calculating unit is used for calculating the number of the RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
the RAM allocation unit is used for judging whether the first data bit width and the RAM block data bit width meet preset conditions or not, and if so, storing the data address to be processed in the RAM block according to a first rule; and if not, storing the to-be-processed data address in the RAM block according to a second rule.
In one embodiment, the preset condition is that Data _ w/M is not more than DW/n,
data _ w is the first Data bit width, M is the number of RAM blocks used for splicing, DW is the Data bit width of a single RAM, and n is a condition parameter, and can take values of 2,3,4, and 5 … DW-1.
In one embodiment, the first rule is:
in the ith block of RAM, the range of the stored Data to be processed is (i-1) D-iD-1, and the Address range is 0-Address _ w-1, where D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data.
In one embodiment, the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) D/2- (i × D)/2-1 and (M + i-1) × D/2- (M + i) × D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
The embodiment also provides a storage device which comprises the block memory splicing module.
The embodiment also provides a field programmable gate array, which comprises the storage device.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (4)
1. A method for tiling a block memory, comprising:
calculating the number of RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
judging whether the first data bit width and the RAM block data bit width meet preset conditions, if so, storing the data address to be processed in the RAM block according to a first rule; if not, storing the data address to be processed in the RAM block according to a second rule;
the preset condition is that Data _ w/M is less than or equal to DW/n,
wherein, Data _ w is the first Data bit width, M is the number of the RAM blocks used for splicing, DW is the Data bit width of a single RAM, n is a condition parameter, and the value can be 2,3,4,5 … DW-1;
the first rule is:
in the ith block of RAM block, the range of the stored Data to be processed is (i-1). times.D-i.times.D-1, and the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data;
the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) × D/2 — (i × D)/2-1 and (M + i-1) × D/2 — (M + i) D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
2. A block memory tiling module, comprising:
the RAM block number calculating unit is used for calculating the number of the RAM blocks used for splicing according to the first data bit width and the first data depth of the data address to be processed;
the RAM allocation unit is used for judging whether the first data bit width and the RAM block data bit width meet preset conditions or not, and if so, storing the data address to be processed in the RAM block according to a first rule; if not, storing the data address to be processed in the RAM block according to a second rule;
the preset condition is that Data _ w/M is less than or equal to DW/n,
wherein, Data _ w is the first Data bit width, M is the number of the RAM blocks used for splicing, DW is the Data bit width of a single RAM, n is a condition parameter, and the value can be 2,3,4,5 … DW-1;
the first rule is:
in the ith block of RAM block, the range of the stored Data to be processed is (i-1). times.D-i.times.D-1, and the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the bit width of the first Data;
the second rule is:
in the ith block of RAM block, the range of the Data to be processed is (i-1) × D/2 — (i × D)/2-1 and (M + i-1) × D/2 — (M + i) × D/2-1, the Address range is 0-Address _ w-1, wherein D is Data _ w/M, Address _ w is the depth of the Data to be processed, M is the number of RAM blocks used for splicing, and Data _ w is the width of the first Data bit.
3. A storage device comprising the block memory tiling module of claim 2.
4. A field programmable gate array comprising the memory device of claim 3.
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| US6317350B1 (en) * | 2000-06-16 | 2001-11-13 | Netlogic Microsystems, Inc. | Hierarchical depth cascading of content addressable memory devices |
| JP2003132681A (en) * | 2001-10-29 | 2003-05-09 | Mitsubishi Electric Corp | Semiconductor memory |
| US20090182977A1 (en) * | 2008-01-16 | 2009-07-16 | S. Aqua Semiconductor Llc | Cascaded memory arrangement |
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