CN109543845B - Conversion method and device of single quantum bit logic gate - Google Patents
Conversion method and device of single quantum bit logic gate Download PDFInfo
- Publication number
- CN109543845B CN109543845B CN201811082325.3A CN201811082325A CN109543845B CN 109543845 B CN109543845 B CN 109543845B CN 201811082325 A CN201811082325 A CN 201811082325A CN 109543845 B CN109543845 B CN 109543845B
- Authority
- CN
- China
- Prior art keywords
- logic gate
- quantum
- type
- determining
- continuous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The application provides a conversion method and a device of a single-quantum-bit logic gate, wherein the method comprises the following steps: obtaining the type of a single-quantum-bit logic gate supported by a quantum chip, and converting a second single-quantum-bit logic gate to be operated on the quantum chip into the logic gate of the type, so as to facilitate subsequent operation on the quantum chip, wherein the type may be one of the following types: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class, non-pervasive class. By adopting the technical scheme, the problem that the single-quantum-bit logic gate cannot operate on different quantum chips in the related technology is solved, the application ranges of the quantum chips and the single-quantum-bit logic gate are increased in a bidirectional mode, and the quantum computing speed is increased.
Description
Technical Field
The present application relates to, but not limited to, the field of quantum computing, and in particular, to a method and an apparatus for converting a single-quantum-bit logic gate.
Background
In the related art, an instruction set of a quantum chip is a set of quantum operations supported by the quantum chip or a qubit, which includes a set of single-qubit logic gates supported by the qubit.
A single qubit logic gate is an operation performed on only one qubit, represented by a 2 x 2 unitary transformation matrix U, which needs to be satisfied
The parameters may take any value.
In actual quantum programming, it is possible to implement single-qubit logic gates on a single-qubit in a parametric fashion, which may be of arbitrary value, meaning that such an operation may not belong to any of the set of single-qubit logic gates supported by the qubit (the gates in the set of single-qubit logic gates are finite, while the parametric logic gates are infinite). Therefore, any quantum logic gate needs to be converted into a single-quantum-bit logic gate which can be supported by the chip.
The set of single-qubit logic gates supported may be different for different quantum chips. The set of gates supported by a quantum chip may vary depending on the technology, process, principles, etc. of the chip design.
Aiming at the problem that a single-quantum-bit logic gate in the related technology cannot operate on different quantum chips, no effective solution is available at present.
Disclosure of Invention
The embodiment of the application provides a conversion method and a conversion device for a single-quantum-bit logic gate, which are used for at least solving the problem that the single-quantum-bit logic gate cannot operate on different quantum chips in the related technology.
According to an embodiment of the present application, there is provided a method for converting a single-qubit logic gate, including: acquiring a set of first single-quantum-bit logic gates supported by a quantum chip; determining a logic gate type to which the first single-qubit logic gate belongs as a first logic gate type, wherein the logic gate type comprises one of: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class and non-universal class; and converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
According to another embodiment of this document, there is also provided a conversion apparatus of a single-qubit logic gate, comprising: the acquisition module is used for acquiring a set of first single-quantum-bit logic gates supported by a quantum chip; a determining module, configured to determine that a logic gate type to which the first single-quantum-bit logic gate belongs is a first logic gate type, where the logic gate type includes one of: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class and non-universal class; and the conversion module is used for converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
According to a further embodiment of the present application, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
According to yet another embodiment of the present application, there is also provided an electronic device, comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
Through the method and the device, the type of the single-quantum-bit logic gate supported by the quantum chip is obtained, the second single-quantum-bit logic gate to be operated on the quantum chip is converted into the logic gate of the type, so that the subsequent operation on the quantum chip is facilitated, and the type can be one of the following types: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class, non-pervasive class. By adopting the technical scheme, the problem that the single-quantum-bit logic gate cannot operate on different quantum chips in the related technology is solved, the application ranges of the quantum chips and the single-quantum-bit logic gate are increased in a bidirectional mode, and the quantum computing speed is increased.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a block diagram of a hardware structure of a computer terminal of a conversion method of a single-qubit logic gate according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method of inverting a single qubit logic gate according to an embodiment of the present application;
FIG. 3 is a schematic flow diagram of a single qubit logic gate conversion according to the present document.
Detailed Description
The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example one
The method provided by the first embodiment of the present application may be executed in a computer terminal, or a similar computing device. Taking an example of the method running on a computer terminal, fig. 1 is a block diagram of a hardware structure of a computer terminal of a conversion method of a single qubit logic gate according to an embodiment of the present disclosure. As shown in fig. 1, the computer terminal 10 may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally may also include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the conversion method of the single qubit logic gate in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 104, so as to implement the above-described method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
The solution of the present document can be applied to the above-mentioned computer terminal, otherwise referred to as a quantum computer.
In this embodiment, a method for converting a single-qubit logic gate running on the computer terminal is provided, and fig. 2 is a flowchart of a method for converting a single-qubit logic gate according to an embodiment of the present application, where as shown in fig. 2, the flowchart includes the following steps:
step S202, acquiring a set of first single quantum bit logic gates supported by a quantum chip;
this set may also be referred to as a quantum chip instruction set, possibly including multiple qubit logic gates.
Step S204, determining that a logic gate type to which the first single-quantum-bit logic gate belongs is a first logic gate type, wherein the logic gate type includes one of: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class and non-universal class;
non-pervasive types, i.e. logic gates that are not universally applicable, or logic gates that are understood as being supported by the quantum chip, are rare, and are referred to as quantum logic gates of a relatively pervasive type (university) or generic type quantum logic gates, and currently, the ubiquitous type quantum logic gates that have been determined include CNOT, H, S, T, and the like.
And step S206, converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
Through the steps, the type of the single-quantum-bit logic gate supported by the quantum chip is obtained, and a second single-quantum-bit logic gate to be operated on the quantum chip is converted into the logic gate of the type, so that the subsequent operation on the quantum chip is facilitated, wherein the type may be one of the following types: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class, non-pervasive class. By adopting the technical scheme, the problem that the single-quantum-bit logic gate cannot operate on different quantum chips in the related technology is solved, the application ranges of the quantum chips and the single-quantum-bit logic gate are increased in a bidirectional mode, and the quantum computing speed is increased.
Optionally, the logic gate type is determined to be an arbitrary rotation class by: and when detecting that any rotation instruction is included in the set, determining the type of the logic gate to be any rotation class.
Optionally, converting a second single-qubit logic gate to be operated by the quantum chip according to the first logic gate type includes: and under the condition that the type of the first logic gate is any rotation type, the second single-quantum-bit logic gate is directly operated on the quantum chip without converting the second single-quantum-bit logic gate.
Optionally, determining the logic gate type as a bicontinuous class by: upon determining that there are at least two consecutively rotated logic gates in the set in different directions, determining that the logic gate type is a bi-consecutive class.
Optionally, converting a second single-qubit logic gate to be operated by the quantum chip according to the first logic gate type includes: in the case that the first logic gate type is a bi-continuous class, obtaining, among a plurality of first single-quantum-bit logic gates, two continuously rotating logic gates C1 and C2 in different directions; constructing a first double-continuous class model according to the C1 and the C2, and converting the second single-quantum-bit logic gate according to the first double-continuous class model. The converted second single-quantum-bit logic gate may appear as a quantum wire.
Optionally, determining the logic gate type as a single continuous single discrete class by: upon determining that there is one continuously rotating logic gate C3, and at least one fixed angle of rotation logic gate D1 in the set, determining the logic gate type as a single continuous single discrete class.
Optionally, converting a second single-qubit logic gate to be operated by the quantum chip according to the first logic gate type includes: under the condition that the first logic gate type is a single continuous single discrete class, obtaining a continuous rotation logic gate C5 and at least one fixed rotation angle logic gate D2 from a plurality of first single-quantum bit logic gates, and performing base-changing conversion on at least one fixed rotation angle logic gate D2 to obtain a continuous rotation logic gate C6, wherein the rotation directions of the continuous rotation logic gate C5 and the fixed rotation angle logic gate D2 are different, and the rotation directions of the continuous rotation logic gate C5 and the continuous rotation logic gate C6 are different; constructing a second bicontinuous type model from the continuously rotating logic gate C5 and the continuously rotating logic gate C6, transforming the second single-quantum-bit logic gate from the second bicontinuous type model. The converted second single-quantum-bit logic gate may appear as a quantum wire.
The step of performing the base conversion on at least one logic gate D2 with the fixed rotation angle refers to executing a continuous base conversion algorithm on the logic gate D2 with the fixed rotation angle, wherein the specific continuous base conversion algorithm receives a continuous rotation logic gate C and a logic gate D with the fixed rotation angle, and returns a logic gate C 'with the rotation angle different from C, and C' can be constructed through C and D. The steps are firstly to calculate
And judging whether the rotating directions of C and C' are the same or not. If so, return to null. If not, return to C'.
In the above description, the rotation directions of the continuous rotation logic gate C5 and the fixed rotation angle logic gate D2 are different; the direction of rotation of both the continuously rotating logic gate C5 and the continuously rotating logic gate C6 is different. It can be understood as follows:
because each quantum state is visualized on the bloch sphere as a geometric point, the operation of the rotation logic gate on the quantum state on the bloch sphere visually represents the rotation of the quantum state on the bloch sphere. When rotating, common logic gates for continuous rotation are RX (θ) gate, RY (θ) gate, and RZ (θ) gate, where: RX (θ) gate means that the quantum state can rotate any angle around the X-axis, RY (θ) gate means that the quantum state can rotate any angle around the Y-axis, RZ (θ) gate means that the quantum state can rotate any angle around the Z-axis, and common fixed rotation angle logic gates are S gate and T gate (also called pi/8 gate), where S gate means that the qubit is rotated 90 ° around the Z-axis on the bloch sphere and T gate means that the qubit is rotated 45 ° around the Z-axis on the bloch sphere. If the rotation axes (i.e. the rotation directions) of the continuously rotating logic gate and the fixed rotation angle logic gate are the same, the continuously rotating logic gate and the fixed rotation angle logic gate are equivalent when the rotation angle of the continuously rotating logic gate is equal to the rotation angle of the fixed rotation angle logic gate, for example: RZ (π/2) and the S gate are equivalent. When the rotation directions of the two continuous rotation logic gates are the same, the two are equivalent, so that the rotation directions of the continuous rotation logic gate C5 and the fixed rotation angle logic gate D2 are required to be different; the rotation directions of both the continuously rotating logic gate C5 and the continuously rotating logic gate C6 are different to avoid the presence of equivalent logic gates.
Optionally, when it is determined that the type of the logic gate is not the following type, determining that the type of the logic gate is a non-pervasive class: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class.
Optionally, an error warning is issued upon determining that the type of logic gate is a non-pervasive type.
Optionally, after the second single-qubit logic gate to be operated by the quantum chip is converted into the first logic gate type, the converted second single-qubit logic gate is operated on the quantum chip.
Optionally, the first single-quantum-bit logic gate comprises one of: the matrix elements of the first single-quantum-bit logic gate are discrete elements; the matrix elements of the first single-qubit logic gate are consecutive elements. The matrix elements are discrete elements, namely fixed elements, and the continuous elements represent the values of the matrix elements in a certain continuous range.
The following description is made in conjunction with another embodiment of the present document.
With the development of the current technology, various quantum logic gates are supported on a quantum chip, such as a gate rotating at any angle along an X axis and a Y axis in a rotating construction gate. Theoretically (quantum computing basic theory), the new quantum logic gates also have quantum computing universality, namely, any single quantum bit logic gate can be formed.
The technical effect to be achieved by another embodiment of the present application is that the quantum computer has a rotating logic gate with a continuous rotation angle, or other logic gates with fixed special angles, and can perform targeted conversion, so as to convert any single-bit logic gate into a logic gate sequence adapted to the quantum computer.
In another embodiment of the present application, single qubit logic gates in a quantum wire are converted into a set of single qubit logic gates supported in an instruction set of a quantum chip. The representation form is a computer program, the program input is [ 1. quantum logic gate to be converted, 2. quantum chip instruction set ], and the program output is [ converted quantum circuit (1 or a plurality of orderly arranged quantum logic gates) ].
The input quantum instruction set has 2 forms, one of which is a continuous element and represents a quantum logic gate with an operation matrix containing variable parameters; the second is a discrete element, representing a quantum logic gate whose operational matrix does not contain variable parameters.
The input quantum logic gates to be converted are usually given in the form of an operation matrix.
The output transformed quantum wire includes one or more quantum logic gates arranged in an array, wherein each quantum logic gate is a quantum logic gate included in a quantum instruction set.
Fig. 3 is a schematic flow chart of the conversion of the single-qubit logic gate according to the present document, as shown in fig. 3, comprising the following steps:
determining a quantum logic gate to be converted and a quantum chip instruction set as inputs;
step two, executing a quantum instruction set pre-judgment algorithm on the input quantum instruction set, and classifying the quantum instruction set into: any rotation class; a bi-continuous class; a single continuous single discrete class; a fully discrete class; is not universally suitable. Wherein each classification is processed separately.
And step three, for any rotation class, the quantum computer receives an operation matrix in any form, so that the quantum logic gate conforms to the instruction set and is directly output, and the algorithm is stopped. If the quantum chip is not in any rotation type, turning to the fourth step;
and step four, for the 'double continuous class', the quantum computer is shown to accept continuous rotation logic gates Cn in at least two different rotation directions.
Step five, two logic gates C1 and C2 are continuously rotated in different directions;
and step six, executing a 'double-continuous class construction algorithm' by taking the C1 and the C2 as inputs to obtain a quantum line, and stopping the algorithm as an algorithm output. If the single quantum bit logic gate provided by the quantum chip is not a bicontinuous class, turning to step seven;
step seven, for 'single continuous single discrete class', it means that the quantum computer accepts logic gate C1 of continuous rotation in one direction and logic gate Dn of at least one fixed rotation angle in another direction.
Step eight, sequentially executing a continuous basis conversion algorithm to the logic gate with the fixed rotation angle until the algorithm outputs a logic gate C2 which has a different angle from C1 and rotates continuously;
and step nine, taking the C1 and the C2 in different directions or different angles, turning to step six, executing a 'bicontinuous class construction algorithm' as input, obtaining a quantum line, outputting the quantum line as the algorithm, and stopping the algorithm. If the quantum chip is not in the single continuous single discrete class, turning to the step ten;
step ten, for 'full discrete class', the logic gate that represents the quantum computer accepting at least two fixed operation matrixes is adopted.
And step eleven, converting the logic gate matrix into an approximation form of Clifford + T, outputting a line, and stopping the algorithm. If the quantum chip is not in the fully discrete class, turning to step twelve;
step twelve, for 'non-pervasive', the quantum chip does not support the logic gate of the common type;
step thirteen, the algorithm issues an error warning and the program is terminated.
The following describes the detailed steps of the quantum instruction set pre-judgment algorithm, the input of which is the quantum instruction set, and the output of which is the classification of the quantum instruction set.
The first step, judge whether there is any rotation order in the order set (U3), if there is, output "any rotation class", if there is not, enter the second step.
And secondly, judging whether at least two logic gates continuously rotating in independent directions exist in the instruction set, if so, outputting a 'double-continuous type', and if not, entering the third step.
And thirdly, judging whether a logic gate C1 continuously rotating in one direction and at least one logic gate Dn with a fixed rotation angle in the other direction exist in the instruction set, if not, outputting 'non-universal', and if so, turning to the fourth step.
And fourthly, sequentially executing a continuous basis conversion algorithm for the fixed logic gates, if the algorithm outputs at least one logic gate C2 which has a different angle from that of C1 and rotates continuously, outputting a single continuous single discrete class, and if not, entering the fifth step.
And fifthly, for all logic gates rotating in fixed directions, if at least one pi/8 gate and at least one gate with an angle different from pi are contained, outputting the 'full discrete class', and if not, outputting the 'unpopular'.
In the scheme, a double continuous class construction algorithm accepts two logic gates C1 and C2 which rotate continuously, and any single-qubit logic gate U, and an output U is converted into a circuit of which C1 and C2 are basic logic gates.
The continuous basis transform algorithm in the above embodiment accepts a continuously rotating logic gate C and a fixed operational matrix logic gate D, returns a rotation angle of logic gate C 'different from C, and C' can be constructed by C and D. The steps are firstly to calculate
And judging whether the rotation angles of C and C' are the same. If so, return to null. If not, return to C'.
By adopting the technical scheme, the following technical effects are realized:
1. the quantum chip can process the universal basic quantum logic gate scheme given by most quantum computers.
2. The quantum chip can handle continuous rotation, fixed rotation, respectively. And it is divided into several cases to be processed separately.
3. And giving out basic logic gates which cannot form a universal quantum logic gate set for the quantum computer, and sending out error signal prompts.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
Example two
In this embodiment, a conversion apparatus of a single-quantum-bit logic gate is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description already made is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
According to another embodiment of this document, there is provided a conversion apparatus for single-qubit logic gates, comprising:
the acquisition module is used for acquiring a set of first single-quantum-bit logic gates supported by a quantum chip;
a determining module, configured to determine that a logic gate type to which the first single-quantum-bit logic gate belongs is a first logic gate type, where the logic gate type includes one of: any rotation class, bicontinuous class, single continuous single discrete class and non-universal class;
and the conversion module is used for converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
By adopting the technical scheme, the type of the single-quantum-bit logic gate supported by the quantum chip is obtained, and the second single-quantum-bit logic gate to be operated on the quantum chip is converted into the logic gate of the type, so that the subsequent operation on the quantum chip is facilitated, wherein the type may be one of the following types: random rotation class, bicontinuous class, single continuous single discrete class, non-universal class. By adopting the technical scheme, the problem that the single-quantum-bit logic gate cannot operate on different quantum chips in the related technology is solved, the application ranges of the quantum chips and the single-quantum-bit logic gate are increased in a bidirectional mode, and the quantum computing speed is increased.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
EXAMPLE III
Embodiments of the present application also provide a storage medium. Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:
s1, acquiring a set of first single-quantum-bit logic gates supported by the quantum chip;
s2, determining that the logic gate type to which the first single-quantum-bit logic gate belongs is a first logic gate type, wherein the logic gate type includes one of: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class and non-universal class;
and S3, converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Embodiments of the present application further provide an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the above method embodiments.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s1, acquiring a set of first single-quantum-bit logic gates supported by the quantum chip;
s2, determining that the logic gate type to which the first single-quantum-bit logic gate belongs is a first logic gate type, wherein the logic gate type includes one of: any rotation class, bicontinuous class, single continuous single discrete class, full discrete class and non-universal class;
and S3, converting a second single-quantum-bit logic gate to be operated by the quantum chip according to the type of the first logic gate.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present application described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. A method for converting a single qubit logic gate, comprising:
acquiring a set of first single-quantum-bit logic gates supported by a quantum chip;
determining a logic gate type to which the first set of single-quantum-bit logic gates belongs as a first logic gate type, wherein the logic gate types are sequentially determined as one of: bicontinuous, unicontinuous, monodispersed, fully discretized, and other classes;
if the first logic gate type is one of a bicontinuous type, a single continuous single discrete type and a full discrete type, converting a second single-quantum-bit logic gate to be operated by the quantum chip into the type of the single-quantum-bit logic gate supported by the quantum chip according to the first logic gate type;
if the first logic gate type is other types, an error warning is sent out;
wherein the content of the first and second substances,
when detecting that any rotation instruction is included in the set, determining that the type of the logic gate is any rotation type;
when determining that at least two continuous rotation logic gates in different directions exist in the set, determining that the type of the logic gate is a bicontinuous class;
upon determining that one continuous rotation logic gate C3, and at least one fixed rotation angle logic gate D1 are present in the set, determining that the logic gate type is a single continuous single discrete class;
when determining that at least two logic gates with fixed operation matrixes exist in the set, determining that the type of the logic gate is a fully discrete type;
and when the logic gate type is not any one of the above types, determining the logic gate type as other types.
2. The method of claim 1, wherein transforming a second single qubit logic gate of the quantum chip to be operated according to the first logic gate type comprises:
in the case that the first logic gate type is a double-continuous type, obtaining two continuous rotation logic gates C1 and C2 in different rotation directions from a plurality of first single-quantum-bit logic gates;
constructing a first bi-continuous class model from the continuously rotating logic gates C1 and C2, translating the second single-quantum-bit logic gate from the first bi-continuous class model.
3. The method of claim 1, wherein transforming a second single qubit logic gate of the quantum chip to be operated according to the first logic gate type comprises:
under the condition that the first logic gate type is a single continuous single discrete class, obtaining a continuous rotation logic gate C5 and at least one fixed rotation angle logic gate D2 from a plurality of first single-quantum bit logic gates, and performing base-changing conversion on at least one fixed rotation angle logic gate D2 to obtain a continuous rotation logic gate C6, wherein the rotation directions of the continuous rotation logic gate C5 and the fixed rotation angle logic gate D2 are different, and the rotation directions of the continuous rotation logic gate C5 and the continuous rotation logic gate C6 are different;
constructing a second bicontinuous type model from the continuously rotating logic gate C5 and the continuously rotating logic gate C6, transforming the second single-quantum-bit logic gate from the second bicontinuous type model.
4. The method of claim 1, wherein after converting the second single qubit logic gate to be operated by the quantum chip to the type of single qubit logic gate supported by the quantum chip, the method further comprises:
and running the converted second single-quantum-bit logic gate on the quantum chip.
5. An apparatus for inverting a single qubit logic gate, comprising:
the acquisition module is used for acquiring a set of first single-quantum-bit logic gates supported by a quantum chip;
a determining module, configured to determine that a logic gate type to which the first set of single-quantum-bit logic gates belongs is a first logic gate type, where the logic gate type is sequentially determined as one of: bicontinuous, unicontinuous, monodispersed, fully discretized, and other classes;
a conversion module to:
if the first logic gate type is one of a bicontinuous type, a single continuous single discrete type and a full discrete type, converting a second single-quantum-bit logic gate to be operated by the quantum chip into the type of the single-quantum-bit logic gate supported by the quantum chip according to the first logic gate type;
if the first logic gate type is other types, an error warning is sent out;
wherein the content of the first and second substances,
when detecting that any rotation instruction is included in the set, determining that the type of the logic gate is any rotation type;
when determining that at least two continuous rotation logic gates in different directions exist in the set, determining that the type of the logic gate is a bicontinuous class;
upon determining that one continuous rotation logic gate C3, and at least one fixed rotation angle logic gate D1 are present in the set, determining that the logic gate type is a single continuous single discrete class;
when determining that at least two logic gates with fixed operation matrixes exist in the set, determining that the type of the logic gate is a fully discrete type;
and when the logic gate type is not any one of the above types, determining the logic gate type as other types.
6. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when executed.
7. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811082325.3A CN109543845B (en) | 2018-09-17 | 2018-09-17 | Conversion method and device of single quantum bit logic gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811082325.3A CN109543845B (en) | 2018-09-17 | 2018-09-17 | Conversion method and device of single quantum bit logic gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109543845A CN109543845A (en) | 2019-03-29 |
| CN109543845B true CN109543845B (en) | 2020-04-14 |
Family
ID=65841283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811082325.3A Active CN109543845B (en) | 2018-09-17 | 2018-09-17 | Conversion method and device of single quantum bit logic gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109543845B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110598867B (en) * | 2019-09-17 | 2023-08-08 | 本源量子计算科技（合肥）股份有限公司 | Quantum state information conversion method |
| CN113420883B (en) * | 2021-06-28 | 2022-11-22 | 山东浪潮科学研究院有限公司 | Method and equipment for quantum programming frame to adapt to quantum computer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1761941A (en) * | 2003-03-19 | 2006-04-19 | 皇家飞利浦电子股份有限公司 | Type conversion unit in a multiprocessor system |
| WO2013035512A1 (en) * | 2011-09-09 | 2013-03-14 | 公益財団法人国際超電導産業技術研究センター | Superconducting single magnetic flux quantum integrated circuit device |
| CN107038141A (en) * | 2016-10-28 | 2017-08-11 | 章美前 | A kind of quantum chip |
| CN108334952A (en) * | 2017-11-24 | 2018-07-27 | 南京航空航天大学 | A kind of novel universal quantum door and quantum wire optimization method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1870015A (en) * | 2006-06-28 | 2006-11-29 | 中山大学 | Cooperative quantum computer architecture structural conceptual |
| CN107977541B (en) * | 2018-01-17 | 2021-11-09 | 合肥本源量子计算科技有限责任公司 | Method for optimizing quantum circuit simulation |
-
2018
- 2018-09-17 CN CN201811082325.3A patent/CN109543845B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1761941A (en) * | 2003-03-19 | 2006-04-19 | 皇家飞利浦电子股份有限公司 | Type conversion unit in a multiprocessor system |
| WO2013035512A1 (en) * | 2011-09-09 | 2013-03-14 | 公益財団法人国際超電導産業技術研究センター | Superconducting single magnetic flux quantum integrated circuit device |
| CN107038141A (en) * | 2016-10-28 | 2017-08-11 | 章美前 | A kind of quantum chip |
| CN108334952A (en) * | 2017-11-24 | 2018-07-27 | 南京航空航天大学 | A kind of novel universal quantum door and quantum wire optimization method |
Non-Patent Citations (2)
| Title |
|---|
| "新型量子逻辑门的构造方法的研究与实现";陈赛;《万方数据》;20171123;全文 * |
| "量子信息处理中量子线路的优化构造与实现";李文东;《万方数据》;20121227;第2章 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109543845A (en) | 2019-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110363301B (en) | Quantum line processing method, quantum line processing device, storage medium, and electronic device | |
| CN109376867B (en) | Processing method and device of two-quantum-bit logic gate | |
| CN108363737B (en) | Data format conversion method, device and equipment | |
| CN109543845B (en) | Conversion method and device of single quantum bit logic gate | |
| CN115374186B (en) | Data processing method based on big data and AI system | |
| CN112633507A (en) | Method and device for encoding complex vector to quantum circuit | |
| CN110245029A (en) | A kind of data processing method, device, storage medium and server | |
| CN111130828B (en) | Intelligent network distribution method and device and terminal equipment | |
| US11126642B2 (en) | System and method for generating synthetic data for minority classes in a large dataset | |
| CN112181509A (en) | Ensuring data consistency between modular devices and external systems | |
| CN112816959B (en) | Clustering method, device, equipment and storage medium for vehicles | |
| CN110728118A (en) | Cross-data-platform data processing method, device, equipment and storage medium | |
| CN111200608B (en) | Link information processing method and device | |
| CN107944798A (en) | Intelligent goods dispatch method and system | |
| CN114117063A (en) | Entity alignment method, device, electronic equipment and computer readable storage medium | |
| CN115549854A (en) | Cyclic redundancy check method, cyclic redundancy check device, storage medium and electronic device | |
| CN112073505A (en) | Method for unloading on cloud server, control device and storage medium | |
| CN117850753B (en) | Method, device, equipment and medium for generating interface code based on someip matrix | |
| CN117200804A (en) | Encoding and decoding methods, devices, equipment and storage medium | |
| CN116860486A (en) | Information transmission method, producer device, and computer-readable storage medium | |
| CN114282000A (en) | Text clustering method, text clustering device, text clustering medium and electronic device based on quantum computation | |
| DE102015119795A1 (en) | OPC UA specific, hierarchical coder structure for exchanging data and associated methods | |
| CN113835708A (en) | Internet of things communication protocol processing method, electronic equipment and storage medium | |
| CN117873883A (en) | Method and device for generating test case set | |
| CN115081596A (en) | Convolution neural network model reasoning method, device, equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |