CN109543331B - Method for establishing resistance model - Google Patents
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Abstract
The invention provides a method for establishing a resistance model, which is used for self-aligning a source electrode and comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a non-memory cell area; establishing a first resistance model for the memory cell region; establishing a second resistance model for the non-memory cell region; and compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate. Therefore, the established third resistance model can obtain an accurate relation between the resistance and the layout, the unreasonable situation that the resistance value of the unit length is increased along with the increase of the resistance width in the resistance model obtained by the fact that the self-aligned source resistance is the non-uniform resistance is avoided, the definition of the original square resistance is optimized, the simulation precision of the resistance performance of the whole self-aligned source and the accuracy of the performance prediction of the subsequent reduction unit can be improved, and the whole erasing uniformity of a wafer and the product yield are further improved.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a method for establishing a resistance model.
Background
Flash Memory (Flash Memory) is a Memory that is non-volatile for long life and retains stored data information when powered off, with data deletions not being in individual bytes but in fixed blocks, typically 256KB to 20MB in block size. Flash memory is a variation of electrically erasable read-only memory (EEPROM) which, unlike EEPROM, can be erased and rewritten on a byte level rather than being erased on an entire chip, whereas most chips of flash memory require block erasure. Flash memory is commonly used to store settings information, such as data in a basic program (BIOS) of a computer, a Personal Digital Assistant (PDA), a digital camera, etc., because it can still store data when powered off.
Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, electrical programmability, and erasability. At present, the flash memory unit mainly carries out process operation at a 65nm technology node, and with the increasing requirement on a high-capacity flash memory, if the existing technology node is utilized, the number of chips on each silicon chip is reduced. This means that the performance of the flash memory cell is affected by the need to reduce the size of the flash memory cell, both the width of the active area of the flash memory cell and the length of the channel.
The self-alignment-source (SAS) technique proposed to increase the density of flash memory cells uses the already formed flash memory control gate as a basis for alignment. This structure has become the mainstream technology for the 65nm technology node. However, since the etching is performed first and then the ion implantation is performed, the Source (Source) end is diffused in the transverse direction differently, which results in the difference of the erasing speed. It is difficult to coordinate the erase speed differences in the wafer yield test, and sometimes it is necessary to increase the erase time or voltage intentionally for the overall erase uniformity (to complete the erase of slow/fast cells simultaneously), but for fast cells, the current leakage may cause the erase failure of the entire flash memory cell.
There is also a method in the prior art for exchanging the sequence of SAS etching and ion implantation to form the source that is theoretically feasible but requires ion implantation into the source
Requires a large amount of energy below the silicon oxide layer, which is unacceptable for elemental silicon.
The existing resistor model processes the resistance of the self-aligned source terminal in a normal resistor manner, that is, calculates according to the size on the layout (layout), and the formula is R = L/W · Rs (please refer to fig. 1, where R is the total resistance, L is the length of the resistor region, W is the width of the resistor region, and Rs is the square resistance of the resistor region). Where the sheet resistance Rs is defined as the resistance per unit length, in ohm/m. According to the mode of extracting the resistance from the resistance model, when SAS resistors with different widths are measured, the larger the resistance width is, the larger the resistance per unit length is, on one hand, the result is different from the conventional recognition, on the other hand, for a layout which is not integral multiple of the original test structure, the measured total resistance has errors, and the SAS resistor is a non-uniform resistor, so that the existing calculation mode is unreasonable.
Therefore, it is necessary to invent a resistance model establishing method capable of accurately calculating the self-aligned source.
Disclosure of Invention
The invention aims to provide a resistance model establishing method to solve the problem that the resistance value of a unit length is unreasonably increased along with the increase of the resistance width in the resistance model in the prior art.
In order to solve the above technical problem, the present invention provides a method for establishing a resistance model, which is used for self-aligning a source resistance, and the method for establishing the resistance model includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a non-memory cell area;
establishing a first resistance model for the memory cell region;
establishing a second resistance model for the non-memory cell region;
and compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate.
Optionally, in the method for establishing a resistance model, establishing a first resistance model for the memory cell region includes:
dividing the memory cell area into an active area, a shallow trench isolation bottom and an active area side wall;
obtaining resistance test structures of the active area, the shallow trench isolation bottom and the active area side wall;
respectively calculating the resistance values of the three resistance test structures per unit length;
and respectively combining the resistance values of the respective areas in unit length according to the sizes of the active area, the shallow trench isolation bottom and the active area side wall included in the memory cell to establish a first resistance model of the memory cell.
Optionally, in the method for establishing the resistance model, the resistivity in each of the three regions, namely the active region, the bottom of the shallow trench isolation, and the sidewall of the active region, is the same, and the resistivity in different regions is different.
Optionally, in the method for establishing the resistance model, calculating the resistance values per unit length in the three resistance test structures respectively includes:
the same resistance width values are taken for the three regions, and the resistance lengths of unit length in the three regions are respectively measured;
respectively applying a certain voltage V to the three regions, and measuring corresponding current I;
and respectively calculating the resistance value of each unit length of the three regions according to a formula Rsqr = V/I, wherein Rsqr is the resistance value of the unit length.
Optionally, in the method for establishing the resistance model, the non-memory cell region is connected to the memory cell region.
Optionally, in the method for establishing a resistance model, a second resistance model is established for the non-memory cell region according to the sheet resistance of the non-memory cell region.
Optionally, in the method for establishing a resistance model, establishing a second resistance model for the non-memory cell region includes:
measuring the size of the non-memory cell area;
calculating according to a formula R = L/W Rs suitable for the non-memory cell region, wherein R is a resistance of the resistance region in the non-memory cell region, L is a length of the resistance region in the non-memory cell region, W is a width of the resistance region in the non-memory cell region, and Rs is a sheet resistance of the resistance region in the non-memory cell region.
Optionally, in the method for establishing the resistance model, the functional relation of the first resistance model is as follows: y =0.0513x 2 -10.383x +833.85, where x is the resistance width of the memory cell region and y is the resistance of the memory cell region.
Optionally, in the method for establishing the resistance model, the functional relation of the third resistance model is as follows: y =0.0112x 2 -1.8349x +85.45, wherein x is the resistance width of the semiconductor substrate and y is the resistance of the semiconductor substrate.
In the method for establishing the self-aligned source resistance model provided by the invention, the method for establishing the resistance model comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a non-memory cell area; establishing a first resistance model for the memory cell region; establishing a second resistance model for the non-memory cell region; and compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate. Therefore, the established third resistance model can obtain an accurate relation between the resistance and the layout, errors generated in the total resistance model established for the layout which is not integral multiple of the original test structure are avoided, and the inventor finds that the resistance model obtained by the existing calculation mode has unreasonable points that the resistance value of unit length is increased along with the increase of the resistance width because the SAS resistance is non-uniform resistance. According to the invention, the original square resistor definition is optimized according to the problem that the resistivity of each area in the characteristics of the SAS resistor is different, the square resistor defined according to the layout is optimized into the resistor defined according to the unit, and each area is independently defined, so that the simulation precision of the resistance performance of the integral self-aligned source electrode and the accuracy of the prediction of the subsequent reduced unit performance can be improved, and the integral erasing uniformity and the product yield of the wafer are further improved.
Drawings
FIG. 1 is a layout of a self-aligned source in a flash memory cell;
FIG. 2 is a functional relationship curve of the first resistance model according to the present embodiment;
FIG. 3 is a schematic flow chart of a method for establishing a resistance model according to the present embodiment;
FIG. 4 is a schematic flow chart illustrating the process of establishing a first resistance model according to the present embodiment;
FIG. 5 is a cross-sectional view of a memory cell region of the present embodiment;
FIG. 6 is a schematic flow chart of the present embodiment for calculating the unit length resistance values in the three resistance test structures respectively;
FIG. 7 is a schematic flowchart illustrating a second resistance model according to the present embodiment;
fig. 8 is a functional relationship curve of the third resistance model according to the present embodiment.
Detailed Description
A resistance model establishing method for processing the resistance of a self-aligned source terminal according to a general resistance mode is characterized in that calculation is carried out according to the size on a layout, SAS resistances with different widths are measured, the larger the resistance width is, the larger the resistance of the unit length is, on one hand, the result is different from conventional knowledge, on the other hand, for the layout which is not integral multiple of the original test structure, the measured total resistance has errors, and the calculation mode of the resistance model establishing method is unreasonable because the SAS resistance is non-uniform resistance.
In order to solve the above technical problem, the present invention provides a method for establishing a resistance model, which is used for self-aligning a source resistance, and the method for establishing the resistance model includes: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a non-memory cell area; establishing a first resistance model for the memory cell region; establishing a second resistance model for the non-memory cell region; and compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate.
To make the objects, advantages and features of the present invention more apparent, the method for establishing the resistance model according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings are intended to show different emphasis, sometimes in different proportions.
First, referring to fig. 3, the present embodiment provides a method for establishing a resistance model of a self-aligned source, where the method for establishing the resistance model includes:
step S10: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell region and a non-memory cell region (not shown in the figure), and the non-memory cell region is connected with the memory cell region;
step S11: establishing a first resistance model for the memory cell region;
step S12: establishing a second resistance model for the non-memory cell region;
step S13: and compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate.
The third resistance model established through the steps can obtain an accurate relation between the resistance and the layout, errors of a total resistance model established for the layout which is not integral multiple of the original test structure are avoided, and the inventor finds that the resistance model obtained through the existing calculation mode shows unreasonable points that the resistance value of the unit length is increased along with the increase of the resistance width because the SAS resistance is non-uniform resistance. According to the invention, the original square resistance definition is optimized according to the problem that the resistivity of each area in the characteristics of the SAS resistor is different, the square resistance defined according to the layout is optimized into the resistor defined according to the unit, and each area is independently defined, so that the simulation precision of the resistance performance of the integral self-aligned source electrode and the accuracy of the performance prediction of the subsequent reduction unit can be improved, and the integral erasing uniformity and the product yield of the wafer are further improved.
Referring to fig. 4, preferably, step S11: establishing a first resistance model for the memory cell region includes:
step S110: the memory cell area is divided into an active area, a shallow trench isolation bottom and an active area side wall, wherein the resistivity of the active area, the shallow trench isolation bottom and the active area side wall is the same in each area, and the resistivity of different areas is different. Defining the resistivity of the side wall of the active region as rho 1, the length as L1 and the depth as D1 as shown in FIG. 5; defining the resistivity of the active region as rho 2, the length as L2 and the depth as D2; defining the resistivity of the bottom of the shallow trench isolation as rho 3, the length as L3 and the depth as D3, and using data in the later step of establishing a model is more convenient.
Step S111: obtaining resistance test structures of the active area, the shallow trench isolation bottom and the active area side wall;
step S112: respectively calculating the resistance values of the three resistance test structures per unit length;
step S113: and respectively combining the resistance values of the respective areas in unit length according to the sizes of the active area, the shallow trench isolation bottom and the active area side wall included in the memory cell to establish a first resistance model of the memory cell.
Through the steps, according to the characteristics of different resistivities of the three regions, namely the active region, the shallow trench isolation bottom and the active region side wall, contained in the memory cell, the resistance value of unit length is calculated for the three regions respectively, and a first resistance model representing the resistance of the memory cell region is established by combining the size of each region.
Referring to fig. 6, preferably, step S112: respectively calculating the resistance values per unit length in the three resistance test structures comprises the following steps:
step S1120: measuring the resistance widths of the three regions, preferably, measuring the resistance widths of the three regions within a range of 60nm to 100nm, for example, measuring the resistance widths of 80nm, wherein the resistance lengths of the active region is 80nm, the bottom of the shallow trench isolation is 70nm, and the sidewall of the active region is 300nm;
step S1121: respectively applying a certain voltage V to the three regions, and measuring corresponding current I;
step S1122: and respectively calculating the resistance value of each unit length of the three regions according to a formula Rsqr = V/I, wherein Rsqr is the resistance value of the unit length.
By the steps, the average value is obtained according to a plurality of groups of experimental data, the resistance value of each unit length in the resistance test structure of the active area, the shallow groove isolation bottom and the active area side wall is more accurately obtained, and the first resistance model is conveniently established in the next step.
Referring to fig. 7, preferably, a second resistance model is established for the non-memory cell region according to the sheet resistance of the non-memory cell region, and step S12: establishing a second resistance model for the non-memory cell region includes:
step S120: measuring the size of the non-memory cell region, specifically, measuring the resistance R of the resistance region in the non-memory cell region, the length L of the resistance region in the non-memory cell region, and the width W of the resistance region in the non-memory cell region;
step S121: and calculating according to a formula R = L/W Rs suitable for the non-storage unit area, wherein the Rs is the square resistance of the resistance area in the non-storage unit area.
Through the steps, due to the characteristics of the non-memory cell region, a second resistance model can be established for the non-memory cell region according to the square resistance, the average value of the second resistance model is obtained through multiple experiments, and the second resistance model of the non-memory cell region is more accurately extracted.
Referring to fig. 2, in the present embodiment, the functional relation of the first resistance model is as follows: y =0.0513x 2 -10.383x +833.85, where x is the resistance width of the memory cell region and y is the resistance of the memory cell region. The resistance of the edge part of the memory cell area and the resistance of the middle part of the memory cell area are respectively measured through experiments, the resistance of the edge part of the memory cell area and the resistance of the middle part of the memory cell area are compounded according to the characteristics of the memory cell area, the middle value is obtained, the functional relation of the first resistance model is expressed more accurately and clearly, and a foundation is laid for subsequently extracting the resistance of the whole semiconductor substrate.
Referring to fig. 8, in the present embodiment, the functional relation of the third resistance model is as follows: y =0.0112x 2 -1.8349x +85.45, wherein x is the resistance width of the semiconductor substrate and y is the resistance of the semiconductor substrate. The third resistance model overcomes the defect that the resistance value of unit length increases along with the increase of the resistance width in the resistance model obtained by the existing calculation modeAnd the relationship between the self-aligned source resistance and the layout is obtained accurately, so that the performance of the semiconductor substrate can be simulated more accurately.
In summary, the method for establishing the resistance model provided by the invention has the following advantages:
the established third resistance model can obtain an accurate relation between the resistance and the layout, avoids generating errors on the total resistance model established by the layout which is not integral multiple of the original test structure, and avoids unreasonable situation that the resistance value of unit length is increased along with the increase of the resistance width in the resistance model obtained by the existing calculation mode because the SAS resistance is non-uniform resistance.
Furthermore, according to the problem that the resistivity of each area in the characteristics of the SAS resistor is different, the original square resistor definition is optimized, the square resistor defined according to the layout is optimized to be the resistor defined according to the unit, and each area is independently defined, so that the simulation precision of the resistance performance of the integral self-aligned source electrode and the accuracy of performance prediction of the subsequent reduced unit can be improved.
Furthermore, the overall erasing uniformity and the product yield of the wafer are improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A method for establishing a resistance model is used for self-aligning a source electrode resistor, and is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a non-memory cell area;
establishing a first resistance model for the memory cell region;
establishing a second resistance model for the non-memory cell region;
compounding the first resistance model and the second resistance model to obtain a third resistance model corresponding to the semiconductor substrate;
wherein establishing a first resistance model for the memory cell region comprises:
dividing the memory cell area into an active area, a shallow trench isolation bottom and an active area side wall;
obtaining resistance test structures of the active area, the shallow groove isolation bottom and the active area side wall;
respectively calculating the resistance values of the three resistance test structures per unit length;
according to the sizes of the active area, the shallow trench isolation bottom and the active area side wall which are contained in the memory cell, respectively combining the resistance values of the respective areas in unit length to establish a first resistance model of the memory cell;
establishing a second resistance model for the non-memory cell according to the square resistance of the non-memory cell region;
establishing a second resistance model for the non-memory cell region includes:
measuring the size of the non-memory cell area;
calculating according to a formula R = L/W Rs suitable for the non-memory cell region, wherein R is a resistance of the resistance region in the non-memory cell region, L is a length of the resistance region in the non-memory cell region, W is a width of the resistance region in the non-memory cell region, and Rs is a sheet resistance of the resistance region in the non-memory cell region.
2. The method for establishing a resistance model according to claim 1, wherein the resistivity in each of the three regions of the active region, the bottom of the shallow trench isolation and the sidewall of the active region is the same, and the resistivity in different regions is different.
3. The method for establishing the resistance model according to claim 1, wherein the step of calculating the resistance values per unit length in the three resistance test structures respectively comprises:
the same resistance width values are taken for the three regions, and the resistance lengths of unit length in the three regions are respectively measured;
respectively applying a certain voltage V to the three regions, and measuring corresponding current I;
and respectively calculating the resistance value of each unit length of the three regions according to a formula Rsqr = V/I, wherein Rsqr is the resistance value of the unit length.
4. The method for establishing a resistance model according to claim 1, wherein the non-memory cell region is connected to the memory cell region.
5. The method of establishing a resistance model of claim 1, wherein the first resistance model has a functional relationship of: y =0.0513x 2 -10.383x +833.85, where x is the resistance width of the memory cell region and y is the resistance of the memory cell region.
6. The method of establishing a resistance model of claim 1, wherein the functional relationship of the third resistance model is: y =0.0112x 2 -1.8349x +85.45, where x is the resistance width of the semiconductor substrate and y is the resistance of the semiconductor substrate.
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| CN107679261A (en) * | 2017-08-11 | 2018-02-09 | 上海集成电路研发中心有限公司 | The modeling method of dead resistance between a kind of MOS device source and drain and substrate |
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| US9141733B2 (en) * | 2013-11-20 | 2015-09-22 | International Business Machines Corporation | Method, system, and computer program product for modeling resistance of a multi-layered conductive component |
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| CN102254846A (en) * | 2011-07-04 | 2011-11-23 | 上海宏力半导体制造有限公司 | Method for simulating resistance of metal silicide layer in semiconductor device |
| CN107391849A (en) * | 2017-07-25 | 2017-11-24 | 上海华力微电子有限公司 | Resistance model for prediction and its modification method |
| CN107679261A (en) * | 2017-08-11 | 2018-02-09 | 上海集成电路研发中心有限公司 | The modeling method of dead resistance between a kind of MOS device source and drain and substrate |
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