CN109542625A

CN109542625A - A kind of storage resource control method, device and electronic equipment

Info

Publication number: CN109542625A
Application number: CN201811444821.9A
Authority: CN
Inventors: 葛海亮
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-11-29
Filing date: 2018-11-29
Publication date: 2019-03-29

Abstract

The embodiment of the present invention provides a kind of storage resource control method, device and electronic equipment, and the first FPGA card uses storage resource according to first resource table, and updates；The second FPGA card is sent by updated first resource table, to indicate that the second FPGA card updates Secondary resource table according to the updated first resource table；First FPGA card obtains the update message for carrying Secondary resource table to be updated；First FPGA card updates the first resource table according to the Secondary resource table to be updated got；Wherein, first register configuration is in the first FPGA card, and for second register configuration in the second FPGA card, the first resource table and the Secondary resource table include the record of all storage resources in server system.By configuring shared resource table, effective communication can be carried out between each FPGA, the dynamic configuration of the storage resource of whole system is realized, effectively improves the service efficiency of storage resource.

Description

Storage resource control method and device and electronic equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for controlling storage resources, and an electronic device.

Background

In recent years, as data is growing exponentially, data centers need to maintain a balance between large-scale performance demands and operational efficiency. In order to achieve both performance and efficiency, a new heterogeneous computing architecture is imperative, and among them, an FPGA (Field Programmable Gate Array) as an accelerator is becoming the mainstream of the accelerated application of the data center.

Referring to fig. 1, a schematic diagram of a current FPGA and server interconnection architecture according to an embodiment of the present invention is shown in fig. 1, where one end of the FPGA card is usually connected to HOST (chinese: HOST) at the server end through PCIE (Peripheral component interconnect Express, chinese: high speed serial computer expansion bus) golden finger, and the other end of the FPGA card is externally connected to a Memory External Memory2, including but not limited to DDR (DDR) devices. In the FPGA card, the function of a BSP (Chinese: FPGA acceleration basic function logic Support Package) part is to realize the communication between a Kernel (Chinese: FPGA acceleration algorithm realization unit) of the FPGA card and a HOST at a server end, the Kernel part is a module for realizing a hardware acceleration function through FPGA hardware logic, and the HOST at the server end is also interconnected with a Memory 1. In such a system architecture, the FPGA card can interact with information in the HOST on the server side and can access the memories including the external Memory2 and Memory1 to each other.

However, through research, the inventor finds that when a plurality of FPGA cards are inserted into one or more servers, there are many storage resources for the servers, including memories inside the FPGA cards and external memories interconnected with the FPGA cards, and how to manage dynamic and effective use of the storage resources becomes a systematic problem. Aiming at management and use of storage resources, a curing logic form is usually used at present, namely, when the storage resources are allocated for the first time, the FPGA is used for curing, the use of the storage resources is changed every time, and the FPGA logic needs to be changed and programmed again.

Therefore, how to dynamically reconfigure time storage resources and improve the resource utilization efficiency is an urgent technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a method, an apparatus and an electronic device for controlling storage resources, which are used to solve the problems in the prior art that dynamic reconfiguration of storage resources is difficult and resource utilization efficiency is low.

To achieve the above and other related objects, according to a first aspect of the present invention, an embodiment of the present invention provides a storage resource control method, including:

the first FPGA card uses storage resources according to a first resource table stored in a first register and updates the first resource table;

the first FPGA card sends the updated first resource table to a second FPGA card to instruct the second FPGA card to update a second resource table stored in a second register according to the updated first resource table;

the method comprises the steps that a first FPGA card obtains an update message from a second FPGA card, wherein the update message carries a second resource table to be updated;

the first FPGA card updates the first resource table according to the acquired second resource table to be updated;

the first register is configured in a first FPGA card, the second register is configured in a second FPGA card, and the first resource table and the second resource table both comprise records of all storage resources in the server system.

Optionally, the first FPGA card uses the storage resource according to a first resource table stored in the first register, including:

the method comprises the steps that a first FPGA card obtains a bandwidth request value of a program to be operated;

the first FPGA card selects an idle storage resource matched with the bandwidth request value from the first resource table according to the bandwidth request value;

the first resource table comprises records of storage resources which are sorted according to the read-write operation speed.

the first FPGA card acquires the priority of a program to be run;

the first FPGA card selects idle storage resources matched with the priority from the first resource table according to the priority;

the first resource table comprises records of storage resources which are sorted according to the read-write priority.

Optionally, before the first FPGA card sends the updated first resource table to the second FPGA card, the method further includes:

and the first FPGA card sends a first instruction to the second FPGA card to indicate the second FPGA card to forbid modifying the second resource table.

Optionally, the method further comprises:

the first FPGA card acquires the priority of the second FPGA card;

and when the first FPGA card receives the update message from the second FPGA card and the priority of the second FPGA card is greater than that of the first FGPA card, sending a second instruction to the second FPGA card to indicate that the second FPGA card allows the modification of the second resource table.

According to a second aspect of the present invention, an embodiment of the present invention further provides a storage resource control apparatus, including:

the allocation module is used for using the storage resources according to the first resource table stored in the first register and updating the first resource table;

the sending module is used for sending the updated first resource table to the second FPGA card so as to instruct the second FPGA card to update the second resource table stored in the second register according to the updated first resource table;

the acquisition module is used for acquiring an update message from the second FPGA card, wherein the update message carries a second resource table to be updated;

the updating module is used for updating the first resource table according to the obtained second resource table to be updated;

Optionally, the allocation module is configured to,

acquiring a bandwidth request value of a program to be operated;

selecting an idle storage resource matched with the bandwidth request value from the first resource table according to the bandwidth request value;

Optionally, the allocation module is configured to,

acquiring the priority of a program to be run;

according to the priority, selecting idle storage resources matched with the priority from the first resource table;

Optionally, the sending module is further configured to,

before sending the updated first resource table to the second FPGA card, sending a first instruction to the second FPGA card to indicate the second FPGA card to forbid modifying the second resource table; or,

obtaining a priority of a second FPGA card

According to a third aspect of the present invention, there is also provided an electronic device, including a first FPGA card and a second FPGA card,

As described above, the storage resource control method, device and electronic device provided in the embodiments of the present invention have the following beneficial effects: the first FPGA card uses storage resources according to a first resource table stored in a first register and updates the first resource table; the first FPGA card sends the updated first resource table to a second FPGA card to instruct the second FPGA card to update a second resource table stored in a second register according to the updated first resource table; the method comprises the steps that a first FPGA card obtains an update message from a second FPGA card, wherein the update message carries a second resource table to be updated; the first FPGA card updates the first resource table according to the acquired second resource table to be updated; the first register is configured in a first FPGA card, the second register is configured in a second FPGA card, and the first resource table and the second resource table both comprise records of all storage resources in the server system. Through configuring the shared resource table, the FPGAs can be effectively communicated, the dynamic configuration of the storage resources of the whole system is realized, and the use efficiency of the storage resources is effectively improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic diagram of a current FPGA and server interconnection architecture according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an interconnection architecture including a plurality of FPGA cards and a plurality of server terminals according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an FPGA card according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method for controlling storage resources according to an embodiment of the present invention;

fig. 5 is a flowchart illustrating a resource allocation method according to an embodiment of the present invention;

fig. 6 is a flowchart illustrating another resource allocation method according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a resource table sharing control method according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a storage resource control apparatus according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a hardware structure of an electronic device that executes a storage resource control method according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Fig. 2 is a schematic diagram of an interconnection architecture including multiple FPGA cards and multiple server terminals according to an embodiment of the present invention. As shown in fig. 2, a server 1 end is interconnected with a first FPGA card, a server 2 end is interconnected with a second FPGA card, a server N-1 end is interconnected with an (N-1) th FPGA card, and a server N end is interconnected with the (N) th FPGA card, where N is a natural number, and the interconnection form between each server end and the corresponding FPGA card is not described herein again with reference to the description of the architecture shown in fig. 1. In the embodiment of the invention, a first FPGA card and a second FPGA card are interconnected, the first FPGA card is also interconnected with an (N-1) th FGPA card, the second FPGA card is interconnected with an (N) th FPGA card, and the (N-1) th FPGA card is interconnected with the (N) th FPGA card. The interconnection between the server and the FPGA card and the interconnection between the FPGA cards may be in the form of an ethernet optical port, which is not limited in the embodiment of the present invention. In addition, a Memory1_1 is further arranged inside the server 1, the first FPGA card is further interconnected with a Memory External Memory2_1, a Memory1_2 is further arranged inside the server 2, the second FPGA card is further interconnected with a Memory External Memory2_2, a Memory1_ N-1 is further arranged inside the server N-1, the (N-1) th FPGA card is further interconnected with a Memory External Memory2_ N-1, a Memory1_ N is further arranged inside the server N, and the (N) th FPGA card is further interconnected with a Memory External Memory2_ N.

Referring to fig. 3, which is a schematic structural diagram of an FPGA card according to an embodiment of the present invention, as shown in fig. 3, a storage resource agent management module (Memory Control Adapter) is implemented in the FPGA card by logic (including but not limited to a verilog or a hardware description language such as VHDL), where the storage resource agent management module has a register called a record reconfiguration register for recording information of storage resources in a system, and the register records a condition of the storage resources of the system. The condition of the storage resource can be described in a form of a resource table, for example, the storage resource includes identifiers, read-write permission, read-write speed, priority and the like of the server side, the FPGA card and the interconnected memory. The module is connected with the HOST server side (including but not limited to a PCIE interface form) on the architecture side, and the FPGA other modules on the side (including but not limited to a Kernel acceleration module) are further communicated with FPGA internal storage resources (including but not limited to on _ chip ram, rom and the like) and FPGA External storage resources External memory2 (including but not limited to DDR and the like devices). In the embodiment of the invention, the first FPGA card, the second FPGA card, the (N-1) th FPGA card and the (N) th FPGA card have the structures shown in FIG. 3.

In the embodiment of the present invention, with reference to the architectures shown in fig. 2 and fig. 3, a system formed by 2 FPGA cards and 2 server terminals is taken as an example to describe in detail a control method for a storage resource in the system, it should be noted that the architecture is only an exemplary architecture, and the storage resource control method provided in the embodiment of the present invention may also be applied to a scenario where a plurality of FPGA cards are configured on one server, and a plurality of server terminals and a plurality of FPGA cards are interconnected, for example, and is not described in detail in the embodiment of the present invention.

Referring to fig. 4, which is a schematic flow chart of a storage resource control method provided in the embodiment of the present invention, and as shown in fig. 4, the embodiment of the present invention shows a process in which a storage resource agent management module in a first FPGA card executes the storage resource control method:

step S101: and the first FPGA card uses the storage resource according to the first resource table stored in the first register and updates the first resource table.

In order to implement the resource configuration accuracy of the FPGA card and meet the requirements of different programs or services, in a first implementation case, referring to fig. 5, a flowchart of a resource allocation method provided in an embodiment of the present invention is shown in fig. 5, where the method includes the following steps:

step S1011: the first FPGA card acquires a bandwidth request value of a program to be operated.

The first FPGA card may obtain a bandwidth request value of the program to be executed, and in an exemplary embodiment, for example, the bandwidth request value of the program to be executed, which needs to be executed on the first FPGA card, is 100 kbps.

Step S1012: the first FPGA card selects an idle storage resource matched with the bandwidth request value from the first resource table according to the bandwidth request value; the first resource table comprises records of storage resources which are sorted according to the read-write operation speed.

The first FPGA card queries a first resource table, which in an exemplary embodiment, in connection with the system architecture shown in FIG. 2, when including the first FPGA, the second FPGA, and the server 1 side and the server 2 side, may include { External Memory2_1:200Kbps, occupied, priority 1}, { External Memory2_2:100Kbps, idle, priority 2}, { Memory1_1:300Kbps, idle, priority 3}, { Memory1_2:100Kbps, occupied, priority 4 }. Through the first resource table, it can be seen that in a system architecture including the first FPGA, the second FPGA, the server 1 side and the server 2 side, all storage resources, that is, an External Memory2_1 Memory interconnected with the first FPGA card can meet the read-write requirement of 200Kbps, the current state is occupied, and the priority is level 1; similarly, for other storage resources, the External Memory2_2 Memory interconnected with the second FPGA card can meet the read-write requirement of 100Kbps, the current state is idle, and the priority is 2; the Memory1_1 Memory of the server 1 end can meet the read-write requirement of 300Kbps, the current state is idle, and the priority is 3 level; the Memory1_2 at the server 2 can meet the read-write requirement of 100Kbps, the current state is occupied, and the priority is level 4. In addition, the priority is assigned to the entire storage resource in the order of priority 1, priority 2, priority 3, and priority 4.

According to the above embodiment, the bandwidth request value of the program to be executed is 100Kbps, the External Memory2_2 matches the bandwidth request value, and the External Memory2_2 is in an idle state, and the External Memory2_2 is allocated to the program to be executed on the first FGPA card.

In order to improve the efficiency of resource allocation, resources are allocated for different programs or services, refer to fig. 6, which is a flowchart of another resource allocation method provided in the embodiment of the present invention, and as shown in fig. 6, the method includes the following steps:

and S1013, the first FPGA card acquires the priority of the program to be operated.

In an exemplary embodiment, the first FPGA card acquires the priority of the program to be run as priority 3.

Step S1014: the first FPGA card selects idle storage resources matched with the priority from the first resource table according to the priority; the first resource table comprises records of storage resources which are sorted according to the read-write priority.

Similarly, according to the first resource table described in the above embodiment, it may be determined that the Memory1_1 Memory is in an idle state and has the same priority as the program to be executed, and then the first FPGA card allocates the Memory1_1 Memory to the program to be executed for use.

In addition, in order to implement sharing of the first resource table and the second resource table and prevent resource allocation conflict, in the first implementation case, before the first FPGA card allocates resources and executes subsequent steps, a first instruction may be further sent to the second FPGA card, where the first instruction is used to instruct the second FPGA card to prohibit modification of the second resource table. In specific implementation, the second resource table has the same form or structure as the first resource table, and the first resource table and the second resource table need to maintain sharing and information consistency in the resource allocation process.

In a second implementation case, referring to fig. 7, a flowchart of a resource table sharing control method according to an embodiment of the present invention is shown in fig. 7, where the method includes:

step S1015: the first FPGA card acquires the priority of the second FPGA card.

In an exemplary embodiment, priority levels of the first FPGA card and the second FPGA card may be established, and the FPGA cards of different priorities may allocate the resources for use.

Step S1016: and when the first FPGA card receives the update message from the second FPGA card and the priority of the second FPGA card is greater than that of the first FPGA card, sending a second instruction to the second FPGA card to indicate that the second FPGA card allows the modification of the second resource table.

When the first FPGA card receives an update message from the second FPGA card, the second FPGA card is represented to request resources, a resource request conflict possibly exists between the first FPGA card and the second FPGA card, and further when the priority of the second FPGA card is larger than that of the first FPGA card, the second FPGA card is represented to have higher priority, the first FPGA card sends a second instruction to the second FPGA card to indicate that the second FPGA card allows to modify the second resource table, and meanwhile, the first FPGA card performs resource configuration and updating of the first resource table after waiting for the second FPGA card to be updated.

When the priority of the first FPGA card is greater than the priority of the second FPGA card, the first instruction may be sent to the second FPGA card, and the second FPGA card is instructed to prohibit modifying the second resource table, that is, the second FPGA is suspended from performing storage resource allocation, so as to avoid a conflict.

Step S102: and the first FPGA card sends the updated first resource table to the second FPGA card so as to instruct the second FPGA card to update the second resource table stored in the second register according to the updated first resource table.

And when the resource allocation of the first FPGA card is completed, updating the first resource table. According to the description of the above embodiment, when the External Memory2_2 Memory is allocated to the program to be executed on the first FGPA card for use, the first resource table is updated to { External Memory2_1:200Kbps, occupied, priority 1}, { External Memory2_2:100Kbps, occupied, priority 2}, { Memory1_1:300Kbps, free, priority 3}, and { Memory1_2:100Kbps, occupied, priority 4}, and the updated first resource table is further sent to the second resource table to keep the information of the second resource table on the second FPGA card consistent.

Step S103: the first FPGA card acquires an update message from the second FPGA card, and the update message carries a second resource table to be updated.

Similarly, after the second FPGA card performs resource allocation, the updated second resource table also needs to be sent to the first FPGA card, so as to ensure that the first resource table on the first FPGA card is consistent with the second resource table on the second FPGA card.

Step S104: and the first FPGA card updates the first resource table according to the acquired second resource table to be updated.

And the first FPGA card updates the first resource table according to the acquired second resource table to be updated. In an exemplary embodiment, after the second FPGA card allocates and uses the Memory of the Memory1_1, the second resource table is updated to { External Memory2_1:200Kbps, occupied, priority 1}, { External Memory2_2:100Kbps, free, priority 2}, { Memory1_1:300Kbps, occupied, priority 3}, and { Memory1_2:100Kbps, occupied, priority 4 }. Further, the first FPGA card updates the first resource table to the content consistent with the second resource table according to the update message received in step S103, so as to keep the information consistent.

It should be noted that, in the embodiment of the present invention, only a system formed by 2 FPGA cards is taken as an example, and a first FPGA card is taken as an implementation subject to describe the control method of the storage resource, and the execution subject which does not represent the embodiment of the present invention is limited to the first FPGA card. In specific implementation, any one FPGA card in one system may be used as an implementation subject to implement the method, which is not limited in the embodiment of the present invention.

As can be seen from the description of the foregoing embodiment, in the storage resource control method provided in the embodiment of the present invention, the first FPGA card uses the storage resource according to the first resource table stored in the first register, and updates the first resource table; the first FPGA card sends the updated first resource table to a second FPGA card to instruct the second FPGA card to update a second resource table stored in a second register according to the updated first resource table; the method comprises the steps that a first FPGA card obtains an update message from a second FPGA card, wherein the update message carries a second resource table to be updated; the first FPGA card updates the first resource table according to the acquired second resource table to be updated; the first register is configured in a first FPGA card, the second register is configured in a second FPGA card, and the first resource table and the second resource table both comprise records of all storage resources in the server system. Through configuring the shared resource table, the FPGAs can be effectively communicated, the dynamic configuration of the storage resources of the whole system is realized, and the use efficiency of the storage resources is effectively improved.

Through the above description of the method embodiments, those skilled in the art can clearly understand that the present invention can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media that can store program codes, such as Read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and so on.

Corresponding to the embodiment of the storage resource control method provided by the invention, the invention also provides a storage resource control device.

Referring to fig. 8, which is a schematic structural diagram of a storage resource control apparatus according to an embodiment of the present invention, as shown in fig. 8, the apparatus includes:

the allocation module 11 is configured to use the storage resource according to the first resource table stored in the first register, and update the first resource table;

a sending module 12, configured to send the updated first resource table to the second FPGA card, so as to instruct the second FPGA card to update the second resource table stored in the second register according to the updated first resource table;

an obtaining module 13, configured to obtain an update message from a second FPGA card, where the update message carries a second resource table to be updated;

an updating module 14, configured to update the first resource table according to the obtained second resource table to be updated;

In a first implementation case, the allocating module 11 may be further configured to obtain a bandwidth request value of a program to be executed;

In a second implementation case, the allocation module 11 may be further configured to obtain a priority of the program to be run;

In addition, the sending module 12 may be further configured to send a first instruction to the second FPGA card before sending the updated first resource table to the second FPGA card, so as to instruct the second FPGA card to prohibit modification of the second resource table.

Alternatively, the sending module 12 may be further configured to obtain a priority of the second FPGA card

The embodiments of the present invention are similar to the above embodiments, and reference may be made to the description of the above embodiments, which are not repeated herein.

Embodiments of the present invention provide a non-volatile computer storage medium, where a computer-executable instruction is stored in the computer storage medium, and the computer-executable instruction may execute the storage resource control method in any of the above method embodiments.

An embodiment of the present invention further provides an electronic device, where the electronic device includes at least a first FPGA card and a second FPGA card, and the first FPGA card and the second FPGA card have the structures shown in fig. 3, and meanwhile, the resource control method described in the foregoing method embodiment may be executed, and have the same technical effects, and details are not described in the embodiment of the present invention.

Fig. 9 is a schematic diagram of a hardware structure of an electronic device executing a storage resource control method according to an embodiment of the present invention, and as shown in fig. 9, the electronic device includes:

one or more processors 910 and a memory 920, one processor 910 being illustrated in fig. 9.

The apparatus for performing the storage resource control method may further include: an input device 930 and an output device 940.

The processor 910, the memory 920, the input device 930, and the output device 940 may be connected by a bus or other means, and fig. 9 illustrates an example of a connection by a bus.

The memory 920 is used as a non-volatile computer-readable storage medium and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the storage resource control method in the embodiment of the present invention (for example, the allocating module 11, the sending module 12, the obtaining module 13, and the updating module 14 shown in fig. 8). The processor 910 executes various functional applications of the server and data processing by running nonvolatile software programs, instructions and modules stored in the memory 920, that is, implementing the storage resource control method of the above method embodiment.

The memory 920 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the storage resource control device, and the like. Further, the memory 920 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 920 may optionally include memory located remotely from processor 910, which may be connected to a storage resource control device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 930 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the storage resource control device. The output device 940 may include a display device such as a display screen.

The one or more modules are stored in the memory 920 and, when executed by the one or more processors 910, perform the storage resource control method in any of the method embodiments described above.

The product can execute the method provided by the embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method. For technical details that are not described in detail in this embodiment, reference may be made to the method provided by the embodiment of the present invention.

The electronic device of embodiments of the present invention exists in a variety of forms, including but not limited to:

(1) a mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.

(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.

(3) A portable entertainment device: such devices can display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.

(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.

(5) And other electronic devices with data interaction functions.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for apparatus or system embodiments, since they are substantially similar to method embodiments, they are described in relative terms, as long as they are described in partial descriptions of method embodiments. The above-described embodiments of the apparatus and system are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A storage resource control method, comprising the steps of:

2. The storage resource control method according to claim 1, wherein the first FPGA card uses the storage resource according to the first resource table stored in the first register, and includes:

3. The storage resource control method according to claim 1, wherein the first FPGA card uses the storage resource according to the first resource table stored in the first register, and includes:

the first FPGA card acquires the priority of a program to be run;

4. The storage resource control method according to claim 1, wherein before the first FPGA card sends the updated first resource table to the second FPGA card, the method further comprises:

5. The storage resource control method according to claim 4, further comprising:

the first FPGA card acquires the priority of the second FPGA card;

6. A storage resource control apparatus, comprising:

7. The storage resource control apparatus of claim 6, wherein the allocation module is configured to,

acquiring a bandwidth request value of a program to be operated;

8. The storage resource control apparatus of claim 6, wherein the allocation module is configured to,

acquiring the priority of a program to be run;

9. The storage resource control apparatus of claim 6, wherein the sending module is further configured to,

obtaining a priority of a second FPGA card

10. An electronic device, comprising a first FPGA card and a second FPGA card,