CN109541444B - Integrated circuit fault injection detection method based on mixed granularity parity check - Google Patents

Integrated circuit fault injection detection method based on mixed granularity parity check Download PDF

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CN109541444B
CN109541444B CN201811212551.9A CN201811212551A CN109541444B CN 109541444 B CN109541444 B CN 109541444B CN 201811212551 A CN201811212551 A CN 201811212551A CN 109541444 B CN109541444 B CN 109541444B
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刘强
王沛晶
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Tianjin University
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
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    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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Abstract

The invention relates to the technical field of integrated circuit safety detection, and aims to realize high fault detection rate and low resource occupation. Analyzing a circuit, wherein a fault injection sensitive part or a key part adopts fine-grained parity check, and other parts adopt coarse-grained parity check; and providing a fault detection rate and a resource calculation method, and evaluating the detection efficiency of different mixed particle size verification methods to obtain an optimal mixed particle size detection scheme. Therefore, the invention adopts the technical scheme that the integrated circuit fault injection detection method based on the mixed-granularity parity check adopts the parity check with different granularities for different parts of the circuit, specifically adopts the fine-granularity parity check for the data processed by the fault injection sensitive part or the key part in the circuit according to the fault injection attack characteristic, and adopts the coarse-granularity parity check for other parts. The invention is mainly applied to the integrated circuit safety detection occasions.

Description

Integrated circuit fault injection detection method based on mixed granularity parity check
Technical Field
The invention relates to the technical field of integrated circuit safety detection, in particular to an integrated circuit fault injection detection method based on mixed granularity parity check.
Background
In recent years, fault injection attacks have severely compromised integrated circuit security. The fault injection attack forces the circuit to leak key information by deliberately introducing faults into the circuit, and has strong attack capability, short required time and great harm. Common fault injection techniques are voltage fault injection, laser fault injection, electromagnetic fault injection, clock fault injection, and the like.
The fault injection attack resisting technology [1] can protect a circuit chip from malicious attack and ensure the safety of data inside the chip. Common fault injection attack resisting technologies include physical isolation, environmental monitoring, redundant computing and the like. Physical isolation and environmental monitoring detect specific fault injection attacks through package interference, metal layers, sensors and the like, and the application range is small. Redundancy calculation techniques, which use additional hardware or functionality to confirm whether a circuit has a fault, can be classified as spatial redundancy, temporal redundancy, and information redundancy.
Spatial redundancy detects whether a circuit fails through additional hardware, and resource consumption is large [2 ]. Temporal redundancy detects transient or periodic faults by repeatedly executing programs, with a high time cost [3 ]. The information redundancy adopts error detection coding, redundant information is added in data for fault detection, and the required space and time cost are low.
In conventional error detection coding, the parity code requires significantly less resources than the cyclic redundancy code [4 ]. However, the parity code has a drawback that even bit failures cannot be detected. Byte parity, while achieving higher failure detection rates than word parity, requires significantly higher resources than word parity [4, 5 ]. Therefore, it is necessary to find a fault injection detection method with high fault detection rate and low resource consumption.
Reference documents:
[1]BARENGHI A，BREVEGLIERI L，KOREN I，et al.Fault Injection Attacks on Cryptographic Devices:Theory，Practice，and Countermeasures[J].Proceedings of the IEEE，2012，100(11):3056-3076.
[2]BENEVENUTI F，KASTENSMIDT F L.Evaluation of fault attack detection on SRAM-based FPGAs[C]//Test Symposium.Bogota:IEEE，2017:1-6.
[3]MESTIRI H，BENHADJYOUSSEF N，MACHHOUT M，et al.A Robust Fault Detection Scheme for the Advanced Encryption Standard[J].International Journal of Computer Network&Information Security，2013，5(6):49-55.
[4]BERTONI G，BREVEGLIERI L，KOREN I，et al.Concurrent fault detection in a hardware implementation of the RC5encryption algorithm[J].Application-Specific Systems，Architectures，and Processors，2003,16(3):423-432.
[5]WEN Liang，JIANG Wei，JIANGKe，et al.Detecting Fault Injection Attacks on Embedded Real-Time Applications:A System-Level Perspective[C]//IEEE，International Conference on High PERFORMANCE Computing and Communications，2015IEEE，International Symposium on Cyberspace Safety and Security，and 2015IEEE，International Conf on Embedded Software and Systems.New York:IEEE Computer Society，2015:700-705。
disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an integrated circuit fault injection detection method based on mixed granularity parity check so as to realize high fault detection rate and low resource occupation. Analyzing a circuit, wherein a fault injection sensitive part or a key part adopts fine-grained parity check, and other parts adopt coarse-grained parity check; and providing a fault detection rate and a resource calculation method, and evaluating the detection efficiency of different mixed particle size verification methods to obtain an optimal mixed particle size detection scheme. Therefore, the invention adopts the technical scheme that the integrated circuit fault injection detection method based on the mixed-granularity parity check adopts the parity check with different granularities for different parts of the circuit, specifically adopts the fine-granularity parity check for the data processed by the fault injection sensitive part or the key part in the circuit according to the fault injection attack characteristic, and adopts the coarse-granularity parity check for other parts.
Further, the mixed-granularity parity check fault injection detection method comprises the following steps of detecting an original circuit by adopting a prediction circuit and a comparison circuit: the original circuit is a circuit to be detected, the prediction circuit calculates a theoretical value and an actual value of the parity of an output result, the comparison circuit is a comparator, and whether the theoretical value is the same as the actual value is judged; the prediction circuit predicts and obtains a theoretical value of the parity of the output result according to input data and a parity check principle, and calculates and obtains an actual value of the parity of the result through an output result of the original circuit; and obtaining a comparison result by the actual value and the theoretical value through the comparison circuit, if the actual value and the theoretical value are consistent, judging that the output of the original circuit is correct, and otherwise, the original circuit is injected with a fault.
Further, the fault detection rate of the mixed-granularity parity check fault injection detection method is as follows
Figure BDA0001832755370000021
In the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diIndicating the detection rate, beta, of other paths using different granularity paritiesiThe method represents the weight of the verification method in the mixed granularity verification technology, the method is defined according to the sensitivity of the circuit to faults, the value of i is determined by the original circuit, and the value of i is the number of other paths except the critical path in the original circuit.
Further, the resource consumption R of the mixed-granularity parity check fault injection detection method can be obtained by laying out and routing through an EDA tool.
Further, the detection efficiency η of the mixed-granularity parity check fault injection detection method is as follows
Figure BDA0001832755370000022
The hybrid method with the highest detection efficiency is the optimal method for detecting the mixed-granularity parity check fault.
The mixed granularity fault detection is realized by an RC5 encryption algorithm, pipeline operation is adopted, N groups of completely same circuit structures are utilized, an encryption module 0 initializes a plaintext, an encryption module 1- (N-1) executes encryption operation, a prediction circuit and a comparison circuit are added to each encryption module, and parity check methods with different granularities are adopted for different encryption modules according to the sensitivity degrees of the different encryption modules to faults, namely, the number of parity bits added in the prediction modules is different.
Specifically, by adopting an RC5 encryption algorithm, the selection parameter combination is: the word length is 32 bits, the key length is 16 bytes, and the number of encryption rounds is 12; by adopting clock fault injection attack, the specific design method of the prediction circuit is as follows: the RC5 encryption algorithm involves operation operations including addition, exclusive-OR and cyclic left shift, and a calculation method for obtaining the parity prediction values of the three operations according to mathematical reasoning:
parity p (A) of m-bit data A by XOR of its corresponding bit am-1、am-2…a0To obtain
Figure BDA0001832755370000031
The parity p (A + B) of the sum of two numbers is formed by XOR of the parity p (A), p (B) and carry input C of the two addendsinAnd all carry bits generated in addition
Figure BDA0001832755370000032
To obtain
Figure BDA0001832755370000033
Parity of two XOR
Figure BDA0001832755370000034
Derived from parity p (A), p (B) of these two numbers exclusive-OR
Figure BDA0001832755370000035
The parity p (A < < k) after one number cycle left shift of k bits does not change
p(A<<<k)＝p(A) (8)
The design of the prediction circuit in the RC5 encryption algorithm fault detection is obtained through the above description, the RC5 encryption algorithm is subjected to static time sequence analysis, the delay time of different paths is obtained according to a time sequence report, the clock fault injection is carried out in the time sequence simulation after layout and wiring, the parity check is expanded to be based on any bit, one parity bit is added to each 32, 16, 8 and 4 bits, different paths are added with different numbers of parity bits according to the path delay time, and the mixed-granularity parity check fault detection rate is as follows
Figure BDA0001832755370000036
In the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diThe detection rate of other paths adopting different granularity parity check is shown, and the actual value of the detection rate of the parity check fault of different granularity is dcAnd diThe ratio of the number of faults detected by the checking method to the total number of injected faults is obtained, betaiRepresents the weight of the checking method in the mixed granularity checking technology, and beta is used in the clock fault injectioniIs defined as follows
Figure BDA0001832755370000037
Wherein λ isiRepresenting the delays of the different paths.
The invention has the characteristics and beneficial effects that:
the invention solves the problems of low detection rate of word parity check faults and large consumption of byte parity check resources in the existing fault detection technology, provides a fault detection technology with high fault detection rate and low resource consumption, and realizes the compromise of the fault detection rate and the resources.
Description of the drawings:
fig. 1 is a structural diagram of a parity check fault injection detection method.
Fig. 2 is a block diagram of an implementation of RC5 encryption algorithm hybrid granularity fault detection.
FIG. 3 illustrates the efficiency of different mixed-granularity parity failure detection in the RC5 encryption algorithm.
Detailed Description
The invention aims to overcome the defects in the prior art and provides an integrated circuit fault injection detection method based on mixed granularity parity check to realize high fault detection rate and low resource occupation. Analyzing a circuit, wherein a fault injection sensitive part or a key part adopts fine-grained parity check, and other parts adopt coarse-grained parity check; and providing a fault detection rate and a resource calculation method, and evaluating the detection efficiency of different mixed particle size verification methods to obtain an optimal mixed particle size detection scheme.
The purpose of the invention is realized by the following technical scheme:
a fault injection detection method for an integrated circuit based on mixed granularity parity check is used for adopting different granularity parity check on different parts of the circuit. According to the characteristics of fault injection attack, fine-grained parity check is adopted for data processed by a fault injection sensitive part or a key part in a circuit, and coarse-grained parity check is adopted for other parts.
Furthermore, the mixed-granularity parity check fault injection detection method comprises an original circuit, a prediction circuit and a comparison circuit. The prediction circuit predicts and obtains a theoretical value of the parity of the output result according to input data and a parity check principle, and calculates and obtains an actual value of the parity of the result through an output result of the original circuit; and obtaining a comparison result by the actual value and the theoretical value through the comparison circuit, if the actual value and the theoretical value are consistent, judging that the output of the original circuit is correct, and otherwise, the original circuit is injected with a fault.
Further, the fault detection rate of the mixed-granularity parity check fault injection detection method is as follows
Figure BDA0001832755370000041
In the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diIndicating the detection rate of other paths using different granularity parity checks. Beta is aiThe weight of the checking method in the mixed granularity checking technology is expressed, and the checking method is defined according to the sensitivity of the circuit to the fault. The value of i is determined by the original circuit, and the value is the number of other paths in the original circuit except the critical path.
Further, the resource consumption R of the mixed-granularity parity check fault injection detection method can be obtained by laying out and routing through an EDA tool.
Further, the detection efficiency η of the mixed-granularity parity check fault injection detection method is as follows
Figure BDA0001832755370000042
The hybrid method with the highest detection efficiency is the optimal method for detecting the mixed-granularity parity check fault.
The present invention will be described in further detail with reference to specific examples.
As shown in fig. 1, the structure of the parity check integrated circuit fault injection detection method includes an original circuit, a prediction circuit and a comparison circuit. The prediction circuit obtains a theoretical value p (x) of the parity of the output result by predicting according to input data x and a parity check principle, and obtains an actual value y (x) of the parity of the result by calculating the output result of the original circuit; and the actual value y (x) and the theoretical value p (x) are compared by a comparison circuit to obtain a comparison result, if the actual value y (x) and the theoretical value p (x) are consistent, the output of the original circuit is considered to be correct, otherwise, the original circuit is failed to inject.
The parity check is mixed-granularity parity check which adopts different-granularity check methods for different parts of the circuit, fine-granularity parity check is adopted for data processed by fault injection sensitive parts or key parts in the circuit, and coarse-granularity parity check is adopted for other parts. Taking clock fault injection as an example, more parity bits are added to paths with larger delays and fewer parity bits are added to paths with smaller delays.
Taking RC5 encryption algorithm as an example, the parameter combination is selected as follows: the word length is 32 bits, the key length is 16 bytes, and the number of encryption rounds is 12. As shown in fig. 2, the RC5 encryption algorithm mixed granularity fault detection implementation structure adopts a pipeline operation, including 13 sets of identical circuit structures, an encryption module 0 initializes a plaintext, and encryption modules 1 to 12 execute encryption operations. A prediction circuit and a comparison circuit are added to each encryption module, and parity check methods with different granularities are adopted for the encryption modules according to the sensitivity degrees of the different encryption modules to faults, namely the number of parity bits added to the prediction modules is different. And analyzing the detection efficiency of different mixing methods by adopting clock fault injection attack. The design method of the prediction circuit is as follows. The RC5 encryption algorithm involves arithmetic operations including addition, exclusive or, and round-robin left-shifting. The calculation method of the parity prediction values of the three operations can be obtained according to mathematical reasoning.
Parity p (A) of m-bit data A by XOR of its corresponding bit am-1、am-2…a0To obtain
Figure BDA0001832755370000051
Parity p (A + B) of the sum of two numbers is determined by XORParity of the two addends p (A), p (B), carry-in CinAnd all carry bits generated in addition
Figure BDA0001832755370000052
To obtain
Figure BDA0001832755370000053
Parity of two XOR
Figure BDA0001832755370000054
Derived from parity p (A), p (B) of these two numbers exclusive-OR
Figure BDA0001832755370000055
The parity p (A < < k) after one number cycle left shift of k bits does not change
p(A<<<k)＝p(A) (8)
The design method of the prediction circuit in the fault detection of the RC5 encryption algorithm can be obtained from the above description. And performing static timing analysis on the RC5 encryption algorithm, and obtaining the delay time of different paths according to the timing report. The clock fault injection is performed in the timing simulation after the wiring is laid out. Expanding the parity check to be based on any bit, taking the example of adding one parity bit to each 32, 16, 8 and 4 bits, adding different numbers of parity bits to different paths according to the path delay time, wherein the fault detection rate of the mixed-granularity parity check is as follows because the critical path plays an important role in the fault detection rate
Figure BDA0001832755370000056
In the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diIndicating the detection rate of other paths using different granularity parity checks. Different granulesActual value of parity check failure detection rate (i.e., d)cAnd di) The fault detection method can be used for detecting the fault number of the injection fault in the injection fault detection system. Beta is aiRepresents the weight of the checking method in the mixed granularity checking technology, and beta is used in the clock fault injectioniIs defined as follows
Figure BDA0001832755370000057
Wherein λ isiRepresenting the delays of the different paths. In this example, the original circuit is an RC5 encryption algorithm, and its operation includes initializing plaintext and 12 rounds of encryption, each round of which operates on 2 data, respectively, except for the critical path, i takes a value of 0-24.
The resource consumption of the RC5 encryption algorithm mixed-granularity parity check method can be obtained after the wiring is laid out through Vivado. The detection efficiency obtained by selecting different mixing methods is shown in fig. 2, the design marked as 32 is to adopt 32-bit parity check in all circuit modules, and the design marked as 16-32 is to adopt 16-bit parity check in the module where the critical path is located and adopt 32-bit parity check in other modules. As can be seen from fig. 2, the 32-bit and 4-bit parities are less efficient in detection due to lower failure detection rate and more resource consumption, respectively. The modules are arranged according to the descending order of the path delay time, the parity check of 4 bits, 8 bits and 16 bits is adopted for the modules where the first 4 paths are located in sequence, and the detection efficiency of the other modules is highest by adopting a 32-bit check mixed parity check method, so that the method is the optimal method for mixed-granularity parity check.
The present invention is not limited to the above-described embodiments. The foregoing description of the specific embodiments is intended to describe and illustrate the technical solutions of the present invention, and the above specific embodiments are merely illustrative and not restrictive. Those skilled in the art can make many changes and modifications to the invention without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (4)

1. A fault injection detection method of an integrated circuit based on mixed-granularity parity check is characterized in that different-granularity parity check is adopted for different parts of a circuit to be detected, fine-granularity parity check is adopted for data processed by a fault injection sensitive path or a key path in the circuit to be detected, and coarse-granularity parity check is adopted for other parts according to the characteristics of fault injection attack; the integrated circuit fault injection detection method based on the mixed granularity parity check comprises the following steps of detecting an original circuit by adopting a prediction circuit and a comparison circuit: the original circuit is a circuit to be detected, the prediction circuit calculates a theoretical value and an actual value of the parity of the output result, the comparison circuit is a comparator and judges whether the theoretical value is the same as the actual value, and the prediction circuit predicts to obtain the theoretical value of the parity of the output result according to input data and a parity check principle; and calculating the actual value of the parity of the result through the output result of the original circuit; and obtaining a comparison result by the actual value and the theoretical value through the comparison circuit, if the actual value and the theoretical value are consistent, judging that the output of the original circuit is correct, and otherwise, the original circuit is injected with a fault.
2. The method of claim 1, wherein the integrated circuit fault injection detection method based on mixed-granularity parity check is further characterized in that the fault detection rate of the integrated circuit fault injection detection method based on mixed-granularity parity check is as follows:
Figure FDA0003258494850000011
in the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diIndicating the detection rate, beta, of other paths using different granularity paritiesiThe detection method is characterized in that the detection method represents the weight of the detection method in a mixed granularity verification technology, the detection method is defined according to the sensitivity of a circuit to faults, the value of i is determined by an original circuit, and the value of i is the number of other paths except for a key path in the original circuit.
3. The method of claim 2, further comprising the step of laying out and routing the resource consumption R of the mixed-granularity parity-check-based integrated circuit fault injection detection method through an EDA tool; further, the detection efficiency eta of the integrated circuit fault injection detection method based on the mixed granularity parity check is as follows
Figure FDA0003258494850000012
The detection method with the maximum detection efficiency is the optimal method for detecting the mixed granularity parity check fault.
4. The mixed-granularity parity-check-based integrated circuit fault injection detection method of claim 1, wherein an RC5 encryption algorithm is adopted, and the parameters are selected from the group consisting of: the word length is 32 bits, the key length is 16 bytes, the number of encryption rounds is 12 rounds, a clock fault injection attack is adopted, and the specific design method of the prediction circuit is as follows: the RC5 encryption algorithm involves operation operations including addition, exclusive-OR and cyclic left shift, and a calculation method for obtaining the parity prediction values of the three operations according to mathematical reasoning:
parity p (A) of m-bit data A is obtained by XOR-ing its corresponding bits am-1, am-2 … a0
Figure FDA0003258494850000013
The parity p (A + B) of the sum of two numbers is obtained by XOR-ing the parity p (A), p (B) of the two addends, the carry input Cin and all the carries generated in the addition
Figure FDA0003258494850000014
To obtain
Figure FDA0003258494850000015
Parity of two XOR
Figure FDA0003258494850000016
Derived from parity p (A), p (B) of these two numbers exclusive-OR
Figure FDA0003258494850000021
The parity p (A < < k) after one number cycle left shift of k bits does not change
p(A<<<k)＝p(A) (8)
After the design of a prediction circuit in the fault detection of the RC5 encryption algorithm is obtained, static time sequence analysis is carried out on the RC5 encryption algorithm, delay time of different paths is obtained according to a time sequence report, clock fault injection is carried out on the RC5 encryption algorithm in time sequence simulation after layout and wiring, parity check is expanded to be based on any bit, one parity bit is added to each 32 bit, 16 bit, 8 bit and 4 bit, different numbers of parity bits are added to different paths according to the path delay time, and the critical path plays an important role in the fault detection rate, so that the mixed-granularity parity check fault detection rate is as follows
Figure FDA0003258494850000022
In the formula: d represents the fault detection rate of the mixed granularity fault detection technology, DcFault detection rate for sensitive or critical paths of a circuit, diThe method is characterized in that the detection rate of other paths adopting different granularity parity check is shown, the actual value of the detection rate of the different granularity parity check fault, namely the ratio of the number of the faults detected by the detection method to the total number of the injected faults, namely dc and di, is obtained, and betaiRepresents the weight of the detection method in the mixed granularity verification technology, and beta is generated in the clock fault injectioniIs defined as follows
Figure FDA0003258494850000023
Wherein λ isiRepresenting the delays of the different paths.
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