CN109524401A - A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof - Google Patents
A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof Download PDFInfo
- Publication number
- CN109524401A CN109524401A CN201811167145.5A CN201811167145A CN109524401A CN 109524401 A CN109524401 A CN 109524401A CN 201811167145 A CN201811167145 A CN 201811167145A CN 109524401 A CN109524401 A CN 109524401A
- Authority
- CN
- China
- Prior art keywords
- drain electrode
- source electrode
- grid
- type
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 230000003068 static effect Effects 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 43
- 239000010408 film Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical compound [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 27
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 238000007519 figuring Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 229910052593 corundum Inorganic materials 0.000 claims description 7
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 7
- 238000001816 cooling Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000012467 final product Substances 0.000 claims description 3
- 238000001771 vacuum deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 2
- 239000005751 Copper oxide Substances 0.000 claims description 2
- 229910000431 copper oxide Inorganic materials 0.000 claims description 2
- NFFYXVOHHLQALV-UHFFFAOYSA-N copper(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Cu].[Cu] NFFYXVOHHLQALV-UHFFFAOYSA-N 0.000 claims description 2
- 229910003437 indium oxide Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 230000015654 memory Effects 0.000 abstract description 13
- 230000000295 complement effect Effects 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 238000011161 development Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000002041 carbon nanotube Substances 0.000 description 2
- 229910021393 carbon nanotube Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Thin Film Transistor (AREA)
Abstract
本发明涉及一种基于氧化物半导体的高性能静态随机读取存储器及其制备方法，由6个N型薄膜晶体管，或2个P型和4个N型薄膜晶体管组成；衬底为柔性衬底，N、P型薄膜晶体管的半导体层分别采用N型、P型金属氧化物材料。本发明的存储器的制作方法，包括：a).制备栅极；b).制备栅介质层；c).刻蚀互连线通孔；d).制备SnO半导体层；e).退火处理；f).制备IGZO半导体层；g).制备源、漏电极；h).退火处理。本发明通过N、P型场效应管来形成互补的存储器，具有很高且均衡的读写噪声容限和非常快的读写速度，可被广泛地用于诸如可穿戴设备的大规模柔性电路中，突破了现有SRAM性能低的限制。
The invention relates to a high-performance static random access memory based on oxide semiconductor and a preparation method thereof, which is composed of 6 N-type thin film transistors, or 2 P-type and 4 N-type thin film transistors; the substrate is a flexible substrate , The semiconductor layers of the N and P-type thin film transistors are respectively made of N-type and P-type metal oxide materials. The manufacturing method of the memory of the present invention includes: a) preparing a gate electrode; b) preparing a gate dielectric layer; c) etching interconnection line through holes; d). f). Preparation of IGZO semiconductor layer; g). Preparation of source and drain electrodes; h). Annealing treatment. The present invention forms a complementary memory through N and P type field effect transistors, has high and balanced read and write noise tolerance and very fast read and write speed, and can be widely used in large-scale flexible circuits such as wearable devices. It breaks through the limitation of low performance of the existing SRAM.
Description
Technical field
The present invention relates to a kind of Static Random Access Memory (SRAM), more specifically, more particularly to a kind of based on oxygen
High-performance Static Random Access Memory of compound semiconductor and preparation method thereof.
Background technique
Thin film technique has very big potentiality, is widely used in high yield, multi-functional, inexpensive and flexible integrated circuit
In；Oxide semiconductor due to high mobility, can it is transparent, can large area film forming and technological temperature low (such as can room temperature) it is all
More advantages, it is considered to be can be used for one of flexibility/transparent electron ideal material.For example, being based on indium gallium zinc oxygen (IGZO) film
The RFID tag and near-field communication technology of transistor (TFT) have certain development, still, these circuits work when
Data (extract operation) can only be read from read-only memory by waiting, and the write operation (depositing operation) without can be carried out data is serious to limit
Further development.In addition, there is some Static Random Access Memories (SRAM) based on flexible semiconductor to be reported
Road is such as based on organic semiconductor and carbon nano-tube material, and still, organic semiconductor is usually P-type material, lacks high-performance N-type
Organic semiconductor, and stability is not satisfactory, and purify and be mass produced carbon nanotube TFT and challenged there is also great.Cause
This, the SRAM performance for being currently based on flexible semiconductor is still low, cannot realize small area, strong noise tolerance and fast read-write speed simultaneously
Degree.With the development of flexible wearable equipment, Internet of Things etc., to can carry out writing and can the flexible memory development of read operation propose
Require, therefore, on a large scale can the development of flexible circuit to be badly in need of performance indexes excellent based on flexible semiconductor
SRAM。
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of high-performance static state random writes of based oxide semiconductor
Access to memory (SRAM)；
The present invention also provides the preparation methods of above-mentioned high-performance Static Random Access Memory.
The technical solution of the present invention is as follows:
A kind of high-performance Static Random Access Memory of based oxide semiconductor, including 6 thin film transistor (TFT)s, 6
Thin film transistor (TFT) is 6 N-type TFTs or 6 thin film transistor (TFT)s include that 2 P-type TFTs and 4 N-types are thin
Film transistor, the material of the active layer of the N-type TFT are N-type oxide semiconductor, the P-type TFT
The material of active layer is p-type oxide semiconductor.
Preferred according to the present invention, the N-type oxide semiconductor is indium gallium zinc oxygen IGZO, indium oxide In2O3Or zinc oxide
ZnO；The p-type oxide semiconductor includes stannous oxide SnO or copper oxide Cu2O3。
Preferred according to the present invention, 6 thin film transistor (TFT)s include 2 P-type TFTs and 4 N-type TFTs
When, the circuit connecting relation of 6 thin film transistor (TFT)s are as follows: 4 N-type TFTs of setting are respectively N1, N2, N3, N4,2 p-types
Thin film transistor (TFT) is respectively P1, P2, and the drain electrode of N1 is connect with the drain electrode of P1, and the source electrode of P1 and the source electrode of N1 are being separately connected power supply just
The drain electrode of pole and power cathode, N2 is connect with the drain electrode of P2, and the source electrode of P2 and the source electrode of N2 are separately connected positive pole and power supply
Cathode, the grid of N1 and the grid of P1 are connected to the junction of the drain electrode and the drain electrode of P1 of N1, and connect the source electrode of N4, the grid of N2
The grid of pole and P2 are connected to the junction of the drain electrode and the drain electrode of P2 of N2, and connect the source electrode of N3.
It is preferred according to the present invention, when 6 thin film transistor (TFT)s are 6 N-type TFTs, the electricity of 6 thin film transistor (TFT)s
Road connection relationship are as follows: 6 N-type TFTs of setting are respectively N1, N2, N3, N4, N5, N6, and the drain electrode of N1 connects with the drain electrode of N5
It connects, the source electrode of N5 and the source electrode of N1 are separately connected positive pole and power cathode, and the drain electrode of N2 is connect with the drain electrode of N6, the source of N6
The source electrode of pole and N2 are separately connected positive pole and power cathode, and the grid of N1 and the grid of N5 are connected to the drain electrode of N1 with N5's
The junction of drain electrode, and connect the source electrode of N4, the grid of N2 and the grid of N6 are connected to the connection of the drain electrode and the drain electrode of N6 of N2
Place, and connect the source electrode of N3.2 above-mentioned P-type TFTs be can be used as into the normally opened of pull-up resistor with 2 channel resistances
N-type TFT replaces.
It is preferred according to the present invention, the thin film transistor (TFT) by it is lower from it is upper successively include substrate, grid, gate dielectric layer, half
Conductor layer, source electrode and drain electrode, source electrode and drain electrode are grown on the semiconductor layer.
Preferred according to the present invention, the substrate is the flexible substrate or such as silicon-on-insulator, glass of such as polyimides
The rigid insulation substrate of glass, the grid, source electrode and drain electrode use the metal layer of single or double layer such as Ti, Au, Al, the grid
Dielectric layer is such as Al2O3、SiO2、HfO2、Ta2O5Insulation film.
The production method of the high-performance Static Random Access Memory of above-mentioned based oxide semiconductor, which is characterized in that
It is realized by following steps:
A, grid is prepared, the patterning process side of such as ultraviolet photolithographic, laser direct-writing, mask plate, electron beam exposure is used
Method defines the figure of grid on substrate, using such as electron beam evaporation, thermal evaporation technique for vacuum coating substrate surface according to
Secondary depositing Ti metal layer and Au metal layer, are removed, and grid is formed；
B, gate dielectric layer is prepared, one layer of aluminium oxide Al is deposited on the surface of grid using atom layer deposition process2O3Film,
Form gate dielectric layer；
C, etching interconnection line three-way hole, defines through-hole range with figuring technique, uses dry etching or wet etching
The aluminium oxide Al that will be exposed2O3Film etches away, and forms interconnection line three-way hole；
D, semiconductor layer is prepared, the figure of semiconductor layer is defined using photoetching process, is partly led using reaction magnetocontrol sputtering growth
Body thin film carries out strip operation, forms semiconductor layer；
E, it makes annealing treatment, device is heated to 200-250 DEG C, and kept for 1-3 hours, it is cooling；
It is further preferred that device is heated to 225 DEG C, and is kept for 2 hours by annealing in the step e.
F, source electrode, drain electrode are prepared, the figure of source electrode, drain electrode is defined using figuring technique, using electron beam evaporation
Deposited metal film；
G, it makes annealing treatment, device is heated to 80-170 DEG C, and kept for 0.5-2 hours, it is cooling；To obtain the final product.
It is further preferred that device is heated to 100 DEG C, and kept for 1 hour in the step g.
The interconnection of large-scale circuit may be implemented in the production of above-mentioned random-access memory.
Preferred according to the present invention, the step d prepares semiconductor layer, comprising: defines SnO semiconductor using photoetching process
The figure of layer grows SnO film using reaction magnetocontrol sputtering, carries out strip operation.
Preferred according to the present invention, the step d prepares semiconductor layer, comprising: define using figuring technique
The figure of IGZO semiconductor layer grows IGZO film using reaction magnetocontrol sputtering, carries out strip operation.
It is preferred according to the present invention, in the step a, Ti metal layer with a thickness of 3-10nm, the thickness of Au metal layer
10—50nm；
In the step b, aluminium oxide Al2O3The thickness of film is greater than 5nm；
In the step d, SnO film with a thickness of 10-25nm；IGZO film with a thickness of 10-50nm；
In the step f, source electrode is the Ti metal layer that thickness is greater than 10nm；Drain electrode is the Au metal that thickness is greater than 10nm
Layer.
It is further preferred that in the step a, Ti metal layer with a thickness of 5nm, the thickness 30nm of Au metal layer；
In the step b, aluminium oxide Al2O3Film with a thickness of 30nm；
In the step d, SnO film with a thickness of 20nm；IGZO film with a thickness of 24nm；
In the step f, source electrode is the Ti metal layer with a thickness of 50nm；Drain electrode is the Au metal layer with a thickness of 30nm.
The beneficial effects of the present invention are:
The high-performance Static Random Access Memory of based oxide semiconductor of the invention, being used as by using IGZO has
The n type field effect transistor and SnO that active layer is formed form complementary as the p type field effect transistor that active layer is formed
Memory, form can carry out write-in and read operation can flexible memory, also realized while with minimum area
Very high and balanced reading and noise margin and very fast read or write speed are write, area is minimum, only 0.0208mm2, read and
When it is very high and balanced to write noise margin, is 1.43V and 1.67V, while also achieving very fast writing rate, respectively one writing
121us and 82us when writing " 0 " so that the high-performance SRAM of this based oxide semiconductor can be widely used in such as
In the extensive flexible circuit of wearable device, Internet of Things etc., the read-write and processing of Lai Shixian data breach existing SRAM
The limitation of low, the flexible difficulty of energy, beneficial effect is significant, is suitable for the application of popularization.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of N-type IGZO thin film transistor (TFT) in Static Random Access Memory of the invention；
Fig. 2 is the structural schematic diagram of p-type SnO thin film transistor (TFT) in Static Random Access Memory of the invention；
Fig. 3 is the circuit diagram of the high-performance Static Random Access Memory of based oxide semiconductor of the invention；
Fig. 4 be based oxide semiconductor of the invention high-performance Static Random Access Memory under an optical microscope
Domain；
Fig. 5 is the performance diagram of N-type IGZO thin film transistor (TFT) in the present invention；
Fig. 6 is the performance diagram of p-type SnO thin film transistor (TFT) in the present invention；
Fig. 7 is the quiescent voltage transfer curve figure of high-performance SRAM of the invention when carrying out read operation；
Fig. 8 is the quiescent voltage transfer curve figure of high-performance SRAM of the invention when carrying out write operation；
Fig. 9 is the response wave shape figure of high-performance SRAM of the invention when whether enabling WL；
Figure 10 is the waveform diagram of the high-performance SRAM of the invention VR and VL in write-in " 0 " state；
Figure 11 is the waveform diagram of the high-performance SRAM of the invention VR and VL when one state is written.
1, substrate, 2, grid, 3, gate dielectric layer, 4, semiconductor layer, 5, source electrode, 6, drain electrode.
Specific embodiment
The invention will be further described with embodiment with reference to the accompanying drawings of the specification, but not limited to this.
Embodiment 1
A kind of high-performance Static Random Access Memory of based oxide semiconductor, including 6 thin film transistor (TFT)s, 6
Thin film transistor (TFT) is 6 N-type TFTs or 6 thin film transistor (TFT)s include that 2 P-type TFTs and 4 N-types are thin
Film transistor, the material of the active layer of N-type TFT are N-type oxide semiconductor, the active layer of P-type TFT
Material is p-type oxide semiconductor.The performance of current existing p-type oxide semiconductor is still low, is mainly reflected in mobility, electric current
On-off ratio and subthreshold swing, so there is no the complementary SRAM based on N-type and p-type oxide semiconductor at present.In this patent
SnO TFT high-performance is obtained by specific experimental technique.
When 6 thin film transistor (TFT)s include 2 P-type TFTs and 4 N-type TFTs, 6 thin film transistor (TFT)s
Circuit connecting relation are as follows: 4 N-type TFTs of setting are respectively N1, N2, N3, N4, and 2 P-type TFTs are respectively
The drain electrode of P1, P2, N1 are connect with the drain electrode of P1, and the source electrode of P1 and the source electrode of N1 are separately connected positive pole and power cathode, N2
Drain electrode connect with the drain electrode of P2, the source electrode of P2 and the source electrode of N2 are separately connected positive pole and power cathode, the grid of N1 and
The grid of P1 is connected to the junction of the drain electrode and the drain electrode of P1 of N1, and connects the source electrode of N4, and the grid of N2 and the grid of P2 are equal
It is connected to the junction of the drain electrode and the drain electrode of P2 of N2, and connects the source electrode of N3.
When 6 thin film transistor (TFT)s are 6 N-type TFTs, the circuit connecting relation of 6 thin film transistor (TFT)s are as follows: setting 6
A N-type TFT is respectively N1, N2, N3, N4, N5, N6, and the drain electrode of N1 is connect with the drain electrode of N5, the source electrode of N5 and N1's
Source electrode is separately connected positive pole and power cathode, and the drain electrode of N2 is connect with the drain electrode of N6, and the source electrode of N6 and the source electrode of N2 are distinguished
Positive pole and power cathode are connected, the grid of N1 and the grid of N5 are connected to the junction of the drain electrode and the drain electrode of N5 of N1, and
The source electrode of N4 is connected, the grid of N2 and the grid of N6 are connected to the junction of the drain electrode and the drain electrode of N6 of N2, and connect the source of N3
Pole.2 above-mentioned P-type TFTs can be used as to the normally opened N-type TFT generation of pull-up resistor with 2 channel resistances
It replaces.
Thin film transistor (TFT) by it is lower from it is upper successively include substrate 1, grid 2, gate dielectric layer 3, semiconductor layer 4, source electrode 5 and drain electrode
6, source electrode 5 and drain electrode 6 are grown on semiconductor layer 4.
Substrate 1 is the flexible substrate of such as polyimides or the rigid insulation substrate of such as silicon-on-insulator, glass, grid
2, using the metal layer of single or double layer such as Ti, Au, Al, gate dielectric layer 3 is such as Al for source electrode 5 and drain electrode 62O3、SiO2、
HfO2、Ta2O5Insulation film.
Embodiment 2
According to a kind of high-performance Static Random Access Memory of based oxide semiconductor described in embodiment 1, area
It is not, N-type oxide semiconductor is indium gallium zinc oxygen IGZO, forms N-type IGZO thin film transistor (TFT), and p-type oxide semiconductor is
Stannous oxide SnO forms p-type SnO thin film transistor (TFT).The structural schematic diagram of N-type IGZO thin film transistor (TFT) is as shown in Figure 1, p-type
The structural schematic diagram of SnO thin film transistor (TFT) is as shown in Figure 2.
Grid 2 is made of Ti metal layer and Au metal layer, and Ti metal layer is contacted with substrate 1, and Au metal layer is set to Ti gold
Belong on layer；Gate dielectric layer 3 uses aluminium oxide Al2O3Film, source electrode 5 and drain electrode 6 individually using Ti metal or can use Ti and Au
Alloy.
As shown in Figure 3 and Figure 4, the high-performance static state random write that the present embodiment based oxide semiconductor is set forth takes
The circuit diagram of memory and domain under an optical microscope, shown in Static Random Access Memory by 4 N-type film crystals
Manage (being respectively labeled as N1, N2, N3 and N4) and 2 P-type TFTs (being respectively labeled as P1, P2) composition, the drain electrode of N1 and
The drain electrode of P1 is connected, and the drain electrode of N2 is connected with the drain electrode of P2, and two ends after being connected are connected to power supply just and in power ground,
Material is thus formed complementary structures.2 P-type TFTs P1, P2 can also with the very big N-type TFT of channel resistance come
Instead of.The grid of N1 and P1 is connected with the source electrode of the junction of N2 and P2 and N4, the grid of N2 and P2 and the company of N1 and P1
The place of connecing is connected with the source electrode of N3, and the grid of N3 and N4 form (enabled) the end WL of Read-write Catrol, and the drain electrode of N3 forms memory
Right side read and write end BR, the drain electrode of N4 formed memory left side read and write end BL.The junction of N1 and P1 is denoted as VR's, N2 and P2
Junction is denoted as VL.
Embodiment 3
The production method of the high-performance Static Random Access Memory of based oxide semiconductor described in embodiment 1 or 2,
It is characterized in that, being realized by following steps:
A, grid 2 is prepared, the patterning process side of such as ultraviolet photolithographic, laser direct-writing, mask plate, electron beam exposure is used
Method defines the figure of grid 2 on substrate 1, using the technique for vacuum coating of such as electron beam evaporation, thermal evaporation on 1 surface of substrate
It is sequentially depositing Ti metal layer and Au metal layer, is removed, grid 2 is formed；
B, gate dielectric layer 3 is prepared, one layer of aluminium oxide Al is deposited on the surface of grid 2 using atom layer deposition process2O3It is thin
Film forms gate dielectric layer 3；
C, etching interconnection line three-way hole, defines through-hole range with figuring technique, uses dry etching or wet etching
The aluminium oxide Al that will be exposed2O3Film etches away, and forms interconnection line three-way hole；
D, semiconductor layer 4 is prepared, the figure of semiconductor layer 4 is defined using photoetching process, using reaction magnetocontrol sputtering growth half
Conductor thin film carries out strip operation, forms semiconductor layer 4；
E, it makes annealing treatment, device is heated to 225 DEG C, and kept for 2 hours, it is cooling；
F, source electrode 5, drain electrode 6 are prepared, the figure of source electrode 5, drain electrode 6 is defined using figuring technique, using electron beam
Hydatogenesis metallic film；
G, it makes annealing treatment, device is heated to 100 DEG C, and kept for 1 hour, it is cooling；To obtain the final product.
The interconnection of large-scale circuit may be implemented in the production of above-mentioned random-access memory.
Step d prepares semiconductor layer 4, comprising: the figure that SnO semiconductor layer is defined using photoetching process, using reaction magnetic control
Sputtering growth SnO film, carries out strip operation.
Step d prepares semiconductor layer 4, comprising: the figure that IGZO semiconductor layer is defined using figuring technique is adopted
IGZO film is grown with reaction magnetocontrol sputtering, carries out strip operation.
In step a, Ti metal layer with a thickness of 5nm, the thickness 30nm of Au metal layer；In step b, aluminium oxide Al2O3Film
With a thickness of 30nm；In step d, SnO film with a thickness of 20nm；IGZO film with a thickness of 24nm；In step f, source electrode 5 is
With a thickness of the Ti metal layer of 50nm；Drain electrode 6 is the Au metal layer with a thickness of 30nm.
As shown in Figure 5 and Figure 6, N-type IGZO thin film transistor (TFT) and p-type SnO thin film transistor (TFT) in the present invention is set forth
Performance diagram, voltage of the abscissa between grid 2 and source electrode 5, ordinate be drain 6 and source electrode 5 between electric current,
The width of IGZO thin film transistor (TFT) and the ratio W/L=2 of length, the ordinate in the corresponding left side of solid line in figure, dotted line are corresponding right
The ordinate of side.The mobility of N-type IGZO thin film transistor (TFT) shown in Fig. 5 is 10.3cm2V-1s-1, on-off ratio is 6 × 106,
Subthreshold swing is 0.8V/dec, threshold voltage 3.1V.The mobility of p-type SnO thin film transistor (TFT) shown in Fig. 6 is
1.1cm2V-1s-1, on-off ratio is 2.6 × 104, subthreshold swing 1.3V/dec, threshold voltage is -2.8V.As it can be seen that N-type IGZO
Thin film transistor (TFT) and p-type SnO thin film transistor (TFT) it is functional.
As shown in fig. 7, it is bent to give the quiescent voltage transmission characteristic of high-performance SRAM of the invention when carrying out read operation
Line chart, Fig. 8 give the quiescent voltage transfer curve figure of high-performance SRAM of the invention when carrying out write operation, abscissa
For the voltage of the VR point in Fig. 3, ordinate is the voltage of the VL point in Fig. 3.Square side length is read noise tolerance in Fig. 7
(RSNM), it is equal to 1.43V；Square side length is to write noise margin in Fig. 8, is equal to 1.67V.The case where supply voltage is 8V
Under, such read-write noise margin values are sufficiently high, and the two values are not much different relative equilibrium.
Fig. 9 to Figure 11 successively give SRAM of the invention whether enabled WL when response wave shape figure, write-in " 0 " and
The waveform diagram of VR and VL when one state, abscissa are the time, and ordinate is voltage.Fig. 9 can be seen that when WL=" 1 "
When, the waveform that BR point applies can be for transmission to VR point, and when " 0 " WL=, and the waveform that BR point applies is not delivered to VR point.Figure 10
The voltage relationship for showing VR point and VL point with Figure 11, according to the timing definition of rising edge and failing edge, it can be deduced that very
The short time for writing " 0 " and " 1 ", respectively 82 and 121 μ s.
Claims (10)
1. a kind of high-performance Static Random Access Memory of based oxide semiconductor, which is characterized in that including 6 film crystalline substances
Body pipe, 6 thin film transistor (TFT)s are 6 N-type TFTs or 6 thin film transistor (TFT)s include 2 P-type TFTs and 4
A N-type TFT, the material of the active layer of the N-type TFT are N-type oxide semiconductor, the p-type film
The material of the active layer of transistor is p-type oxide semiconductor.
2. a kind of high-performance Static Random Access Memory of based oxide semiconductor according to claim 1, special
Sign is that the N-type oxide semiconductor is indium gallium zinc oxygen IGZO, indium oxide In2O3Or zinc oxide ZnO；The p-type oxide
Semiconductor includes stannous oxide SnO or copper oxide Cu2O3。
3. a kind of high-performance Static Random Access Memory of based oxide semiconductor according to claim 1, special
Sign is, when 6 thin film transistor (TFT)s include 2 P-type TFTs and 4 N-type TFTs, 6 thin film transistor (TFT)s
Circuit connecting relation are as follows: 4 N-type TFTs of setting are respectively N1, N2, N3, N4, and 2 P-type TFTs are respectively
The drain electrode of P1, P2, N1 are connect with the drain electrode of P1, and the source electrode of P1 and the source electrode of N1 are separately connected positive pole and power cathode, N2
Drain electrode connect with the drain electrode of P2, the source electrode of P2 and the source electrode of N2 are separately connected positive pole and power cathode, the grid of N1 and
The grid of P1 is connected to the junction of the drain electrode and the drain electrode of P1 of N1, and connects the source electrode of N4, and the grid of N2 and the grid of P2 are equal
It is connected to the junction of the drain electrode and the drain electrode of P2 of N2, and connects the source electrode of N3.
4. a kind of high-performance Static Random Access Memory of based oxide semiconductor according to claim 3, special
Sign is, when 6 thin film transistor (TFT)s are 6 N-type TFTs, the circuit connecting relation of 6 thin film transistor (TFT)s are as follows: setting 6
A N-type TFT is respectively N1, N2, N3, N4, N5, N6, and the drain electrode of N1 is connect with the drain electrode of N5, the source electrode of N5 and N1's
Source electrode is separately connected positive pole and power cathode, and the drain electrode of N2 is connect with the drain electrode of N6, and the source electrode of N6 and the source electrode of N2 are distinguished
Positive pole and power cathode are connected, the grid of N1 and the grid of N5 are connected to the junction of the drain electrode and the drain electrode of N5 of N1, and
The source electrode of N4 is connected, the grid of N2 and the grid of N6 are connected to the junction of the drain electrode and the drain electrode of N6 of N2, and connect the source of N3
Pole.
5. a kind of high-performance Static Random Access Memory of based oxide semiconductor according to claim 1, special
Sign is, the thin film transistor (TFT) by it is lower from it is upper successively include substrate, grid, gate dielectric layer, semiconductor layer, source electrode and drain electrode,
Source electrode and drain electrode is grown on the semiconductor layer.
6. a kind of high-performance Static Random Access Memory of based oxide semiconductor according to claim 5, special
Sign is that the substrate is flexible substrate or rigid insulation substrate, and the grid, source electrode and drain electrode are using single or double layer
Metal layer, the gate dielectric layer are insulation film.
7. the production method of the high-performance Static Random Access Memory of based oxide semiconductor described in claim 5 or 6,
It is characterized in that, being realized by following steps:
A, grid is prepared, defines the figure of grid on substrate using figuring technique, is being served as a contrast using technique for vacuum coating
Bottom surface is sequentially depositing Ti metal layer and Au metal layer, is removed, and grid is formed；
B, gate dielectric layer is prepared, one layer of aluminium oxide Al is deposited on the surface of grid using atom layer deposition process2O3Film is formed
Gate dielectric layer；
C, etching interconnection line three-way hole, defines through-hole range with figuring technique, will be sudden and violent using dry etching or wet etching
The aluminium oxide Al exposed2O3Film etches away, and forms interconnection line three-way hole；
D, semiconductor layer is prepared, the figure of semiconductor layer is defined using photoetching process, semiconductor film is grown using reaction magnetocontrol sputtering
Film carries out strip operation, forms semiconductor layer；
E, it makes annealing treatment, device is heated to 200-250 DEG C, and kept for 1-3 hours, it is cooling；
It is further preferred that device is heated to 225 DEG C, and is kept for 2 hours by annealing in the step e；
F, source electrode, drain electrode are prepared, the figure of source electrode, drain electrode is defined using figuring technique, is deposited using electron beam evaporation
Metallic film；
G, it makes annealing treatment, device is heated to 80-170 DEG C, and kept for 0.5-2 hours, it is cooling；To obtain the final product；
It is further preferred that device is heated to 100 DEG C, and kept for 1 hour in the step g.
8. the production side of the high-performance Static Random Access Memory of based oxide semiconductor according to claim 7
Method, which is characterized in that the step d prepares semiconductor layer, comprising: the figure that SnO semiconductor layer is defined using photoetching process is adopted
SnO film is grown with reaction magnetocontrol sputtering, carries out strip operation.
9. the production side of the high-performance Static Random Access Memory of based oxide semiconductor according to claim 7
Method, which is characterized in that the step d prepares semiconductor layer, comprising: define IGZO semiconductor layer using figuring technique
Figure, using reaction magnetocontrol sputtering grow IGZO film, carry out strip operation.
10. according to the high-performance Static Random Access Memory of any based oxide semiconductor of claim 7-9
Production method, which is characterized in that in the step a, Ti metal layer with a thickness of 3-10nm, the thickness 10-of Au metal layer
50nm；In the step b, aluminium oxide Al2O3The thickness of film is greater than 5nm；In the step d, SnO film with a thickness of 10-
25nm；IGZO film with a thickness of 10-50nm；In the step f, source electrode is the Ti metal layer that thickness is greater than 10nm；Drain electrode is
Thickness is greater than the Au metal layer of 10nm；
It is further preferred that in the step a, Ti metal layer with a thickness of 5nm, the thickness 30nm of Au metal layer；The step b
In, aluminium oxide Al2O3Film with a thickness of 30nm；In the step d, SnO film with a thickness of 20nm；The thickness of IGZO film
For 24nm；In the step f, source electrode is the Ti metal layer with a thickness of 50nm；Drain electrode is the Au metal layer with a thickness of 30nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811167145.5A CN109524401A (en) | 2018-10-08 | 2018-10-08 | A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811167145.5A CN109524401A (en) | 2018-10-08 | 2018-10-08 | A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109524401A true CN109524401A (en) | 2019-03-26 |
Family
ID=65772599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811167145.5A Pending CN109524401A (en) | 2018-10-08 | 2018-10-08 | A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109524401A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086519A (en) * | 2019-06-13 | 2020-12-15 | 山东大学 | A hydrogen ion concentration sensor chip based on bipolar SnO and its preparation method and application |
| CN114361253A (en) * | 2021-12-29 | 2022-04-15 | 东南大学 | Oxide semiconductor bipolar transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120175609A1 (en) * | 2011-01-12 | 2012-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN102694006A (en) * | 2011-03-25 | 2012-09-26 | 株式会社半导体能源研究所 | Semiconductor device and method of manufacturing semiconductor device |
| CN102891182A (en) * | 2011-07-22 | 2013-01-23 | 株式会社半导体能源研究所 | Semiconductor device |
| CN107170812A (en) * | 2017-06-08 | 2017-09-15 | 湘潭大学 | A kind of ferroelectrical thin film transistor and preparation method thereof |
-
2018
- 2018-10-08 CN CN201811167145.5A patent/CN109524401A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120175609A1 (en) * | 2011-01-12 | 2012-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN102694006A (en) * | 2011-03-25 | 2012-09-26 | 株式会社半导体能源研究所 | Semiconductor device and method of manufacturing semiconductor device |
| CN102891182A (en) * | 2011-07-22 | 2013-01-23 | 株式会社半导体能源研究所 | Semiconductor device |
| CN107170812A (en) * | 2017-06-08 | 2017-09-15 | 湘潭大学 | A kind of ferroelectrical thin film transistor and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| H. SUNAMURA 等: "Enhanced Drivability of High-Vbd Dual-oxide-based Complementary BEOL-FETs for Compact On-chip Pre-driver Applications", 《2014 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TECHNOLOGY): DIGEST OF TECHNICAL PAPERS》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086519A (en) * | 2019-06-13 | 2020-12-15 | 山东大学 | A hydrogen ion concentration sensor chip based on bipolar SnO and its preparation method and application |
| CN112086519B (en) * | 2019-06-13 | 2021-10-26 | 山东大学 | Hydrogen ion concentration sensor chip and preparation method and application thereof |
| CN114361253A (en) * | 2021-12-29 | 2022-04-15 | 东南大学 | Oxide semiconductor bipolar transistor and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107482014B (en) | A kind of multi-level unit thin-film transistor memory and preparation method thereof | |
| CN110943128B (en) | Two-dimensional MOSFET/MFIS multifunctional switching memory device and preparation method thereof | |
| CN103413833B (en) | A kind of flexible zno-based thin-film transistor and preparation method thereof | |
| CN103346089B (en) | A kind of autoregistration bilayer channel metal-oxide thin film transistor (TFT) and preparation method thereof | |
| CN102623459B (en) | Thin-film transistor memory and preparation method thereof | |
| KR101712003B1 (en) | 2-Dimensional laminated composite structured bistable non-volatile memory device and methods of manufacturing the same | |
| US7381586B2 (en) | Methods for manufacturing thin film transistors that include selectively forming an active channel layer from a solution | |
| Jang et al. | Endurance characteristics of amorphous-InGaZnO transparent flash memory with gold nanocrystal storage layer | |
| CN109524401A (en) | A kind of high-performance Static Random Access Memory of based oxide semiconductor and preparation method thereof | |
| CN112968055A (en) | Two-dimensional ferroelectric semiconductor channel ferroelectric dielectric layer field effect transistor and preparation method thereof | |
| CN109801975A (en) | Flexible thin-film transistor and its manufacturing method based on amorphous indium gallium zinc film | |
| CN108365092A (en) | A kind of high temperature resistant memristor based on two-dimensional atomic crystal | |
| CN104465400A (en) | Preparation and in-situ characterization method of residue-free optical photoresist graphene FET | |
| CN109148594B (en) | Near-room-temperature preparation process and application of high-performance thin film transistor | |
| CN102110777A (en) | Organic floating gate field effect transistor and preparation method thereof | |
| CN115207127A (en) | Multi-electric-conduction-state ferroelectric transistor device based on interlayer slippage and preparation method | |
| Dai et al. | Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint | |
| CN113921599A (en) | Flexible programmable memory, preparation method thereof, phase inverter thereof and logic gate circuit | |
| CN107403832A (en) | A kind of high performance thin film transistor and application thereof | |
| CN112447858A (en) | Junction field effect transistor and preparation method thereof | |
| CN101431330A (en) | NOR gate logic circuit and its forming method | |
| CN113921706B (en) | Two-dimensional tellurite-alkene nanowire-based field effect memristor and manufacturing method thereof | |
| CN113380896B (en) | Preparation method of thin film transistor, thin film transistor and display panel | |
| CN113823697A (en) | Schottky gate field effect transistor based on two-dimensional size tailoring and preparation method thereof | |
| CN112436058A (en) | Flexible InGaZnO thin film transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190326 |
|
| RJ01 | Rejection of invention patent application after publication |