CN109524395B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN109524395B
CN109524395B CN201710844807.7A CN201710844807A CN109524395B CN 109524395 B CN109524395 B CN 109524395B CN 201710844807 A CN201710844807 A CN 201710844807A CN 109524395 B CN109524395 B CN 109524395B
Authority
CN
China
Prior art keywords
well
region
doped region
semiconductor substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710844807.7A
Other languages
Chinese (zh)
Other versions
CN109524395A (en
Inventor
邱建维
林鑫成
胡钰豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vanguard International Semiconductor Corp
Original Assignee
Vanguard International Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard International Semiconductor Corp filed Critical Vanguard International Semiconductor Corp
Priority to CN201710844807.7A priority Critical patent/CN109524395B/en
Publication of CN109524395A publication Critical patent/CN109524395A/en
Application granted granted Critical
Publication of CN109524395B publication Critical patent/CN109524395B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor substrate with a first conduction type, wherein the semiconductor substrate comprises a first area and a second area, a buried layer is arranged in the first area of the semiconductor substrate and has the first conduction type, the dopant concentration of the buried layer is higher than that of the semiconductor substrate, an epitaxial layer is arranged on the semiconductor substrate, a first element is arranged on the first area of the semiconductor substrate, the first element comprises a bipolar junction-complementary metal oxide semiconductor-double diffusion metal oxide semiconductor transistor, and a second element is arranged on the second area of the semiconductor substrate, wherein the second element comprises an ultrahigh voltage transistor. The invention can effectively prevent the BCD transistor arranged in the first area of the semiconductor substrate from generating latch-up effect, thereby avoiding the BCD transistor from being burnt out due to short circuit.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which different types of elements are integrated together and a method for manufacturing the same.
Background
Bipolar-Complementary metal oxide semiconductor-Double diffused metal oxide semiconductor (CMOS) -BCD (hereinafter referred to as BCD) is a System-on-a-Chip (SoC) process that can form smart power integrated circuits (smart power integrated circuits) that can fabricate Bipolar transistors, Complementary metal oxide semiconductor transistors (CMOS) and Double diffused metal oxide semiconductor transistors (DMOS) on the same Chip.
BCD processes can effectively integrate power chips, have the advantages of greatly saving packaging cost, reducing power consumption, improving system performance, and the like, and are also increasingly used for manufacturing semiconductor devices as electronic products are increasingly becoming more dense and miniaturized.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for forming the same, and more particularly, embodiments of a BCD transistor and an ultra-high voltage (UHV) transistor integrated into the same semiconductor device.
Embodiments of the present invention divide a semiconductor substrate into a first region in which a first element comprising BCD transistors is disposed and a second region in which a second element comprising UHV transistors is disposed. Forming a patterned mask covering the second region before performing an epitaxial process, and performing a doping process on the first region by using the patterned mask to form a buried layer in the first region, wherein the buried layer has the same conductivity type as the semiconductor substrate and has a dopant concentration higher than that of the semiconductor substrate, so that latch-up effect of the BCD transistor in the first region of the semiconductor substrate can be effectively prevented, and the BCD transistor can be prevented from being burnt due to short circuit.
In addition, the patterned mask can prevent the formation of a buried layer with the same dopant concentration as the first region (i.e., the region where the BCD transistor is disposed) in the second region of the semiconductor substrate, thereby preventing the UHV transistor from failing and effectively maintaining the breakdown voltage (breakdown voltage) of the UHV transistor. The buried layer is not extended to the second region of the semiconductor substrate, so that the BCD transistor and the UHV transistor can be smoothly integrated in the same semiconductor device, and the effects of avoiding latch-up and improving breakdown voltage are achieved at the same time.
According to some embodiments, a semiconductor device is provided. The semiconductor device is included in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the semiconductor substrate, and an epitaxial layer disposed on the semiconductor substrate. The semiconductor device further includes a first device disposed on the first region of the semiconductor substrate, wherein the first device includes a bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor transistor, and a second device disposed on the second region of the semiconductor substrate, wherein the second device includes an ultra high voltage transistor.
According to some embodiments, a method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes providing a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region, and forming a patterned mask on the second region of the semiconductor substrate. The method also includes performing a doping process on the semiconductor substrate through the patterned mask to form a buried layer in the first region, wherein the buried layer has the first conductivity type and a dopant concentration of the buried layer is higher than a dopant concentration of the semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate. The method further includes forming a first device on the first region of the semiconductor substrate, wherein the first device comprises a bipolar-cmos-ldmos transistor, and forming a second device on the second region of the semiconductor substrate, wherein the second device comprises an uhp transistor.
Drawings
The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.
Fig. 1-6 are cross-sectional views illustrating various stages in a method of forming a semiconductor device, in accordance with some embodiments of the present invention.
Reference numerals
100 to a semiconductor device;
101-a semiconductor substrate;
102 to a first zone;
103-patterned mask;
104 to a second zone;
105-doping process;
107-embedding layer;
109-epitaxial layer;
111-a first isolation structure;
113-a second isolation structure;
115 to a first well;
117 to the second well;
119 to a third trap;
121 to a fourth well;
123-first doping area;
125 to the second doping area;
127 to a third doped region;
129 to a fourth doped region;
131 to a fifth doped region;
133 to a sixth doped region;
135 to a first gate dielectric layer;
136-a first gate structure;
137 to a first gate electrode layer;
139 a second gate dielectric layer;
140 to a second gate structure;
141 to a second gate electrode layer;
143 to an interlayer dielectric layer;
145 to a first source electrode;
145a, 145b, 147a, 149b, 151a to guide holes;
147 to a first drain electrode;
149 to a second source electrode;
151 to a second drain electrode;
200-a first element;
300 to a second element;
d-distance;
l1-first length;
l2 to a second length.
Detailed Description
The following provides many different embodiments or examples for implementing the provided semiconductor devices having different components. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.
Fig. 1-6 are cross-sectional views illustrating various stages in a method for forming the semiconductor device 100 shown in fig. 6, wherein the semiconductor device 100 includes a first element 200 and a second element 300, in accordance with some embodiments of the present invention.
According to some embodiments, as shown in fig. 1, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 includes a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 101 has the first conductivity type, for example, the semiconductor substrate 101 of the present embodiment is a lightly doped P-type substrate, while in other embodiments, the semiconductor substrate 101 may be a lightly doped N-type substrate.
Continuing on the foregoing, as shown in fig. 1, the semiconductor substrate 101 is divided into a first region 102 and a second region 104, the first region 102 being a region where a BCD transistor (see fig. 6) of the first element 200 will be formed later, and the second region 104 being a region where a UHV transistor (see fig. 6) of the second element 300 will be formed later. The positions of the first region 102 and the second region 104 can be arbitrarily adjusted according to the configuration requirements of the semiconductor device. In some embodiments, the first region 102 is adjacent to the second region 104. In other embodiments, the first region 102 and the second region 104 may be separated by other regions.
According to some embodiments, as shown in fig. 2, a patterned mask 103 is formed on the second region 104 of the semiconductor substrate 101. In some embodiments, a mask layer (not shown) is formed on the semiconductor substrate 101, and then a patterning process is performed to pattern the mask layer to form the patterned mask 103. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and baking (e.g., hard baking). The etching process includes dry etching or wet etching.
In some embodiments, the patterned mask 103 completely covers the second region 104 of the semiconductor substrate 101 and extends to the first region 102 to cover a portion of the first region 102 of the semiconductor substrate 101. In other words, the patterned mask 103 exposes a portion of the first region 102 of the semiconductor substrate 101.
Next, a doping process 105 is performed to form a buried layer 107 in the first region 102 of the semiconductor substrate 101 using the patterned mask 103, the buried layer 107 having the same first conductivity type as the semiconductor substrate 101. In some embodiments, the doping process 105 includes an ion implantation (ion implantation) process, which may implant a P-type dopant, such As boron (B), into the first region 102 of the P-type semiconductor substrate 101, or implant an N-type dopant, such As phosphorus (P) or arsenic (As), into the N-type semiconductor substrate 101. After the doping process 105 is performed, the buried layer 107 has the same conductivity type as the semiconductor substrate 101, and the dopant concentration of the buried layer 107 is higher than that of the semiconductor substrate 101.
In the present embodiment, the buried layer 107 and the semiconductor substrate 101 are both P-type, and the dopant concentration of the buried layer 107 is about 1x1015Atom/cubic centimeter (atom/cm)3) To about 1x1018Atom/cubic centimeter (atom/cm)3) And the dopant concentration of the semiconductor substrate 101 is about 1x1014Atom/cubic centimeter (atom/cm)3) To about 1x1016Atom/cubic centimeter (atom/cm)3) Within the range of (1).
It is noted that in some embodiments, the patterned mask 103 extends to the first region 102 of the semiconductor substrate 101, such that the buried layer 107 formed by the patterned mask 103 is completely located in the first region 102, i.e., the extent of the buried layer 107 is less than or equal to the extent of the first region 102 (the dopants in the buried layer 107 may be out-diffused such that the extent of the buried layer 107 is equal to the extent of the first region 102). As shown in fig. 2, in some embodiments, the buried layer 107 has a distance D between the boundary near the second region 104 and the boundary between the first region 102 and the second region 104. In some embodiments, distance D is in a range from about 1 μm to about 100 μm. The distance D is a reserved distance of the doping process 105 to ensure that the dopants of the buried layer 107 do not diffuse into the second region 104 of the semiconductor substrate 101.
According to some embodiments, as shown in fig. 3, after forming the buried layer 107, the patterned mask 103 is removed and an epitaxial layer 109 is formed on the semiconductor substrate 101. In some embodiments, the epitaxial layer 109 may be N-type or P-type. The epitaxial layer 109 is formed on the first region 102 and the second region 104 of the semiconductor substrate 101 by a Metal Organic Chemical Vapor Deposition (MOCVD), a plasma-enhanced CVD (PECVD), a Molecular Beam Epitaxy (MBE), a Hydride Vapor Phase Epitaxy (HVPE), a Liquid Phase Epitaxy (LPE), a chloride vapor phase epitaxy (Cl-VPE), other similar processes, or a combination thereof.
In addition, in some embodiments, the buried layer 107 and the epitaxial layer 109 have a portion of the semiconductor substrate 101 therebetween, i.e., the buried layer 107 is completely located within the semiconductor substrate 101 and is not exposed on the top surface of the semiconductor substrate 101.
Subsequently, as shown in fig. 4, a first isolation structure 111 and a second isolation structure 113 are formed in the epitaxial layer 109 near the top surface of the epitaxial layer 109, where the first isolation structure 111 is located in the first region 102, and the second isolation structure 113 is located in the second region 104. In the present embodiment, the first isolation structure 111 and the second isolation structure 113 are Shallow Trench Isolation (STI) structures. In other embodiments, the first isolation structure 111 and the second isolation structure 113 are local oxidation of silicon (LOCOS) isolation structures (not shown), a portion of the first isolation structure 111 and the second isolation structure 113 is embedded in the epitaxial layer 109, and another portion of the first isolation structure 111 and the second isolation structure 113 is formed on the epitaxial layer 109.
In some embodiments, the first isolation structure 111 and the second isolation structure 113 are shallow trench isolation structures, and may be formed by etching and Chemical Vapor Deposition (CVD) processes. In other embodiments, the first isolation structure 111 and the second isolation structure 113 are silicon local oxidation isolation structures, and may be formed by chemical vapor deposition and thermal oxidation processes. Furthermore, the first isolation structure 111 and the second isolation structure 113 are formed of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
In some embodiments, the first isolation structure 111 and the second isolation structure 113 may be formed by a thermal oxidation (thermal oxidation) process, a Chemical Vapor Deposition (CVD) process, or a combination thereof, depending on the isolation type. Furthermore, the first isolation structure 111 and the second isolation structure 113 are formed of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
It is noted that in the cross-sectional view of fig. 4, the first isolation structure 111 has a first length L1, the second isolation structure 113 has a second length L2, and the second length L2 is greater than the first length L1. In some embodiments, the first length L1 is in a range from about 0.3 μm to about 3 μm, and the second length L2 is in a range from about 10 μm to about 50 μm.
The first isolation structure 111 is an isolation structure of a BCD transistor of the first element 200 to be subsequently formed, the second isolation structure 113 is an isolation structure of a UHV transistor of the second element 300 to be subsequently formed, and the second length L2 of the second isolation structure 113 is greater than the first length L1 of the first isolation structure 111 in order to withstand an ultra-high voltage (e.g., in a range of about 300 volts to about 800 volts).
Referring again to fig. 4, a first well 115, a second well 117, a third well 119, and a fourth well 121 are formed in the epitaxial layer 109. The first well 115 and the second well 117 are located on the first region 102 of the semiconductor substrate 101 and directly above the buried layer 107. In some embodiments, the projection of the second well 117 and the buried layer 107 in the direction perpendicular to the surface of the semiconductor substrate 101 partially overlap, and the projection range of the second well 117 in the direction perpendicular to the surface of the semiconductor substrate 101 may exceed the projection range of the buried layer 107 in the direction perpendicular to the surface of the semiconductor substrate 101. In other embodiments, the projection of the second well 117 in a direction perpendicular to the surface of the semiconductor substrate 101 is entirely within the extent of the buried layer 107. In addition, the third well 119 and the fourth well 121 are located on the second region 104 of the semiconductor substrate 101, and projections of the third well 119, the fourth well 121, and the buried layer 107 in a direction perpendicular to the surface of the semiconductor substrate 101 do not overlap at all.
In some embodiments, the first isolation structure 111 is located in the second well 117, and the second isolation structure 113 is located in the fourth well 121. The second well 117 is adjacent to the first well 115, and the fourth well 121 is adjacent to the third well 119.
Furthermore, the first well 115 and the third well 119 have a first conductivity type (in an embodiment of the P-type semiconductor substrate 101, the first well 115 and the third well 119 may be, for example, P-type), and the second well 117 and the fourth well 121 have a second conductivity type opposite to the first conductivity type (in an embodiment of the P-type semiconductor substrate 101, the second well 117 and the fourth well 121 may be, for example, N-type). The first trap 115, the second trap 117, the third trap 119, and the fourth trap 121 may be formed by ion implantation. In some embodiments, the first trap 115 and the third trap 119 may be formed by the same ion implantation process, and the second trap 117 and the fourth trap 121 may be formed by another ion implantation process.
According to some embodiments, as shown in fig. 5, a first gate structure 136 and a second gate structure 140 are formed on the epitaxial layer 109. The first gate structure 136 is located above an interface of the first well 115 and the second well 117, and covers a portion of the first isolation structure 111. The second gate structure 140 is located above an interface of the third well 119 and the fourth well 121, and covers a portion of the second isolation structure 113.
In some embodiments, the first gate structure 136 includes a first gate dielectric layer 135 and a first gate electrode layer 137 disposed on the first gate dielectric layer 135, and the second gate structure 140 includes a second gate dielectric layer 139 and a second gate electrode layer 141 disposed on the second gate dielectric layer 139.
The first gate dielectric layer 135 and the second gate dielectric layer 139 may be made of silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (low-k), or a combination of the foregoing. In some embodiments, first gate dielectric layer 135 and second gate dielectric layer 139 are formed simultaneously by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a spin-on (spinning) process.
The first gate electrode layer 137 and the second gate electrode layer 141 are made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), polysilicon, or other suitable materials. In some embodiments, the first gate electrode layer 137 and the second gate electrode layer 141 are formed simultaneously by deposition and patterning processes. The deposition process may be a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a combination thereof. The patterning process may include a photolithography process and an etching process.
Referring again to fig. 5, a first doping region 123 and a second doping region 125 are formed in the first well 115, a third doping region 127 is formed in the second well 117, a fourth doping region 129 and a fifth doping region 131 are formed in the third well 119, and a sixth doping region 133 is formed in the fourth well 121. In addition, the first doped region 123 is adjacent to the second doped region 125, and the fourth doped region 129 is adjacent to the fifth doped region 131.
In some embodiments, the first doping region 123 and the fourth doping region 129 have a first conductivity type (in an embodiment of the P-type semiconductor substrate 101, the first doping region 123 and the fourth doping region 129 may be, for example, P-type), and the second doping region 125, the third doping region 127, the fifth doping region 131, and the sixth doping region 133 have a second conductivity type (in an embodiment of the P-type semiconductor substrate 101, the second doping region 125, the third doping region 127, the fifth doping region 131, and the sixth doping region 133 may be, for example, N-type). In some embodiments, the dopant concentration of the first doped region 123, the second doped region 125, the third doped region 127, the fourth doped region 129, the fifth doped region 131, and the sixth doped region 133 is about 1x1015Atom/cubic centimeter (atom/cm)3) To about 1x1018Atom/cubic centimeter (atom/cm)3) Within the range of (1).
According to some embodiments, an inter-layer dielectric (ILD) layer 143 is formed on the epitaxial layer 109, the first gate structure 136 and the second gate structure 140, as shown in fig. 6. In some embodiments, the interlayer dielectric layer 143 is formed of silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other suitable dielectric materials. The interlayer dielectric layer 143 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin-on coating, or other suitable process.
After the interlayer dielectric layer 143 is formed, a first source electrode 145, a first drain electrode 147, a second source electrode 149, and a second drain electrode 151 are formed on the interlayer dielectric layer 143. In addition, via holes (via)145a, 145b, 147a, 149b, and 151a are formed within the interlayer dielectric layer 143.
The first source electrode 145 is electrically connected to the first and second doped regions 123 and 125 through via holes 145a and 145b, respectively, and the first drain electrode 147 is electrically connected to the third doped region 127 through via hole 147 a. In addition, a second source electrode 149 is electrically connected to the fourth and fifth doping regions 129 and 131 through via holes 149a and 149b, respectively, and a second drain electrode 151 is electrically connected to the sixth doping region 133 through a via hole 151 a. In some embodiments, the first source electrode 145, the first drain electrode 147, the second source electrode 149, and the second drain electrode 151, and the vias 145a, 145b, 147a, 149b, and 151a may comprise a metal or other suitable conductive material.
After the first source electrode 145, the first drain electrode 147, the second source electrode 149, and the second drain electrode 151 are formed, the semiconductor device 100 is completed. The semiconductor device 100 includes a first element 200 and a second element 300, the first element 200 including BCD transistors and the second element 300 including UHV transistors. The BCD transistors of the first component 200 are located on the first region 102 of the semiconductor substrate 101 and the UHV transistors of the second component 300 are located on the second region 104 of the semiconductor substrate 101.
In some embodiments, the UHV transistor of the second element 300 can withstand high voltages above about 500 volts. In addition, the second region 104 of the semiconductor substrate 100 may further have a medium voltage device (not shown) capable of withstanding about 30 volts. Due to the presence of the aforementioned medium voltage device, the second region 104 of the semiconductor substrate 101 has no latch-up problem, and it is not necessary to avoid latch-up by providing a buried layer in the second region 104 of the semiconductor substrate 100.
In addition, the circuit configuration of the BCD transistors of the first element 200 and the UHV transistors of the second element 300 may not be limited to that shown in fig. 6, in other embodiments, the BCD transistors of the first element 200 and the UHV transistors of the second element 300 may be integrated on the same substrate, and the first element 200 and the second element 300 may include other active and/or passive elements.
In the present embodiment, the buried layer 107 in the first region 102 of the semiconductor substrate 101 is a continuous layer of dopant material. In other embodiments, the buried layer 107 is a discontinuous layer of dopant material located in the first region 102 of the semiconductor substrate 101. In yet another embodiment, another buried layer (not shown) is formed in the second region 104 of the semiconductor substrate 101, and the buried layer in the second region 104 is covered by another cover halfThe patterned mask of the first region 102 of the conductive substrate 101 is formed, and the dopant concentration of the buried layer in the second region 104 is much lower than the dopant concentration of the buried layer 107 in the first region 102, the dopant concentration of the buried layer in the second region 104 may be, for example, about 1x1015Atom/cubic centimeter (atom/cm)3) To about 1x1017Atom/cubic centimeter (atom/cm)3) Is lower than the dopant concentration of the buried layer 107 in the first region 102 (about 1x 10)15Atom/cubic centimeter (atom/cm)3) To about 1x1018Atom/cubic centimeter (atom/cm)3)。
Embodiments of the present invention divide a semiconductor substrate into a first region in which a first element comprising BCD transistors is disposed and a second region in which a second element comprising UHV transistors is disposed. Forming a patterned mask covering the second region before performing an epitaxial process, and performing a doping process on the first region by using the patterned mask to form a buried layer in the first region, wherein the buried layer has the same conductivity type as the semiconductor substrate and has a dopant concentration higher than that of the semiconductor substrate, so that the latch-up effect of the BCD transistor in the first region of the semiconductor substrate can be effectively prevented, and the BCD transistor can be prevented from being burnt due to short circuit.
In addition, the patterned mask can prevent the formation of a buried layer with the same dopant concentration as the first region (i.e., the region where the BCD transistor is disposed) in the second region of the semiconductor substrate, thereby preventing the UHV transistor from failing and increasing the breakdown voltage of the UHV transistor. The buried layer is not extended to the second region of the semiconductor substrate, so that the BCD transistor and the UHV transistor can be smoothly integrated in the same semiconductor device, and the effects of avoiding latch-up and improving breakdown voltage are achieved at the same time.
The foregoing outlines features so that those skilled in the art may better understand the aspects of the present embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims (18)

1. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region;
a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the semiconductor substrate;
an epitaxial layer disposed on the semiconductor substrate;
a first device disposed on the first region of the semiconductor substrate, wherein the first device comprises a bipolar complementary metal oxide semiconductor-bipolar diffused metal oxide semiconductor transistor, wherein the bipolar complementary metal oxide semiconductor-bipolar diffused metal oxide semiconductor transistor comprises:
a first well disposed in the epitaxial layer and having the first conductivity type;
a second well disposed in the epitaxial layer and adjacent to the first well, wherein the second well has a second conductivity type opposite to the first conductivity type;
a first isolation structure located in the second well; and
a first gate structure disposed on the epitaxial layer and above an interface between the first well and the second well, wherein the first gate structure covers a portion of the first isolation structure; and
and a second element disposed on the second region of the semiconductor substrate, wherein the second element comprises an ultra-high voltage transistor and the buried layer does not extend to the second region of the semiconductor substrate.
2. The semiconductor device of claim 1, wherein an extent of the buried layer is less than or equal to an extent of the first region.
3. The semiconductor device of claim 1, wherein a portion of the semiconductor substrate is disposed between the buried layer and the epitaxial layer.
4. The semiconductor device of claim 1, wherein the uhp transistor has a second isolation structure, and wherein the length of the second isolation structure is greater than the length of the first isolation structure.
5. The semiconductor device of claim 1, wherein the BiCMOS-DMOS transistor further comprises:
a first doped region and a second doped region disposed in the first well, wherein the first doped region has the first conductivity type and the second doped region has the second conductivity type; and
a third doped region disposed in the second well and having the second conductivity type.
6. The semiconductor device of claim 5, wherein the BiCMOS-DMOS transistor further comprises:
a first source electrode and a first drain electrode disposed on the epitaxial layer, wherein the first source electrode is electrically connected to the first doped region and the second doped region, and the first drain electrode is electrically connected to the third doped region.
7. The semiconductor device according to claim 4, wherein the extra-high voltage transistor comprises:
a third well disposed in the epitaxial layer and having the first conductivity type;
a fourth well disposed in the epitaxial layer and adjacent to the third well, wherein the fourth well has a second conductivity type opposite to the first conductivity type, and the second isolation structure is located in the fourth well; and
and a second gate structure disposed on the epitaxial layer and above an interface between the third well and the fourth well, wherein the second gate structure covers a portion of the second isolation structure.
8. The semiconductor device according to claim 7, wherein the extra-high voltage transistor further comprises:
a fourth doped region and a fifth doped region disposed in the third well, wherein the fourth doped region has the first conductivity type and the fifth doped region has the second conductivity type; and
and a sixth doped region disposed in the fourth well and having the second conductivity type.
9. The semiconductor device according to claim 8, wherein the uhp transistor further comprises:
and a second source electrode and a second drain electrode disposed on the epitaxial layer, wherein the second source electrode is electrically connected to the fourth doped region and the fifth doped region, and the second drain electrode is electrically connected to the sixth doped region.
10. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate with a first conductive type, wherein the semiconductor substrate comprises a first area and a second area;
forming a patterned mask on the second region of the semiconductor substrate;
performing a doping process on the semiconductor substrate through the patterned mask to form a buried layer in the first region, wherein the buried layer has the first conductivity type and has a dopant concentration higher than that of the semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate;
forming a first device on the first region of the semiconductor substrate, wherein the first device comprises a bipolar-cmos-dmos transistor, wherein forming the bipolar-cmos-dmos transistor comprises:
forming a first well in the epitaxial layer, wherein the first well has the first conductivity type;
forming a second well in the epitaxial layer, wherein the second well is adjacent to the first well and has a second conductivity type opposite to the first conductivity type;
forming a first isolation structure in the second well; and
forming a first gate structure on the epitaxial layer, wherein the first gate structure is located above an interface of the first well and the second well, and the first gate structure covers a portion of the first isolation structure; and
forming a second element on the second region of the semiconductor substrate, wherein the second element comprises an ultra-high voltage transistor and the buried layer does not extend to the second region of the semiconductor substrate.
11. The method of claim 10, wherein the patterned mask is formed before the epitaxial layer is formed, the patterned mask completely covering the second region and extending to a portion of the first region.
12. The method of claim 10, wherein an extent of the buried layer is less than or equal to an extent of the first region.
13. The method of claim 10, wherein the uhp transistor has a second isolation structure, and wherein the second isolation structure has a length greater than a length of the first isolation structure.
14. The method of claim 10, wherein forming the BiCMOS-DMOS transistor further comprises:
forming a first doped region and a second doped region in the first well, wherein the first doped region has the first conductivity type and the second doped region has the second conductivity type; and
forming a third doped region in the second well, wherein the third doped region has the second conductivity type.
15. The method of manufacturing a semiconductor device according to claim 14, wherein forming the bipolar-cmos-ldmos transistor further comprises:
forming a first source electrode and a first drain electrode on the epitaxial layer, wherein the first source electrode is electrically connected to the first doped region and the second doped region, and the first drain electrode is electrically connected to the third doped region.
16. The method of manufacturing a semiconductor device according to claim 13, wherein the forming the uhp transistor comprises:
forming a third well in the epitaxial layer, wherein the third well has the first conductivity type;
forming a fourth well in the epitaxial layer, wherein the fourth well is adjacent to the third well and has a second conductivity type opposite to the first conductivity type, and the second isolation structure is formed in the fourth well; and
and forming a second gate structure on the epitaxial layer, wherein the second gate structure is positioned above an interface of the third well and the fourth well, and the second gate structure covers a part of the second isolation structure.
17. The method of claim 16, wherein forming the uhp transistor further comprises:
forming a fourth doped region and a fifth doped region in the third well, wherein the fourth doped region has the first conductivity type, and the fifth doped region has the second conductivity type; and
forming a sixth doped region in the fourth well, wherein the sixth doped region has the second conductivity type.
18. The method of claim 17, wherein forming the uhp transistor further comprises:
forming a second source electrode and a second drain electrode on the epitaxial layer, wherein the second source electrode is electrically connected to the fourth doped region and the fifth doped region, and the second drain electrode is electrically connected to the sixth doped region.
CN201710844807.7A 2017-09-19 2017-09-19 Semiconductor device and method for manufacturing the same Active CN109524395B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710844807.7A CN109524395B (en) 2017-09-19 2017-09-19 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710844807.7A CN109524395B (en) 2017-09-19 2017-09-19 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN109524395A CN109524395A (en) 2019-03-26
CN109524395B true CN109524395B (en) 2020-09-11

Family

ID=65768258

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710844807.7A Active CN109524395B (en) 2017-09-19 2017-09-19 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN109524395B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267882A1 (en) * 1986-11-10 1988-05-18 SGS MICROELETTRONICA S.p.A. Monolithic integration of isolated, high performance, power vdmos transistors and of high voltage p-channel mos transistors together with cmos, npn, pnp transistors and low leakage diodes
US20070120150A1 (en) * 2005-10-17 2007-05-31 Infineon Technologies Ag Semiconductor component arrangement and method for fabricating it
CN102891088A (en) * 2012-09-17 2013-01-23 电子科技大学 Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device
US20130049113A1 (en) * 2011-08-23 2013-02-28 Jeesung Jung U-shape resurf mosfet devices and associated methods of manufacturing
CN103840008A (en) * 2014-03-31 2014-06-04 成都立芯微电子科技有限公司 High-voltage LDMOS device based on BCD process and manufacturing process
CN104051534A (en) * 2012-12-19 2014-09-17 万国半导体股份有限公司 Vertical DMOS transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267882A1 (en) * 1986-11-10 1988-05-18 SGS MICROELETTRONICA S.p.A. Monolithic integration of isolated, high performance, power vdmos transistors and of high voltage p-channel mos transistors together with cmos, npn, pnp transistors and low leakage diodes
US20070120150A1 (en) * 2005-10-17 2007-05-31 Infineon Technologies Ag Semiconductor component arrangement and method for fabricating it
US20130049113A1 (en) * 2011-08-23 2013-02-28 Jeesung Jung U-shape resurf mosfet devices and associated methods of manufacturing
CN102891088A (en) * 2012-09-17 2013-01-23 电子科技大学 Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device
CN104051534A (en) * 2012-12-19 2014-09-17 万国半导体股份有限公司 Vertical DMOS transistor
CN103840008A (en) * 2014-03-31 2014-06-04 成都立芯微电子科技有限公司 High-voltage LDMOS device based on BCD process and manufacturing process

Also Published As

Publication number Publication date
CN109524395A (en) 2019-03-26

Similar Documents

Publication Publication Date Title
US9257533B2 (en) Method of making an insulated gate bipolar transistor structure
US9076837B2 (en) Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
US9406669B2 (en) Method and structure for vertical tunneling field effect transistor and planar devices
US11855158B2 (en) Semiconductor device structure having a gate structure and overlying dielectric layer
TWI525821B (en) Mosfet device and method for manufacturing the same
US20110260245A1 (en) Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device
KR20140111917A (en) Structure and method for vertical tunneling field effect transistor with leveled source and drain
US11508845B2 (en) Semiconductor structure and associated fabricating method
KR20120088601A (en) Semiconductor device and manufacturing method thereof
US10388649B2 (en) Semiconductor devices and methods for manufacturing the same
TWI624942B (en) High voltage semiconductor device
US10686036B2 (en) Method of making bipolar transistor
CN109524395B (en) Semiconductor device and method for manufacturing the same
JP2006505943A (en) Semiconductor device channel termination
TWI670799B (en) Semiconductor devices and methods for manufacturing the same
TWI676291B (en) Semiconductor substrate structures and methods for forming the same and semiconductor devices
US9837411B2 (en) Semiconductor die with a metal via
US20110263112A1 (en) Method for forming a schottky diode having a metal-semiconductor schottky contact
CN113437149B (en) Semiconductor structure and forming method thereof
JP6235662B2 (en) Semiconductor device
JP5986618B2 (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant