CN109522713A - A method of based on B ü chi automatic machine abbreviation run time verification monitor - Google Patents
A method of based on B ü chi automatic machine abbreviation run time verification monitor Download PDFInfo
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- CN109522713A CN109522713A CN201811359544.1A CN201811359544A CN109522713A CN 109522713 A CN109522713 A CN 109522713A CN 201811359544 A CN201811359544 A CN 201811359544A CN 109522713 A CN109522713 A CN 109522713A
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- automatic machine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4498—Finite state machines
Abstract
The present invention discloses a kind of method based on B ü chi automatic machine abbreviation run time verification monitor, converts B ü chi automatic machine for the attribute that LTL formula describes first；Then redundant marks and removal are carried out to the state of B ü chi automatic machine；Find the state pair for meeting fair simulative relation mutually in B ü chi automatic machine later, and to state to merging；The B ü chi automatic machine after abbreviation is finally converted to deterministic finite state automata, obtains the monitor for verifying.The present invention can speed up the conversion of B ü chi automatic machine to deterministic finite state automata, while memory overhead when verifying JavaMop tool is reduced.
Description
Technical field
The present invention relates to run time verification technical fields, and in particular to tests when one kind is based on the operation of B ü chi automatic machine abbreviation
The method for demonstrate,proving monitor.
Background technique
Run time verification (RV) is a kind of technology for being detected based on system running state and being occurred extremely, can be to
The system of operation is monitored in real time, once the behavior of discovery system violates certain attribution rules, will give immediately prompting or
It reacts.When carrying out run time verification, monitor is the module detected to the system of being verified, it receives the fortune of system
Whereabouts mark carries out inspection judgement to whether system action meets given attribute, and provide a knot then according to given attribute
By.Monitor has important role in verification process at runtime, its operational efficiency affects the effect of whole system verifying
Rate.
Currently, there are many building methods of monitor, wherein the monitor constructing technology based on automatic machine is relatively conventional.Bü
Chi automatic machine is ω-automatic machine one kind, and finite-state automata is extended to by it can receive the automatic machine infinitely inputted, i.e.,
Receive the automatic machine of a unlimited list entries.B ü chi automatic machine is the side for substituting and handling well ω regular language
Formula because they be under boolean operation it is closed, it is commonly used in the formalization verification method based on automatic machine.?
In run time verification, the finite state automata of determinization is often converted into using the attribute that temporal logic describes, B ü chi is certainly
Motivation is in this conversion process by the medium as a centre.However, in this conversion process the state of automatic machine and
The quantity of transition relationship is very big, can consume a large amount of memory and time, this needs further abbreviation and improves.
Summary of the invention
To be solved by this invention carried out based on B ü chi automatic machine in existing run time verification tool JavaMOP
Existing larger overhead issues when verifying provide a kind of method based on B ü chi automatic machine abbreviation run time verification monitor,
It can state and transition relationship in abbreviation conversion process, reduce monitoring expense.
To solve the above problems, the present invention is achieved by the following technical solutions:
A method of based on B ü chi automatic machine abbreviation run time verification monitor, specifically including that steps are as follows:
The attribute that linear temporal formula describes is converted to non-determined B ü chi automatic machine by step 1；
Step 2, non-determined B ü chi automatic machine obtained for step 2 state set in each state, judge with
When the state starts, whether the language that non-determined B ü chi automatic machine receives is empty: if it is empty, then carrying out redundancy mark to the state
Note；Otherwise, which does not mark；
Step 3, by the obtained state for having redundant marks of step 2 from the state set of non-determined B ü chi automatic machine
It deletes, the non-determined B ü chi automatic machine tentatively simplified；
Step 4 finds the fair mould of satisfaction mutually in the obtained non-determined B ü chi automatic machine tentatively simplified of step 3
The state pair of quasi- relationship；
Step 5, to the obtained state of step 4 to merging, the non-determined B ü chi automatic machine that is finally simplified；
The obtained non-determined B ü chi automatic machine finally simplified of step 5 is converted to non-determined finite state by step 6
Automatic machine, then to being determined of non-deterministic finite automaton after, obtain deterministic finite state automata；
Step 7, the monitor that the obtained deterministic finite state automata of step 6 is acted on to system verifying.
Detailed process is as follows for above-mentioned steps 1: firstly, converting the attribute that linear temporal formula describes to staggeredly certainly
Motivation；Then, staggeredly automatic machine is converted to the B ü chi automatic machine of broad sense；Finally, the B ü chi automatic machine of broad sense is converted into
Non-determined B ü chi automatic machine.
Above-mentioned steps 5 need to check whether merging phase can change preliminary simplification to after when carrying out the merging of state pair
The language that receives of non-determined B ü chi automatic machine: if the language received does not change, to this to state to merging,
And remove merge after extra transfer relationship；Otherwise, without the merging of state pair.
Compared with current run time verification tool JavaMOP, the medicine have the advantages that being based on B ü chi automatic machine
The method of monitor in abbreviation run time verification, this method are to do on verification tool JavaMOP to optimize at runtime: before this to fortune
The redundant state of B ü chi automatic machine obtained in verification process carries out judge mark when row, deletes redundant state；B ü is searched again
The state pair for meeting fair simulative relation in chi automatic machine mutually, merges the state pair for meeting this relationship, and remove it is extra
Transition relationship, and do not change the language of automatic machine receiving.By executing the operation in the present invention, automatic machine can be effectively reduced
Memory overhead, accelerate B ü chi automatic machine to the conversion of deterministic finite state automata, run us to system
When reduction verifying expense when verifying.
Detailed description of the invention
Fig. 1 is a kind of method flow diagram based on B ü chi automatic machine abbreviation run time verification monitor.
Fig. 2 is that the example based on fair simulation abbreviation automatic machine is (b) wherein (a) is the B ü chi automatic machine before abbreviation
B ü chi automatic machine after abbreviation.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific example, and referring to attached
Figure, the present invention is described in more detail.
A method of based on monitor in B ü chi automatic machine abbreviation run time verification, as shown in Figure 1, it is specifically included
Step:
Step 1 using the method in existing JavaMOP verification tool is described LTL (linear temporal) formula
Attribute is converted to non-determined B ü chi automatic machine.
Firstly, converting staggeredly automatic machine for the attribute that LTL formula describes；Then, staggeredly automatic machine is converted to broad sense
B ü chi automatic machine；Finally, the non-determined B ü chi automatic machine that the B ü chi automatic machine conversion of broad sense is needed.
Step 2 carries out redundant marks to the state in non-determined B ü chi automatic machine.
Sentence sky algorithm using one to find the redundant state in non-determined B ü chi automatic machine and carry out redundant marks.It is right
Each state q ∈ Q (state set that Q is automatic machine) in automatic machine, B ü chi automatic machine when judging to start with this state q
Whether the language of receiving is empty: if the language received is sky, i.e. f (q)=true, then receiving language to B ü chi automatic machine is
Empty state carries out redundant marks, indicates that these states are redundant states, automatic machine will not be influenced after removing it；If connect
The language received is not sky, i.e. f (q)=false then retains these states, without label.
Step 3, to thering is the state of redundant marks to carry out removal operation in non-determined B ü chi automatic machine, tentatively simplified
Non-determined B ü chi automatic machine.
It is executed with RRS algorithm (redundant state removal algorithm) and removes operation, a B ü chi automatic machine is inputted, for having
The state of redundant marks, i.e. f (q)=true remove it from state of automata set Q, i.e., execution Q ← Q { q }, circulation is sentenced
A preliminary simplified B ü chi automatic machine is obtained after disconnected execution.
Step 4 after removing the redundant state of non-determined B ü chi automatic machine, recycles the related algorithm of fair simulation to exist
The state for meeting fair simulative relation mutually is found in the non-determined B ü chi automatic machine tentatively simplified to (p, q).
To a B ü chi automatic machine, fair simulative relation is expressed asThat is state q justice simulation is indicated in q'
For q≤fQ', and if only if to any ω=a1a2..., there are π=qa1q1a2... so that there are π '=q'a1q'1a2... and it is right
ArbitrarilySet up so thatAlso it sets up, wherein a indicates to execute movement, q table in automatic machine
Showing the state in automatic machine, A indicates automatic machine,Indicate the language that automatic machine A receives.It is found in B ü chi automatic machine mutually
Mutually meet the state of fair simulative relation to (p, q), that is, be state p and q meet q≤fP and p≤fq。
Step 5, to the mutual state pair for meeting fair simulative relation in the non-determined B ü chi automatic machine tentatively simplified
(p, q) is merged, the non-determined B ü chi automatic machine finally simplified.
When the state obtained to step 4 is to union operation is executed, need to check whether these states of merging can change to after
Become the language that automatic machine receives: if the language that automatic machine receives does not change, merging and meet fair simulative relation mutually
State pair, at the same remove merge after extra transfer relationship；If the language that automatic machine receives changes, this cannot be merged
A little states.
In the present embodiment, it is calculated by using Jurdzinskis algorithm and meets fair simulation pass in B ü chi automatic machine
The state of system obtains the set for meeting the state pair of fair simulative relation mutually, that is, executes the knot that step 4 obtains
Fruit, at the same Jurdzinskis algorithm can also check merge these states to whether can change automatic machine receiving language.
Fig. 2 gives the example based on fair simulative relation abbreviation automatic machine, and (a) is the B ü chi automatic machine before abbreviation,
(b) it is B ü chi automatic machine after abbreviation.Having two pairs of states in this B ü chi automatic machine is the mutual pass for meeting fair simulation
System, i.e. (q1, q4) and (q8, q9), therefore we can merge q1And q4, q8And q9.State is being incorporated to (q1, q4) and (q8,
q9) after, transfer relationship (q1, a, q3) to automatic machine receive language be it is extra, can be removed, later state q3And q5It is
Inaccessible state can also be removed.
Step 6 has executed the B ü chi automatic machine minimized after above step 2-5, then converts it into non-determined
Finite-state automata, then being determined obtain deterministic finite state automata.
Step 7, the monitor that the obtained deterministic finite state automata of step 6 is acted on to system verifying.
The present invention adds an abbreviation B ü chi certainly by being converted among non-determined finite automata in B ü chi automatic machine
The process of motivation obtains the B ü chi automatic machine of a minimum, then converts the B ü chi automatic machine of minimum to and non-determined have
State automata is limited, last determinization obtains deterministic finite state automata, the certainty finity state machine at this moment obtained
B ü chi automatic machine is compared much smaller before among the memory headroom and abbreviation of machine consumption, so that applying to the prison of system verifying
Device executive overhead is controlled to reduce.
It should be noted that although the above embodiment of the present invention be it is illustrative, this be not be to the present invention
Limitation, therefore the invention is not limited in above-mentioned specific embodiment.Without departing from the principles of the present invention, all
The other embodiment that those skilled in the art obtain under the inspiration of the present invention is accordingly to be regarded as within protection of the invention.
Claims (3)
1. a kind of method based on B ü chi automatic machine abbreviation run time verification monitor, characterized in that specifically include following step
It is rapid:
The attribute that linear temporal formula describes is converted to non-determined B ü chi automatic machine by step 1；
Step 2, non-determined B ü chi automatic machine obtained for step 2 state set in each state, judge with the shape
When state starts, whether the language that non-determined B ü chi automatic machine receives is empty: if it is empty, then carrying out redundant marks to the state；It is no
Then, which does not mark；
Step 3 deletes the obtained state for having redundant marks of step 2 from the state set of non-determined B ü chi automatic machine,
The non-determined B ü chi automatic machine tentatively simplified；
Step 4, searching meets mutually fair simulation pass in the obtained non-determined B ü chi automatic machine tentatively simplified of step 3
The state pair of system；
Step 5, to the obtained state of step 4 to merging, the non-determined B ü chi automatic machine that is finally simplified；
The obtained non-determined B ü chi automatic machine finally simplified of step 5 is converted to non-determined finity state machine by step 6
Machine, then to being determined of non-deterministic finite automaton after, obtain deterministic finite state automata；
Step 7, the monitor that the obtained deterministic finite state automata of step 6 is acted on to system verifying.
2. a kind of method based on B ü chi automatic machine abbreviation run time verification monitor according to claim 1, feature
It is that detailed process is as follows for step 1: firstly, converting staggeredly automatic machine for the attribute that linear temporal formula describes；It connects
, staggeredly automatic machine is converted to the B ü chi automatic machine of broad sense；Finally, the B ü chi automatic machine of broad sense is converted into non-determined B ü
Chi automatic machine.
3. a kind of method based on B ü chi automatic machine abbreviation run time verification monitor according to claim 1, feature
It is step 5, when carrying out the merging of state pair, to need to check whether merging phase can change the non-determined B tentatively simplified to after
The language that ü chi automatic machine receives: if the language received does not change, to this to state to merging, and remove merging
Extra transfer relationship afterwards；Otherwise, without the merging of state pair.
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| CN110297773A (en) * | 2019-07-01 | 2019-10-01 | 成都奥卡思微电科技有限公司 | Comprehensive method for visualizing, storage medium and terminal are asserted in a kind of formal verification |
| CN111352848A (en) * | 2020-03-09 | 2020-06-30 | 南京航空航天大学 | Method for measuring monitorability probability of property in runtime verification |
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| CN110245085A (en) * | 2019-04-08 | 2019-09-17 | 华东师范大学 | The embedded real-time operating system verification method and system examined using on-time model |
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Application publication date: 20190326 |