CN109511216A - A kind of reliability evaluation multilayer circuit board - Google Patents
A kind of reliability evaluation multilayer circuit board Download PDFInfo
- Publication number
- CN109511216A CN109511216A CN201811548138.XA CN201811548138A CN109511216A CN 109511216 A CN109511216 A CN 109511216A CN 201811548138 A CN201811548138 A CN 201811548138A CN 109511216 A CN109511216 A CN 109511216A
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- CN
- China
- Prior art keywords
- instrument connection
- test
- circuit board
- hole wall
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 title claims abstract description 19
- 238000012360 testing method Methods 0.000 claims abstract description 95
- 238000012545 processing Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 26
- 238000005553 drilling Methods 0.000 claims abstract description 23
- 238000005259 measurement Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 239000011241 protective layer Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000003754 machining Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 239000000306 component Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
Abstract
The invention discloses a kind of reliability evaluation multilayer circuit board, including multiple test sections, each test section includes drilling region and hole wall state test zone, and the aperture of the instrument connection in the drilling region of different test sections is different；Each drilling region includes the test hole array in the same aperture processed by same drill bit; the inner wall of instrument connection from inside to outside successively have conductive layer and protective layer, between instrument connection and instrument connection positioned at the interlayer of multilayer circuit board and the measurement circuit of outer layer conductive test route in series；Also there are two continuity testing pads for tool on the outer-layer circuit plate in drilling region, are connect respectively by a conducting wire with instrument connection corresponding to the starting point of conductive test route and end；Since each hole wall state test zone include processing the same drill bit of instrument connection processing the 1st instrument connection, is spaced the hole wall state instrument connection processed after a certain number of instrument connections in hole wall state test zone.Present invention energy science accurately judges product reliability.
Description
Technical field
The present invention relates to printed wiring board fields, more particularly, to a kind of reliability evaluation multilayer circuit board.
Background technique
The effective carrier of wiring board effect electronic component is called always the aircraft carrier of electronic component, is that hyundai electronics are set
Standby, product key core component is that fast-developing powerful support is able to modern science and technology technical level, to the peace of product
Entirely, stable, efficient, reliability has huge effect and influences, especially in Aeronautics and Astronautics, military project, automobile, shipbuilding, power generation
Field require just more stringent, therefore, people guarantee wiring board efficient, high speed, high-quality, low by various technological means
Cost is produced into as important subject and activity description.
It is specified that reliability refers to that finger element, product, system trouble-freely execute within a certain period of time, under certain condition
The ability or possibility of function can evaluate the reliability of product by reliability, crash rate, Mean interval etc..It is right
For product, the reliability the high better.The product of high reliablity, can work normally that (this is exactly all consumers for a long time
It needs)；For from technical term, be exactly product reliability it is higher, product can be with the time of no-failure operation just
It is longer.Wiring board product reliability test technology is extremely complex at present, and process is also different style, but all do not unify
Standard is tested by technical staff according to the experience, level, professional knowledge etc. of oneself, since method is different therefore causes to tie
Fruit also has very big difference, leads to many times make the reliability of product accurately test and judgement, therefore shadow
The end-use properties of product are rung, so, it has very important significance to the research of the test of product reliability.
Summary of the invention
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of reliability evaluation multilayer line is provided
Multiple important reliability tests synthesis are completed on a reliability test wiring board by time processing technique, are had by plate
Have easy to operate, design rationally, be easily mastered, the features such as manufacturing cost is low, effect is obvious.
To achieve the above object, technical scheme is as follows:
A kind of reliability evaluation multilayer circuit board, which is characterized in that including multiple test sections, each test section includes drilling
The aperture of region and hole wall state test zone, the instrument connection in the drilling region of different test sections is different；
Each drilling region includes the test hole array in the same aperture processed by same drill bit, and the inner wall of instrument connection is by interior
To outside successively with conductive layer and protective layer, the survey of the interlayer and outer layer positioned at multilayer circuit board between instrument connection and instrument connection
Try route conductive test route in series；Also there are two continuity testing pads for tool on the outer-layer circuit plate in drilling region, divide
Not Tong Guo a conducting wire connect with instrument connection corresponding to the starting point of conductive test route and end；
Since each hole wall state test zone include processing the same drill bit of instrument connection processing the 1st instrument connection, interval
In the hole wall state instrument connection of hole wall state test zone processing after a certain number of instrument connections.
Further, the conductive test route is in every row instrument connection in the cross-wise direction of the thickness of multilayer circuit board
In " V " type broken line be distributed, do not go together between instrument connection connection take nearby connection principle connection, until make drill region institute
There are between adjacent instrument connection all connecting test routes.
Further, the hole wall state test zone further includes the processing location hole of hole wall state instrument connection.
Further, the drilling region and the hole wall state test zone further include mark.
Further, the hole wall state test zone further includes two microsection manufacture location holes.
Further, the edge of the multilayer circuit board further includes technology hole.
Further, it is connect by pad with measurement circuit around instrument connection.
It can be seen from the above technical proposal that the present invention is by by multiple important reliabilities in route board machining process
Test is incorporated on a reliability test wiring board to be completed by time processing technique, and important reliability assessment includes
Wiring board circuit reliability in extreme circumstances and mechanical property reliability after the material test of board substrate, processing etc.
Test, this method can science, accurately to product reliability can make accurate judgement and identification, have it is easy to operate, set
The features such as meter is rationally, capacity is grasped, manufacturing cost is low, effect is obvious.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of reliability evaluation multilayer circuit board of the invention；
Fig. 2 is the enlarged structure schematic diagram in the drilling region in Fig. 1；
Fig. 3 is the section partial structural diagram along route plate thickness direction；
Fig. 4 is the enlarged structure schematic diagram of the hole wall state test zone in Fig. 1；
100 be drilling region in figure, and 101 be pad, and 102 be test hole array, and 103 and 105 be continuity testing pad,
104 identify for test section, and 106 be measurement circuit, and 107 be instrument connection, and 200 be hole wall state test zone, and 201 be hole wall state
Instrument connection, 202 be microsection manufacture location hole, and 203 be the processing location hole of hole wall state instrument connection, and 300 be technology hole.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
It should be noted that in following specific embodiments, when describing embodiments of the invention in detail, in order to clear
Ground indicates structure of the invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should be avoided in this, as limitation of the invention to understand.
Important reliability assessment includes that the material of board substrate is tested, the wiring board after processing is in extreme environment
Under circuit reliability and mechanical property reliability etc. test, board substrate and wiring board working process parameter mutual
Match, the reliability of finished product wiring board obtained is just higher.The present invention uses specific circuit plate to the board substrate of particular batch
Finished product wiring board made from processing technology carries out reliability assessment.
In specific embodiment of the invention below, FIG. 1 to FIG. 4 is please referred to.As shown, a kind of reliability evaluation is more
Sandwich circuit board, including multiple test sections, each test section include drilling region and hole wall state test zone, different test sections
The aperture of the instrument connection in drilling region is different.It is summarized from route board machining process in the aperture of the instrument connection of each test section
It arrives.
Each drilling region includes the test hole array in the same aperture processed by same drill bit, from the of test hole array
1 hole starts to process, and every a certain number of instrument connections of processing process a hole wall state instrument connection in hole wall state test zone.
Due to using same drill bit, it can judge the hardness of board substrate indirectly by the abrasion condition of drill bit.Test
Hole array figure is usually thousands of to tens of thousands of using instrument connection as much as possible as principle.
The inner wall of instrument connection successively has conductive layer and protective layer from inside to outside, and being located between instrument connection and instrument connection is more
The interlayer of sandwich circuit board and the measurement circuit of outer layer conductive test route in series；Also have on the outer-layer circuit plate in drilling region
There are two continuity testing pads, pass through instrument connection corresponding to the starting point and end of a conducting wire and conductive test route respectively
Connection.
In the present embodiment, referring to figs. 2 and 3, conductive test route is by more for the specific implementation of conductive test route
A measurement circuit is in series, and measurement circuit is evenly distributed on the interlayer and outer layer of the wiring board in entire drilling region, in every row
Instrument connection is distributed in the cross-wise direction of the thickness of multilayer circuit board in " V " type broken line.Specifically, by taking 6 sandwich circuit boards as an example,
Including L1~L6 laminate face, measurement circuit is etched in each plate face, the survey of the first connectivity is established at L1 layers of multilayer circuit board
Test weld disk 103, the first continuity testing pad 103 and first Kong Yuyong conducting wire of the first row of L1 layers of laminated wiring board connect
It connects, the 1st hole of the 1st row of L1 layers of laminated wiring board and is connected between the 2nd hole of test section length direction with measurement circuit
It connects, the 2nd hole of L2 layers of laminated wiring board and is connected between the 3rd hole of test section length direction with measurement circuit, successively connected
It connects until the 6th hole of L6 layer circuit board is connect with the 7th hole with measurement circuit and then through-thickness connects up, i.e. layer
It closes the 5th layer of wiring board of the 7th hole to connect with the 8th hole with measurement circuit, until the 1st row instrument connection is all connected and finished.It takes nearby
Principle is connect with the 2nd row instrument connection, later, along direction from right to left, according to the 1st row instrument connection interlayer p-wire
The identical mode in road continues to arrange measurement circuit between the 2nd row instrument connection, until all instrument connections of all rows are all connected with test
Route, the last one instrument connection are connect by conducting wire with the second continuity testing pad 105.Preferably, pass through around instrument connection
Pad is connect with measurement circuit.
The conductive test route is tested for Circuit Connectivity, and it is real that the multilayer circuit board in the region that drills is carried out thermal stress
It tests, is placed in 188 DEG C of tin-lead pots and impregnates about 10 seconds kinds or so, repeat 3-6 times.Two connectivity are tested using resistance value tester to survey
Change rate of the resistance value before and after Thermal Stress Experiment between test weld disk, according between the size of resistance change rate assessment pcb layer
And the reliability of outer circuit.Generally commented with being not more than 2% for qualification, or with professional standard or customer requirement standard
Valence.If change in resistance is excessive, open circuit is had occurred in conducting wire in destructive test, is connected using resistance value tester any
Instrument connection can determine that the specific location (such as positioned at which specific sandwich circuit board) of open circuit occurs for conducting wire.Due to test
Hole number is more, counts to the specific location that open circuit occurs, and statistical result is relatively reliable, then the more position of open circuit occurs
Representative processing step is just to need improved processing step.
Since each hole wall state test zone include processing the same drill bit of instrument connection processing the 1st instrument connection, interval
In the hole wall state instrument connection of hole wall state test zone processing after a certain number of instrument connections.Use hole wall state test section
The multilayer circuit board in domain carries out the bond strength test between shock resistance, wear-resistant, tear-proof and the different materials of wiring board, by hole
The multilayer circuit board of wall-like state test zone carries out Thermal Stress Experiment, is placed in 188 DEG C of tin-lead pots and impregnates about 10 seconds kinds or so, weight
It is 3-6 times multiple.Then, hole wall state instrument connection is ground into half bore, by comparing the hole wall for the hole wall state instrument connection successively processed
The shock resistance of the variation assessment wiring board of roughness state and antiwear property, by the combination shape for observing layers of copper and copper protective layer
Bond strength between state assessment material assesses the lear energy of wiring board by the wick effect between observation layers of copper and substrate.
It is processed since all holes on this slice are cutters in the 499 hole states that are spaced, this can be evaluated substantially
The hole wall state that class material is presented at a temperature of different cutter diameters, different cutting-tool wear states, varying environment, has certain cover
Capping, can accurate, science the physical property for judging material and stable chemical performance character state.
Since each hole wall state test zone requires to do slice milled processed, in order to improve process velocity, Ke Yi
The design for increasing the processing location hole and microsection manufacture location hole of hole wall state instrument connection in hole wall state test zone, uses pin
Nail, which connects together multiple wiring boards, to be ground, and grinding efficiency can be improved.It the processing location hole of hole wall state instrument connection and cuts
Bore process processing can be used in piece production location hole.
In order to avoid obscuring, the design of mark, the mark can be increased in each drilling region and hole wall state test zone
Knowing can be processed using bore process.
The edge of multilayer circuit board further includes technology hole, is used convenient for the positioning in route board machining process.
The preparation method of above-mentioned reliability evaluation multilayer circuit board the following steps are included:
Step S1: being designed according to above-mentioned reliability evaluation multilayer circuit board, the layer including determining multilayer circuit board
Number, test section number, the line number for testing hole array and columns, the number of instrument connection, the spacing between instrument connection, hole wall state are surveyed
The position of prospect hole and each interior layer pattern of quantity, multilayer circuit board and outer patterns etc..
Step S2: carry out reliability evaluation multilayer circuit board production, according to early-stage preparations → engineering design → sawing sheet →
Blanking → beat pin → internal layer production → lamination → drilling → change plating → plating → outer graphics production processing step processes to obtain
Reliability evaluation multilayer circuit board.
Step S3: the wiring board in each drilling region and hole wall state test zone is cut down, carries out circuit company respectively
Bond strength test between general character test and the shock resistance of wiring board, wear-resistant, tear-proof and different materials etc..
In conclusion the present invention is by being incorporated in one for multiple important reliability tests in route board machining process
Completed on reliability test wiring board by time processing technique, can science, accurately product reliability can be made accurately
Judgement and identification have the characteristics that easy to operate, design is reasonable, capacity is grasped, manufacturing cost is low, effect is obvious.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Anyone skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (7)
1. a kind of reliability evaluation multilayer circuit board, which is characterized in that including multiple test sections, each test section includes bore area
The aperture of domain and hole wall state test zone, the instrument connection in the drilling region of different test sections is different；
Each drilling region includes the test hole array in the same aperture processed by same drill bit, and the inner wall of instrument connection is from inside to outside
Successively have conductive layer and protective layer, between instrument connection and instrument connection positioned at the interlayer of multilayer circuit board and the p-wire of outer layer
Road conductive test route in series；Also there are two continuity testing pads for tool on the outer-layer circuit plate in drilling region, lead to respectively
A conducting wire is crossed to connect with instrument connection corresponding to the starting point of conductive test route and end；
Since each hole wall state test zone include processing the same drill bit of instrument connection processing the 1st instrument connection, and interval is certain
In the hole wall state instrument connection of hole wall state test zone processing after the instrument connection of quantity.
2. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that the conductive test route is every
Row instrument connection in the cross-wise direction of the thickness of multilayer circuit board in " V " type broken line be distributed, do not go together between instrument connection connect
It connects and takes connection principle connection nearby, until all connecting test route between all adjacent instrument connections in the region that makes to drill.
3. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that the hole wall state test zone
It further include the processing location hole of hole wall state instrument connection.
4. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that the drilling region and the hole
Wall-like state test zone further includes mark.
5. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that the hole wall state test zone
It further include two microsection manufacture location holes.
6. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that the edge of the multilayer circuit board
It further include technology hole.
7. reliability evaluation multilayer circuit board according to claim 1, which is characterized in that around instrument connection by pad with
Measurement circuit connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811548138.XA CN109511216A (en) | 2018-12-18 | 2018-12-18 | A kind of reliability evaluation multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811548138.XA CN109511216A (en) | 2018-12-18 | 2018-12-18 | A kind of reliability evaluation multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109511216A true CN109511216A (en) | 2019-03-22 |
Family
ID=65753492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811548138.XA Pending CN109511216A (en) | 2018-12-18 | 2018-12-18 | A kind of reliability evaluation multilayer circuit board |
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| Country | Link |
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| CN (1) | CN109511216A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112684324A (en) * | 2020-12-30 | 2021-04-20 | 无锡市同步电子科技有限公司 | Method for rapidly exciting and verifying faults of PCB for airborne electronic controller |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102435792A (en) * | 2011-09-28 | 2012-05-02 | 东莞生益电子有限公司 | Additionally connected test plate for reliability test of PCB (Printed Circuit Board) back drill and test method thereof |
| CN105467172A (en) * | 2016-01-01 | 2016-04-06 | 广州兴森快捷电路科技有限公司 | CAF testing plate with switching circuit |
| CN209593896U (en) * | 2018-12-18 | 2019-11-05 | 大连崇达电路有限公司 | A kind of reliability evaluation multilayer circuit board |
-
2018
- 2018-12-18 CN CN201811548138.XA patent/CN109511216A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102435792A (en) * | 2011-09-28 | 2012-05-02 | 东莞生益电子有限公司 | Additionally connected test plate for reliability test of PCB (Printed Circuit Board) back drill and test method thereof |
| CN105467172A (en) * | 2016-01-01 | 2016-04-06 | 广州兴森快捷电路科技有限公司 | CAF testing plate with switching circuit |
| CN209593896U (en) * | 2018-12-18 | 2019-11-05 | 大连崇达电路有限公司 | A kind of reliability evaluation multilayer circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112684324A (en) * | 2020-12-30 | 2021-04-20 | 无锡市同步电子科技有限公司 | Method for rapidly exciting and verifying faults of PCB for airborne electronic controller |
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