CN109509218B - The method, apparatus of disparity map is obtained based on FPGA - Google Patents
The method, apparatus of disparity map is obtained based on FPGA Download PDFInfo
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- CN109509218B CN109509218B CN201910095329.3A CN201910095329A CN109509218B CN 109509218 B CN109509218 B CN 109509218B CN 201910095329 A CN201910095329 A CN 201910095329A CN 109509218 B CN109509218 B CN 109509218B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/30—Determination of transform parameters for the alignment of images, i.e. image registration
- G06T7/33—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
- G06T7/337—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods involving reference images or patches
Abstract
The invention discloses the method, apparatus that disparity map is obtained based on FPGA, to solve the lower technical problem of the precision of disparity map of acquisition existing in the prior art.It include: to be calculated with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously in setting disparity range, obtain the corresponding integer disparity value of smallest match cost of each pair of match point in left mesh figure and right mesh figure；With linear interpolation method, discretization is carried out by setting accuracy between two adjacent parallax values of integer disparity value, and calculate the corresponding small several levels matching cost of each parallax interpolation, it will be in the corresponding small several levels matching cost of all parallax interpolation, sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point, to obtain the disparity map of the sub-pixel of left mesh figure and right mesh figure；Wherein, setting accuracy is inversely proportional with 2 n times side, and n is in FPGA for storing decimal digits according to the data bits used.
Description
Technical field
The present invention relates to field of image processings, more particularly, to the method, apparatus for obtaining disparity map based on FPGA.
Background technique
Binocular stereo vision principle is similar to human eye, is all to obtain target object in two width figures by left and right two images
Alternate position spike (as parallax) as in, then the spatial coordinated information by target object in parallaxometer calculating actual scene.
In general, the size of parallax is related with the distance of target object range Imaging equipment, distance is remoter, and parallax is smaller.And
The process for obtaining parallax is known as Stereo matching, this will directly affect the measurement result of the spatial coordinated information of target object.
In order to obtain good Stereo matching accuracy, the calculation amount during acquisition parallax is usually very big.Currently, city
Binocular vision system majority on face is handled image and is calculated using server.But with the hair of technology
Exhibition and progress, the picture quality and resolution ratio obtained by imaging device is also higher and higher, such as 720P, 1080P, 4K resolution ratio
High-definition image can be found everywhere, and makes to use Stereo Matching Algorithm data to be treated more and more, keeps processing speed slack-off.And
And since server is usually that the serial processing mode used carries out Stereo matching, thus further reduce processing
Speed.
Processing speed in order to solve the problems, such as Stereo Matching Algorithm is slack-off, patrols in the prior art usually using programmable
Embedded platforms such as device (Field Programmable Gate Array, FPGA) are collected to be handled.However, due to FPGA
It generally is suitable for doing integer calculations, so in disparity map acquisition process, the problems such as there are precision loss, this makes the essence of disparity map
It spends lower.
In consideration of it, how effectively to improve the disparity map precision obtained based on FPGA platform become one it is urgently to be resolved
Technical problem.
Summary of the invention
The present invention provides the method, apparatus and storage medium that disparity map is obtained based on FPGA, to solve in the prior art
The lower technical problem of the precision of the disparity map of existing acquisition.
In a first aspect, in order to solve the above technical problems, a kind of FPGA provided in an embodiment of the present invention obtains the side of disparity map
Method is applied to programmable logic device FPGA, and the technical solution of this method is as follows:
In setting disparity range, is calculated, obtained with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously
Obtain the corresponding integer disparity value of smallest match cost of each pair of match point in the left mesh figure and the right mesh figure；Wherein, institute
Stating integer disparity value is a setting parallax value in the setting disparity range；
It is discrete by setting accuracy progress between two adjacent parallax values of the integer disparity value with linear interpolation method
Change, and calculate the corresponding small several levels matching cost of each parallax interpolation, by the corresponding small several levels matching cost of all parallax interpolation
In, sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point；Wherein,
The setting accuracy is inversely proportional with 2 n times side, and n is in FPGA for storing decimal digits according to the data bits used, the phase
Two adjacent parallax values are the two setting parallax values in the setting disparity range；
The disparity map that the sub-pixel disparity value of all match points is constituted, the sub- picture as the left mesh figure and right mesh figure
The disparity map of plain grade.
By being carried out with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously in setting disparity range
Match, obtains the corresponding integer disparity value of smallest match cost of each pair of match point in left mesh figure and right mesh figure；And it is inserted with linear
Value method carries out discretization by setting accuracy between two adjacent parallax values of integer disparity value, and calculates each parallax and insert
It is worth corresponding small several levels matching cost, by the corresponding small several levels matching cost of all parallax interpolation, the smallest small several levels are matched
Sub-pixel disparity value of the corresponding parallax interpolation of cost as each pair of match point；Wherein, setting accuracy with 2 n times side at anti-
Than n is for storing decimal digits according to the data bits used in FPGA, and two adjacent parallax values are in setting disparity range
Interior setting parallax value；The disparity map that the sub-pixel disparity values of all match points is constituted, as left mesh figure and right mesh figure
The disparity map of sub-pixel.Due to after calculating the integer disparity value of each pair of sampled point, with linear interpolation method to each whole
Discretization is carried out by setting accuracy between two adjacent parallaxes of several levels parallax value, realizes the fixed point to sub-pixel disparity value
Processing, and the corresponding small several levels matching cost of each parallax interpolation is calculated, generation is matched from the corresponding small several levels of all parallax interpolation
The smallest small several levels matching cost is found out in valence, using the corresponding parallax interpolation of the smallest small several levels matching cost as each pair of matching
The sub-pixel disparity value of point, to improve the disparity map precision of acquisition.
Optionally, it in setting disparity range, is carried out with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously
It calculates, obtains the corresponding integer disparity value of smallest match cost of each pair of match point in the left mesh figure and the right mesh figure,
Include:
Census transformation is carried out to left mesh figure and right mesh figure respectively, obtains the Census of the left mesh figure and the right mesh figure
Coding；Wherein, the Census is encoded to binary coding；
Based on the Census of the left mesh figure and right mesh figure coding and the setting disparity range, the left mesh is calculated
In figure and the right mesh figure, each setting parallax value corresponding matching generation of each pair of match point in the setting disparity range
Valence；
With the victor is a king, WTA strategy is chosen described in minimum value conduct from the corresponding matching cost of all setting parallax values
Smallest match cost, and using the corresponding setting parallax value of the smallest match cost as the integer disparity value.
Optionally, with linear interpolation method, by setting accuracy between two adjacent parallax values of the integer disparity value
Discretization is carried out, and calculates the corresponding small several levels matching cost of each parallax interpolation, by the corresponding small several levels of all parallax interpolation
In matching cost, sub-pixel disparity of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point
Value, comprising:
Setting parallax value and corresponding matching cost and two adjacent parallaxes based on each pair of match point
Value and corresponding matching cost construct the functional relation of the parallax value and matching cost between two adjacent parallax values；
Discretization interpolation is carried out between two adjacent parallax values according to the setting accuracy, is obtained described adjacent
Two parallax values between multiple parallax interpolation；
Based on each parallax interpolation and the functional relation, obtains the corresponding small several levels of each parallax interpolation and match generation
Valence；
The smallest small several levels matching cost is found out from the corresponding small several levels matching cost of all parallax interpolation, and will be described
The corresponding parallax interpolation of the smallest small several levels matching cost, the sub-pixel disparity value as each match point.
Optionally, setting parallax value and corresponding matching cost based on each pair of match point and described adjacent
Two parallax values and corresponding matching cost construct the letter of the parallax value and matching cost between two adjacent parallax values
Number relationship, comprising:
If the functional relation is set as linear function formula, x is the linear function formula independent variable, and y is the linear letter
Numerical expression dependent variable；Wherein, the coefficient in the linear function formula is unknown number to be solved；
By the setting parallax value of each pair of match point and corresponding matching cost and two adjacent parallax values
And corresponding matching cost, respectively as the independent variable of the linear function, the value of dependent variable, in test case linear function
Coefficient solved, obtain the coefficient value in the linear function；
The coefficient in the linear function formula is replaced with the coefficient value, is built into the parallax of the known sub-pixel
The functional relation of value and small several levels matching cost.
Optionally, the linear function formula is specially parabolical functional expression.
Optionally, it is based on each parallax interpolation and the functional relation, obtains the corresponding decimal of each parallax interpolation
Grade matching cost, comprising:
Derivation is carried out to the parabolical functional expression, obtains derivative function relational expression；
Each parallax interpolation is substituted into the derivative function relational expression and is solved, each parallax is obtained and inserts
It is worth corresponding small several levels matching cost.
Second aspect, the embodiment of the invention provides a kind of device for obtaining disparity map based on FPGA, which includes:
Matching unit, for setting disparity range in, for Stereo Matching Algorithm to simultaneously acquisition left mesh figure and
Right mesh figure is calculated, and the corresponding integer of smallest match cost of each pair of match point in the left mesh figure and the right mesh figure is obtained
Grade parallax value；Wherein, the integer disparity value is a setting parallax value in the setting disparity range；
Interpolating unit, for using linear interpolation method, by setting essence between two adjacent parallax values of integer disparity value
Degree carries out discretization, and calculates the corresponding small several levels matching cost of each parallax interpolation, by the corresponding decimal of all parallax interpolation
In grade matching cost, the corresponding parallax interpolation of the smallest small several levels matching cost is regarded as the sub-pixel of each match point
Difference；Wherein, the setting accuracy is inversely proportional with 2 n times side, for storing decimal digits according to using in the n FPGA
Data bits, two adjacent parallax values are two setting parallax values in the setting disparity range by all matchings
The disparity map that the sub-pixel disparity value of point is constituted, the disparity map as the left mesh figure and the sub-pixel of right mesh figure.
Optionally, the matching unit is specifically used for:
Census transformation is carried out to left mesh figure and right mesh figure respectively, obtains the Census of the left mesh figure and the right mesh figure
Coding；Wherein, the Census is encoded to binary coding；
Based on the Census of the left mesh figure and right mesh figure coding and the setting disparity range, the left mesh is calculated
In figure and the right mesh figure, each setting parallax value corresponding matching generation of each pair of match point in the setting disparity range
Valence；
With the victor is a king, WTA strategy is chosen described in minimum value conduct from the corresponding matching cost of all setting parallax values
Smallest match cost, and using the corresponding setting parallax value of the smallest match cost as the integer disparity value.
Optionally, the interpolating unit is specifically used for:
Setting parallax value and corresponding matching cost and two adjacent parallaxes based on each pair of match point
Value and corresponding matching cost construct the functional relation of the parallax value and matching cost between two adjacent parallax values；
Discretization interpolation is carried out between two adjacent parallax values according to the setting accuracy, is obtained described adjacent
Two parallax values between multiple parallax interpolation；
Based on each parallax interpolation and the functional relation, obtains the corresponding small several levels of each parallax interpolation and match generation
Valence；
The smallest small several levels matching cost is found out from the corresponding small several levels matching cost of all parallax interpolation, and will be described
The corresponding parallax interpolation of the smallest small several levels matching cost, the sub-pixel disparity value as each match point.
Optionally, the interpolating unit is also used to:
If the functional relation is set as linear function formula, x is the linear function formula independent variable, and y is the linear letter
Numerical expression dependent variable；Wherein, the coefficient in the linear function formula is unknown number to be solved；
By the setting parallax value of each pair of match point and corresponding matching cost and two adjacent parallax values
And corresponding matching cost, respectively as the independent variable of the linear function, the value of dependent variable, in test case linear function
Coefficient solved, obtain the coefficient value in the linear function；
The coefficient in the linear function formula is replaced with the coefficient value, is built into the parallax of the known sub-pixel
The functional relation of value and small several levels matching cost.
Optionally, the linear function formula is specially parabolical functional expression.
Optionally, the interpolating unit is also used to:
Derivation is carried out to the parabolical functional expression, obtains derivative function relational expression；
Each parallax interpolation is substituted into the derivative function relational expression and is solved, each parallax is obtained and inserts
It is worth corresponding small several levels matching cost.
The technical solution in said one or multiple embodiments through the embodiment of the present invention, the embodiment of the present invention at least have
There is following technical effect:
In embodiment provided by the invention, by setting disparity range, with Stereo Matching Algorithm to acquiring simultaneously
Left mesh figure and right mesh figure matched, the smallest match cost for obtaining each pair of match point in left mesh figure and right mesh figure is corresponding whole
Several levels parallax value；And with linear interpolation method, between two adjacent parallax values of integer disparity value by setting accuracy carry out from
Dispersion, and the corresponding small several levels matching cost of each parallax interpolation is calculated, the corresponding small several levels of all parallax interpolation are matched into generation
In valence, sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each pair of match point；Wherein, if
The n times side for determining precision with 2 is inversely proportional, and n is in FPGA for storing decimal digits according to the data bits used, two adjacent views
Difference is the setting parallax value in setting disparity range；The disparity map that the sub-pixel disparity value of all match points is constituted,
Disparity map as left mesh figure and the sub-pixel of right mesh figure.Due to after calculating the integer disparity value of each pair of sampled point,
Discretization is carried out by setting accuracy between linear interpolation method two parallaxes adjacent to each integer disparity value, is realized to Asia
The fixed point of Pixel-level parallax value is handled, and calculates the corresponding small several levels matching cost of each parallax interpolation, is inserted from all parallaxes
It is worth in corresponding small several levels matching cost and finds out the smallest small several levels matching cost, the smallest small several levels matching cost is corresponding
Sub-pixel disparity value of the parallax interpolation as each pair of match point, to improve the disparity map precision of acquisition.
Detailed description of the invention
Fig. 1 is a kind of flow chart that parallax drawing method is obtained based on FPGA provided in an embodiment of the present invention；
Fig. 2 is that the hardware description language of the sub-pixel disparity value provided in an embodiment of the present invention for obtaining each pair of match point shows
It is intended to；
Fig. 3 is a kind of structural schematic diagram that parallax map device is obtained based on FPGA provided in an embodiment of the present invention.
Specific embodiment
Implementation column of the present invention provides the method, apparatus and storage medium that disparity map is obtained based on FPGA, to solve existing skill
The lower technical problem of the precision of the disparity map of acquisition present in art.
In order to solve the above technical problems, general thought is as follows for technical solution in the embodiment of the present application:
There is provided a kind of method that disparity map is obtained based on FPGA, comprising: in setting disparity range, use Stereo Matching Algorithm
The left mesh figure and right mesh figure of acquisition simultaneously are calculated, the smallest match generation of each pair of match point in left mesh figure and right mesh figure is obtained
The corresponding integer disparity value of valence；Wherein, integer disparity value is the setting parallax value set in disparity range；With linear
Interpolation method carries out discretization by setting accuracy between two adjacent parallax values of the integer disparity value, and calculates each
The corresponding small several levels matching cost of parallax interpolation, by the corresponding small several levels matching cost of all parallax interpolation, the smallest decimal
Sub-pixel disparity value of the corresponding parallax interpolation of grade matching cost as each match point；Wherein, setting accuracy and 2 n times
Side is inversely proportional, and n is for storing decimal digits according to the data bits used in FPGA, and two adjacent parallax values are to regard in setting
Two setting parallax values in poor range；The disparity map that the sub-pixel disparity value of all match points is constituted, as left mesh figure
With the disparity map of the sub-pixel of right mesh figure.
Due in the above scheme, by setting disparity range, with Stereo Matching Algorithm to the left mesh of acquisition simultaneously
Figure and right mesh figure are matched, and the corresponding integer grade view of smallest match cost of each pair of match point in left mesh figure and right mesh figure is obtained
Difference；And with linear interpolation method, discretization is carried out by setting accuracy between two adjacent parallax values of integer disparity value, and
The corresponding small several levels matching cost of each parallax interpolation is calculated, by the corresponding small several levels matching cost of all parallax interpolation, most
Sub-pixel disparity value of the small corresponding parallax interpolation of small several levels matching cost as each pair of match point；Wherein, setting accuracy
N times side with 2 is inversely proportional, and n is for storing decimal digits according to the data bits used in FPGA, and two adjacent parallax values are
Setting parallax value in setting disparity range；The disparity map that the sub-pixel disparity value of all match points is constituted, as a left side
The disparity map of the sub-pixel of mesh figure and right mesh figure.Due to after calculating the integer disparity value of each pair of sampled point, with linear
Discretization is carried out by setting accuracy between interpolation method two parallaxes adjacent to each integer disparity value, is realized to sub-pixel
The fixed point of parallax value is handled, and calculates the corresponding small several levels matching cost of each parallax interpolation, corresponding from all parallax interpolation
Small several levels matching cost in find out the smallest small several levels matching cost, the corresponding parallax of the smallest small several levels matching cost is inserted
It is worth the sub-pixel disparity value as each pair of match point, to improve the disparity map precision of acquisition.
In order to better understand the above technical scheme, below by attached drawing and specific embodiment to technical solution of the present invention
It is described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the detailed of technical solution of the present invention
Thin explanation, rather than the restriction to technical solution of the present invention, in the absence of conflict, the embodiment of the present invention and embodiment
In technical characteristic can be combined with each other.
Referring to FIG. 1, the embodiment of the present invention, which provides one kind, obtains parallax drawing method, the treatment process of this method based on FPGA
It is as follows.
Step 101: in setting disparity range, being carried out with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously
It calculates, obtains the corresponding integer disparity value of smallest match cost of each pair of match point in left mesh figure and right mesh figure；Wherein, integer
Grade parallax value is the setting parallax value set in disparity range.
Specifically, being carried out in setting disparity range with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously
It calculates, obtains the corresponding integer disparity value of smallest match cost of each pair of match point in left mesh figure and right mesh figure, can use
Following manner is calculated:
Census transformation first is carried out to left mesh figure and right mesh figure respectively, obtains the Census coding of left mesh figure and right mesh figure；
Wherein, Census is encoded to binary coding；Disparity range, meter are encoded and set again based on the Census of left mesh figure and right mesh figure
Calculate each setting parallax value corresponding matching cost of each pair of match point in setting disparity range in left mesh figure and right mesh figure.
For example, it for example can be 5 × 5 that the neighborhood form that uses of Census transformation, which be M × M() square sliding window,
The then calculation formula that the Census of left mesh figure and right mesh figure coding uses are as follows:
Wherein, L_CT(i, j) encoded for the Census of left mesh figure, also referred to as left code pattern, R_CT(i, j) it is right mesh
The Census of figure is encoded, also referred to as right code pattern, and i, j are that the horizontal, vertical of same pixel position in left mesh figure and right mesh figure sits
Mark, n, m convert cross, the ordinate of the center pixel of the neighborhood form used, and n=m={-M/2, M/2 } for Census,For than
The connection operation by turn of special position, ξ operation are defined using following equation:
(3)
By formula (1), (2) by the pixel value in each matching neighborhood of a point window of left mesh figure and right mesh figure,
The Census coding of binary data expression is converted to, later, matching cost calculation method can be used to calculate, left mesh figure, the right side
Matching cost of the Census encoded radio of corresponding two pixels of mesh figure in setting disparity range.Using matching cost as Hamming
(Hamming) for distance, the specific calculation formula of Hamming distance are as follows:
(4)
Wherein, Cost(i, j, d) be matching cost matrix, i, j be left mesh figure, in right mesh figure pixel transverse and longitudinal coordinate, d
It for setting parallax value and is integer, the value range of d is setting disparity range { 1,2,3 ..., DSR }, and DSR is the maximum of setting
Parallax value, Hamming are Hamming calculating.
By using formula (4), each setting parallax value of each pair of match point in setting disparity range can be calculated
Corresponding Hamming distance, since Hamming distance is the similarity for characterizing two images, so, smallest hamming distance is corresponding
Setting parallax value, the parallax value in left mesh figure as to be requested and right mesh figure between Corresponding matching point.
Specifically, finding corresponding smallest match cost in setting disparity range for each pair of match point, victor can be used
It chooses minimum value from the corresponding matching cost of all setting parallax values for king (Winner Takes A11, WTA) strategy and makees
For smallest match cost.And using the corresponding setting parallax value of smallest match cost as the integer disparity value of Corresponding matching point.
In the same way, other respective integer disparities of match point in available left mesh figure and right mesh figure.
In obtaining left mesh figure and right mesh figure after each pair of respective integer disparity of match point, step 102 can be executed.
Step 102: using linear interpolation method, carried out between two adjacent parallax values of integer disparity value by setting accuracy
Discretization, and the corresponding small several levels matching cost of each parallax interpolation is calculated, the corresponding small several levels of all parallax interpolation are matched
In cost, sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point；Wherein,
Setting accuracy is inversely proportional with 2 n times side, and n is adjacent two for storing decimal digits according to the data bits used in FPGA
Parallax value is two setting parallax values in setting disparity range.
Specifically, sub-pixel disparity value can be calculated in the following ways:
Firstly, setting parallax value and corresponding matching cost and integer disparity value based on each pair of match point are adjacent
Two parallax values and corresponding matching cost, parallax value between adjacent two parallax values of building integer disparity value with
Functional relation with cost.
The functional relation of parallax value and matching cost between two adjacent parallax values of specific building integer disparity value
It can be in the following ways:
If functional relation is set as linear function formula, x is linear function formula independent variable, and y is linear function formula dependent variable；Its
In, the coefficient in linear function formula is unknown number to be solved；Then, by the setting parallax value of each pair of match point and corresponding
With cost and integer disparity value adjacent two parallax values and corresponding matching cost, respectively as linear function from
The value of variable, dependent variable solves the coefficient in test case linear function, obtains the coefficient value in linear function；Most
Afterwards, with the coefficient in coefficient value replacement linear function formula, the parallax value for being built into known sub-pixel matches generation with small several levels
The functional relation of valence.
Preferably, linear function formula is parabolical functional expression.
For example, linear function formula is parabolical functional expression, then the linear function formula can be expressed as y=ax2+ bx+c,
In, x is independent variable, for representing parallax interpolation；Y is dependent variable, and for representing corresponding matching cost, a, b, c are linear letter
Coefficient in numerical expression.At this point, a, b, c are unknown number.
The integer disparity value d that each pair of match point can be obtained according to step 101, in setting disparity range, each pair of
Two adjacent parallax values of integer disparity value d with point are respectively d-1 and d+1, can calculate d, d- according to formula (4)
1, d+1 corresponding matching cost value Cost1, Cost2, Cost3；
Here y=ax is chosen2+ bx+c is used as linear equation, according to integer disparity value d and corresponding two adjacent views
Difference d-1, d+1 and their matching cost value Cost1, Cost2, Cost3 may be constructed three interpolation points, be respectively as follows: (d-1,
Cost2), these three interpolation points are substituted into linear equation the value for calculating coefficient a, b by (d, Cost1), (d+1, Cost3):
(5)
(6)
In FPGA, when carrying out multiplication or division arithmetic, if multiplicand or dividend are 2 integral multiples, using shifting
Bit arithmetic is calculated, and is not only easy to realize in this way, and can be not take up the resource of FPGA.If multiplicand or dividend are not
2 integral multiple then needs to call multiplier or divider, and then needs to occupy certain resource using multiplier or divider, and
The quantity of multiplier and divider is limited in FPGA, if the number for carrying out multiplication or division arithmetic is excessive, be will lead to and is multiplied
Musical instruments used in a Buddhist or Taoist mass, divider not enough using calculating speed is reduced in turn, so according to formula (5), (6) it is found that the use of linear function formula being to throw
When the functional expression design factor of object line, multiplication operation need to be only used, other is displacement or signed magnitude arithmetic(al), and then can be had
Effect ground reduces the occupancy to FPGA resource.
It should be noted that the reason of only calculating a, b coefficient in parabolical functional expression here without design factor c exists
It is described later, wouldn't explain herein.Due to only needing the value of calculating section coefficient, institute when calculating parabolical functional expression
Can effectively reduce calculating process, to reduce the resource occupation to FPGA.
Since in parabolical functional expression, the corresponding derivative of the minimum value of parabolical functional expression is zero, and parabola
Functional expression in dependent variable y represents is matching cost, therefore smallest match cost can be by the derivative of parabolical functional expression
Determine, y=| 2ax+b |, by carrying out derivation to parabolical functional expression, it may not be necessary to carry out complicated operation, a demand take y=
| 2ax+b | corresponding x value when minimum can determine the sub-pixel disparity value of corresponding each match point, to reduce calculating
The complexity of smallest match cost.
Secondly, carrying out discretization interpolation between two adjacent parallax values according to setting accuracy, adjacent two are obtained
Multiple parallax interpolation between parallax value.
If the data bits of decimal place is to indicate with n in FPGA, that setting accuracy is 1/2n, according to the think of of sampling
Think, between two adjacent parallaxes of integer disparity value d (d-1, d+1), by setting accuracy 1/2nTo linear function formula y=ax2+
Bx+c is sampled, and is equivalent between two adjacent parallaxes between (d-1, d+1) according to setting accuracy 1/2nIt carries out between waiting
Every interpolation, multiple parallax interpolation { d-1, d-1+1/2 are obtainedn, d-1+2/2n..., d-1+2n+1/2n }。
In FPGA, 1/2n~2n+1/2nValue can be obtained from specified address with the mode tabled look-up, refer to table 1.
Table 1
Again, it is based on each parallax interpolation and functional relation, obtains the corresponding small several levels matching cost of each parallax interpolation.
Specifically, being first to carry out derivation to parabolical functional expression, corresponding derivative function relational expression is obtained, then again by each parallax
Interpolation is substituted into derivative function relational expression and is solved, and obtains the corresponding small several levels matching cost of each parallax interpolation.
Since progress multiplication or division arithmetic need to occupy certain resource in FPGA, then multiplication or division arithmetic are carried out
When need multiplier to be used, limited amount of the divider in FPGA, so, in order to which to calculate each parallax value corresponding reducing
Use of the small several levels matching cost to multiplier or divider, in embodiments of the present invention, first to parabolical functional expression into
Row derivation obtains corresponding derivative function relational expression, and calculates the corresponding decimal of each parallax value using derivative function relational expression
Grade matching cost, may not necessarily not only calculate whole coefficients in functional relation, but also can reduce the use of multiplier in this way,
To effectively reduce the occupancy to FPGA resource.
For example, all calculate tri- coefficients of a, b, c of parabolical functional expression according to conventional calculation,
Each parallax interpolation is substituted into parabolical functional expression again afterwards and calculates corresponding small several levels parallax value, then is also needed parabola
Functional expression in coefficient c calculate, the expression formula of calculated coefficient c are as follows:
(7)
As can be seen that calculate the value of coefficient c from formula (7), at least need to increase by 3 multiplyings, calculate a,
B, the value of tri- coefficients of c is then needed using multiple multipliers, if each parallax value is substituted into calculating pair in parabolical functional expression
The small several levels matching cost answered then often calculates one small several levels matching cost, needs using 4 multipliers and 2 adders.
It is calculated according to the embodiment passed through in the embodiment of the present invention, due to being to need to only use parabolical function
The corresponding derivative function relational expression of formula calculates the corresponding small several levels matching cost of each parallax interpolation, so need to only calculate a, b two
The value of a coefficient, and this need to use a multiplier, in the corresponding small several levels matching cost of each parallax interpolation of calculating, often
Secondary calculating only needs only with 1 multiplier and an adder.
Obviously, using method provided in an embodiment of the present invention, the corresponding small several levels parallax value of each parallax interpolation is being calculated
When, the quantity of the required multiplier used and adder is fewer than the quantity of the conventionally calculation mode multiplier used and adder,
So method provided in an embodiment of the present invention can effectively reduce the occupancy to FPGA resource.
By multiple parallax interpolation { d-1, d-1+1/2n, d-1+2/2n..., d-1+2n+1/2nSubstitute into the hope of coefficient throwing
In the derivative function relational expression of the functional expression of object line, the corresponding matching cost of each parallax interpolation can be obtained.
Finally, find out the smallest matching cost from the corresponding matching cost of all parallax interpolation, and by the smallest matching
The corresponding parallax interpolation of cost, the sub-pixel disparity value as each match point.
Fig. 2 is referred to, the Hardware description language of the sub-pixel disparity value of each pair of match point is calculated for the embodiment of the present invention
Schematic diagram address 0 ~ address n of speech is 1 ~ address of address n in table 1, and the data that their the insides store are corresponding decimal in table 1
Position data ,/data that the input terminal of multiplier is connected are added to obtain plus/minus with the data on input terminal data line/multiplies with plus/minus
The data of the output end of musical instruments used in a Buddhist or Taoist mass, comparator are used to for the smaller in the data of two input terminals being output to the output of comparator
It holds, " taking just " on comparator output terminal data line, which represents, takes its positive value for the data that comparator exports, and y0 ~ yn represents each view
The corresponding small several levels matching cost of poor interpolation, yminFor the minimum value in y0 ~ yn, yminCorresponding input address is 0 ~ address of address
2n+1In with yminIt is worth corresponding address, from figure 2 it can be seen that 1 multiplier need to be only used when calculating each parallax interpolation,
Also, due to the concurrent operations that can carry out multithreading in FPGA, so y0 ~ yn can be calculated in the same time, from
And it can quickly calculate the sub-pixel disparity value of each pair of match point.
After the sub-pixel disparity value for obtaining each match point, step 103 can be executed.
Step 103: the disparity map that the sub-pixel disparity values of all match points is constituted, as left mesh figure and right mesh figure
The disparity map of sub-pixel.
Based on the same inventive concept, a kind of device being obtained disparity map based on FPGA is provided in one embodiment of the invention, it should
The specific embodiment of the poor drawing method of the acquisition of device can be found in the description of embodiment of the method part, and overlaps will not be repeated,
Fig. 3 is referred to, which includes:
Matching unit 301, for setting in disparity range, for the left mesh figure with Stereo Matching Algorithm to acquisition simultaneously
It is calculated with right mesh figure, the smallest match cost for obtaining each pair of match point in the left mesh figure and the right mesh figure is corresponding whole
Several levels parallax value；Wherein, the integer disparity value is a setting parallax value in the setting disparity range；
Interpolating unit 302, for using linear interpolation method, by setting between two adjacent parallax values of integer disparity value
Precision carries out discretization, and calculates the corresponding small several levels matching cost of each parallax interpolation, and all parallax interpolation are corresponding small
In several levels matching cost, sub-pixel of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point
Parallax value；Wherein, the setting accuracy is inversely proportional with 2 n times side, and n is in the FPGA for storing decimal digits according to using
Data bits, two adjacent parallax values be it is described setting disparity range in two setting parallax values by all
The disparity map that sub-pixel disparity value with point is constituted, the disparity map as the left mesh figure and the sub-pixel of right mesh figure.
Optionally, the matching unit 301 is specifically used for:
Census transformation is carried out to left mesh figure and right mesh figure respectively, obtains the Census of the left mesh figure and the right mesh figure
Coding；Wherein, the Census is encoded to binary coding；
Based on the Census of the left mesh figure and right mesh figure coding and the setting disparity range, the left mesh is calculated
In figure and the right mesh figure, each setting parallax value corresponding matching generation of each pair of match point in the setting disparity range
Valence；
With the victor is a king, WTA strategy is chosen described in minimum value conduct from the corresponding matching cost of all setting parallax values
Smallest match cost, and using the corresponding setting parallax value of the smallest match cost as the integer disparity value.
Optionally, the interpolating unit 302 is specifically used for:
Setting parallax value and corresponding matching cost and two adjacent parallaxes based on each pair of match point
Value and corresponding matching cost construct the functional relation of the parallax value and matching cost between two adjacent parallax values；
Discretization interpolation is carried out between two adjacent parallax values according to the setting accuracy, is obtained described adjacent
Two parallax values between multiple parallax interpolation；
Based on each parallax interpolation and the functional relation, obtains the corresponding small several levels of each parallax interpolation and match generation
Valence；
The smallest small several levels matching cost is found out from the corresponding small several levels matching cost of all parallax interpolation, and will be described
The corresponding parallax interpolation of the smallest small several levels matching cost, the sub-pixel disparity value as each match point.
Optionally, the interpolating unit 302 is also used to:
If the functional relation is set as linear function formula, x is the linear function formula independent variable, and y is the linear letter
Numerical expression dependent variable；Wherein, the coefficient in the linear function formula is unknown number to be solved；
By the setting parallax value of each pair of match point and corresponding matching cost and two adjacent parallax values
And corresponding matching cost, respectively as the independent variable of the linear function, the value of dependent variable, in test case linear function
Coefficient solved, obtain the coefficient value in the linear function；
The coefficient in the linear function formula is replaced with the coefficient value, is built into the parallax of the known sub-pixel
The functional relation of value and small several levels matching cost.
Optionally, the linear function formula is specially parabolical functional expression.
Optionally, the interpolating unit 302 is also used to:
Derivation is carried out to the parabolical functional expression, obtains derivative function relational expression；
Each parallax interpolation is substituted into the derivative function relational expression and is solved, each parallax is obtained and inserts
It is worth corresponding small several levels matching cost.
In embodiment provided by the invention, by setting disparity range, with Stereo Matching Algorithm to acquiring simultaneously
Left mesh figure and right mesh figure matched, the smallest match cost for obtaining each pair of match point in left mesh figure and right mesh figure is corresponding whole
Several levels parallax value；And with linear interpolation method, between two adjacent parallax values of integer disparity value by setting accuracy carry out from
Dispersion, and the corresponding small several levels matching cost of each parallax interpolation is calculated, the corresponding small several levels of all parallax interpolation are matched into generation
In valence, sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each pair of match point；Wherein, if
The n times side for determining precision with 2 is inversely proportional, and n is in FPGA for storing decimal digits according to the data bits used, two adjacent views
Difference is the setting parallax value in setting disparity range；The disparity map that the sub-pixel disparity value of all match points is constituted,
Disparity map as left mesh figure and the sub-pixel of right mesh figure.Due to after calculating the integer disparity value of each pair of sampled point,
Discretization is carried out by setting accuracy between linear interpolation method two parallaxes adjacent to each integer disparity value, is realized to Asia
The fixed point of Pixel-level parallax value is handled, and calculates the corresponding small several levels matching cost of each parallax interpolation, is inserted from all parallaxes
It is worth in corresponding small several levels matching cost and finds out the smallest small several levels matching cost, the smallest small several levels matching cost is corresponding
Sub-pixel disparity value of the parallax interpolation as each pair of match point, to improve the disparity map precision of acquisition.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as the production of method, system or computer program
Product.Therefore, in terms of the embodiment of the present invention can be used complete hardware embodiment, complete software embodiment or combine software and hardware
Embodiment form.Moreover, it wherein includes computer available programs generation that the embodiment of the present invention, which can be used in one or more,
The meter implemented in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of code
The form of calculation machine program product.
The embodiment of the present invention be referring to according to the method for the embodiment of the present invention, equipment (system) and computer program product
Flowchart and/or the block diagram describe.It should be understood that can be realized by computer program instructions in flowchart and/or the block diagram
The combination of process and/or box in each flow and/or block and flowchart and/or the block diagram.It can provide these calculating
Processing of the machine program instruction to general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices
Device is to generate a machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute
For realizing the function of being specified in one or more flows of the flowchart and/or one or more blocks of the block diagram
Device.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. the method for obtaining disparity map based on FPGA characterized by comprising
In setting disparity range, is calculated with left mesh figure and right mesh figure of the Stereo Matching Algorithm to acquisition simultaneously, obtain institute
State the corresponding integer disparity value of smallest match cost of each pair of match point in left mesh figure and the right mesh figure；Wherein, described whole
Several levels parallax value is a setting parallax value in the setting disparity range；
With linear interpolation method, discretization is carried out by setting accuracy between two adjacent parallax values of the integer disparity value,
And the corresponding small several levels matching cost of each parallax interpolation is calculated, by the corresponding small several levels matching cost of all parallax interpolation,
Sub-pixel disparity value of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point；Wherein, institute
The n times side that setting accuracy is stated with 2 is inversely proportional, and n is to be used to store decimal digits in FPGA according to the data bits used, described adjacent
Two parallax values be it is described setting disparity range in two setting parallax values；
The disparity map that the sub-pixel disparity value of all match points is constituted, the sub-pixel as the left mesh figure and right mesh figure
Disparity map；
Wherein, the corresponding small several levels matching cost of each parallax interpolation is calculated in the following ways:
The functional relation between the parallax value and matching cost between two adjacent parallax values of the integer disparity value is constructed,
Wherein, the functional relation is parabolical functional expression；
Derivation is carried out to the parabolical functional expression, obtains corresponding derivative function relational expression；
Each parallax interpolation is substituted into derivative function relational expression and is solved, it is corresponding to obtain each parallax interpolation
Small several levels matching cost.
2. the method as described in claim 1, which is characterized in that in setting disparity range, with Stereo Matching Algorithm to simultaneously
The left mesh figure and right mesh figure of acquisition are calculated, and the smallest match of each pair of match point in the left mesh figure and the right mesh figure is obtained
The corresponding integer disparity value of cost, comprising:
Census transformation is carried out to left mesh figure and right mesh figure respectively, the Census for obtaining the left mesh figure and the right mesh figure is compiled
Code；Wherein, the Census is encoded to binary coding；
Based on the Census of the left mesh figure and right mesh figure coding and the setting disparity range, calculate the left mesh figure and
In the right mesh figure, each setting parallax value corresponding matching cost of each pair of match point in the setting disparity range；
With the victor is a king, WTA strategy chooses minimum value as the minimum from the corresponding matching cost of all setting parallax values
Matching cost, and using the corresponding setting parallax value of the smallest match cost as the integer disparity value.
3. the method as described in claim 1, which is characterized in that linear interpolation method is used, it is adjacent in the integer disparity value
Discretization is carried out by setting accuracy between two parallax values, and calculates the corresponding small several levels matching cost of each parallax interpolation, it will
In the corresponding small several levels matching cost of all parallax interpolation, described in the corresponding parallax interpolation of the smallest small several levels matching cost is used as
The sub-pixel disparity value of each match point, comprising:
Setting parallax value and corresponding matching cost and two adjacent parallax values based on each pair of match point and
Corresponding matching cost constructs the functional relation of the parallax value and matching cost between two adjacent parallax values；
Discretization interpolation is carried out between two adjacent parallax values according to the setting accuracy, obtains described adjacent two
Multiple parallax interpolation between a parallax value；
Based on each parallax interpolation and the functional relation, the corresponding small several levels matching cost of each parallax interpolation is obtained；
Find out the smallest small several levels matching cost from the corresponding small several levels matching cost of all parallax interpolation, and by the minimum
The corresponding parallax interpolation of small several levels matching cost, the sub-pixel disparity value as each match point.
4. method as claimed in claim 3, which is characterized in that setting parallax value based on each pair of match point and corresponding
Matching cost and adjacent two parallax values and corresponding matching cost, construct two adjacent parallax values it
Between parallax value and matching cost functional relation, comprising:
If the functional relation is set as linear function formula, x is the linear function formula independent variable, and y is the linear function formula
Dependent variable；Wherein, the coefficient in the linear function formula is unknown number to be solved；
By the setting parallax value of each pair of match point and corresponding matching cost and two adjacent parallax values and right
The matching cost answered is in test case linear function respectively as the independent variable of the linear function, the value of dependent variable
Number is solved, and the coefficient value in the linear function is obtained；
Replace the coefficient in the linear function formula with the coefficient value, be built into the parallax value of the known sub-pixel with
The functional relation of small several levels matching cost.
5. obtaining the device of binocular stereo vision disparity map, it is applied to programmable logic device FPGA characterized by comprising
Matching unit, setting disparity range in, for Stereo Matching Algorithm to simultaneously acquisition left mesh figure and right mesh figure into
Row calculates, and obtains the corresponding integer disparity of smallest match cost of each pair of match point in the left mesh figure and the right mesh figure
Value；Wherein, the integer disparity value is a setting parallax value in the setting disparity range
Interpolating unit, for use linear interpolation method, between two adjacent parallax values of integer disparity value by setting accuracy into
Row discretization, and the corresponding small several levels matching cost of each parallax interpolation is calculated, by the corresponding small several levels of all parallax interpolation
With in cost, sub-pixel disparity of the corresponding parallax interpolation of the smallest small several levels matching cost as each match point
Value；Wherein, the setting accuracy is inversely proportional with 2 n times side, and n is in the FPGA for storing decimal digits according to the number used
According to digit, two adjacent parallax values are two setting parallax values in the setting disparity range；By all matchings
The disparity map that the sub-pixel disparity value of point is constituted, the disparity map as the left mesh figure and the sub-pixel of right mesh figure；
Wherein, the interpolating unit is specifically used for:
The functional relation between the parallax value and matching cost between two adjacent parallax values of the integer disparity value is constructed,
Wherein, the functional relation is parabolical functional expression；
Derivation is carried out to the parabolical functional expression, obtains corresponding derivative function relational expression；
Each parallax interpolation is substituted into derivative function relational expression and is solved, it is corresponding to obtain each parallax interpolation
Small several levels matching cost.
6. device as claimed in claim 5, which is characterized in that the matching unit is specifically used for:
Census transformation is carried out to left mesh figure and right mesh figure respectively, the Census for obtaining the left mesh figure and the right mesh figure is compiled
Code；Wherein, the Census is encoded to binary coding；
Based on the Census of the left mesh figure and right mesh figure coding and the setting disparity range, calculate the left mesh figure and
In the right mesh figure, each setting parallax value corresponding matching cost of each pair of match point in the setting disparity range；
With the victor is a king, WTA strategy chooses minimum value as the minimum from the corresponding matching cost of all setting parallax values
Matching cost, and using the corresponding setting parallax value of the smallest match cost as the integer disparity value.
7. device as claimed in claim 5, which is characterized in that the interpolating unit is specifically used for:
Setting parallax value and corresponding matching cost and two adjacent parallax values based on each pair of match point and
Corresponding matching cost constructs the functional relation of the parallax value and matching cost between two adjacent parallax values；
Discretization interpolation is carried out between two adjacent parallax values according to the setting accuracy, obtains described adjacent two
Multiple parallax interpolation between a parallax value；
Based on each parallax interpolation and the functional relation, the corresponding small several levels matching cost of each parallax interpolation is obtained；
Find out the smallest small several levels matching cost from the corresponding small several levels matching cost of all parallax interpolation, and by the minimum
The corresponding parallax interpolation of small several levels matching cost, the sub-pixel disparity value as each match point.
8. device as claimed in claim 7, which is characterized in that the interpolating unit is also used to:
If the functional relation is set as linear function formula, x is the linear function formula independent variable, and y is the linear function formula
Dependent variable；Wherein, the coefficient in the linear function formula is unknown number to be solved；
By the setting parallax value of each pair of match point and corresponding matching cost and two adjacent parallax values and right
The matching cost answered is in test case linear function respectively as the independent variable of the linear function, the value of dependent variable
Number is solved, and the coefficient value in the linear function is obtained；
Replace the coefficient in the linear function formula with the coefficient value, be built into the parallax value of the known sub-pixel with
The functional relation of small several levels matching cost.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080101388A (en) * | 2007-05-17 | 2008-11-21 | (주)코아정보시스템 | A face detection algorithm based on a new modified census transform |
| CN101841730A (en) * | 2010-05-28 | 2010-09-22 | 浙江大学 | Real-time stereoscopic vision implementation method based on FPGA |
| CN103366354A (en) * | 2012-03-27 | 2013-10-23 | 富士通株式会社 | Method and system for stereo matching |
| CN106525004A (en) * | 2016-11-09 | 2017-03-22 | 人加智能机器人技术（北京）有限公司 | Binocular stereo vision system and depth measuring method |
| CN108322725A (en) * | 2018-02-28 | 2018-07-24 | 哈尔滨理工大学 | A kind of vision fusion method based on FPGA |
-
2019
- 2019-01-31 CN CN201910095329.3A patent/CN109509218B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080101388A (en) * | 2007-05-17 | 2008-11-21 | (주)코아정보시스템 | A face detection algorithm based on a new modified census transform |
| CN101841730A (en) * | 2010-05-28 | 2010-09-22 | 浙江大学 | Real-time stereoscopic vision implementation method based on FPGA |
| CN103366354A (en) * | 2012-03-27 | 2013-10-23 | 富士通株式会社 | Method and system for stereo matching |
| CN106525004A (en) * | 2016-11-09 | 2017-03-22 | 人加智能机器人技术（北京）有限公司 | Binocular stereo vision system and depth measuring method |
| CN108322725A (en) * | 2018-02-28 | 2018-07-24 | 哈尔滨理工大学 | A kind of vision fusion method based on FPGA |
Non-Patent Citations (2)
| Title |
|---|
| Accurate hardware-based stereo vision;Kristian Ambrosch等;《Computer Vision and Image Understanding》;20100811;第1303-1316页 * |
| 计算机视觉中深度信息估计算法的研究;马利;《中国博士论文全文数据库》;20180715;摘要，正文第45-68页 * |
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