CN109495209B - Bit interleaving and de-interleaving method and device - Google Patents
Bit interleaving and de-interleaving method and device Download PDFInfo
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- CN109495209B CN109495209B CN201710814404.8A CN201710814404A CN109495209B CN 109495209 B CN109495209 B CN 109495209B CN 201710814404 A CN201710814404 A CN 201710814404A CN 109495209 B CN109495209 B CN 109495209B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention provides a bit interleaving and de-interleaving method and a device, wherein the bit interleaving method is applied to a transmitting end and comprises the following steps: when a predetermined condition is satisfied, bit interleaving is performed. The invention solves the technical problem of low interleaving efficiency in the related technology.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method and an apparatus for bit interleaving and bit deinterleaving.
Background
Interleavers play a crucial role in communication systems, and their main role is to change the order of elements in an input data sequence to maximize the correlation between elements to spread out errors that may occur. The role of the interleaver is particularly important in high order modulation. The traditional rectangular interleaver is a global interleaver, the interleaving depth varies with the length of the sequence input to the interleaver, and the longer the interleaved sequence, the larger the delay.
In an Amplitude Modulation system, each bit in a Modulation symbol has different protection capability, and taking 16QAM (Quadrature Amplitude Modulation) as an example, it is assumed that the bit in each symbol is represented as { b }0,b1,b2,b3Then { b }0,b1The protective capability of the device is larger than that of b2,b3High (or low error probability). In the related art, in Polar code coding and decoding systems used in NR (new radio access technology), received data with different reliabilities or log-likelihood ratio LLR (log-like radio) also have a great influence on decoding performance, and how to adopt an efficient interleaving manner in an NR system has not been solved at present.
In view of the above problems in the related art, no effective solution has been found at present.
Disclosure of Invention
The embodiment of the invention provides a bit interleaving method and a bit de-interleaving method and a bit interleaving device, which are used for at least solving the technical problem of low interleaving efficiency in the related technology.
According to an embodiment of the present invention, there is provided a bit interleaving method including: performing bit interleaving when a specified condition is satisfied, wherein the specified condition comprises at least one of:
a mode of operation of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
a length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
a modulation coding, MCS, level of the information bit sequence;
the aggregation level of the control channel unit carrying the information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of the information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying the information bit sequence;
a carrier frequency carrying the sequence of information bits.
The information bit sequence described in the present invention is the bit sequence that needs to be input into the interleaver.
According to an embodiment of the present invention, there is provided a bit deinterleaving method applied to a receiving end, including: receiving a matrix array to be deinterleaved; reading a sequence of bits in columns in the matrix array; and deinterleaving bits in each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol.
According to another embodiment of the present invention, there is provided a bit interleaving apparatus including: an interleaving module, configured to perform bit interleaving when a specified condition is met, where the specified condition includes at least one of:
a mode of operation of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
a length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
a modulation coding, MCS, level of the information bit sequence;
carrying the aggregation level of the Control Channel Element (CCE) of the information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of the information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying the information bit sequence;
a carrier frequency carrying the sequence of information bits.
According to another embodiment of the present invention, there is provided a bit deinterleaving apparatus including: a receiving module, configured to receive a matrix array to be deinterleaved; a reading module for reading a bit sequence by columns in the matrix array; and a deinterleaving module, configured to deinterleave bits in each modulation symbol in the matrix array, where each column of the matrix array corresponds to at most one modulation symbol.
According to still another embodiment of the present invention, there is also provided a storage medium. The storage medium is configured to store program code for performing the steps of:
performing bit interleaving when a specified condition is satisfied, wherein the specified condition comprises at least one of:
a mode of operation of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
a length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
a modulation coding, MCS, level of the information bit sequence;
carrying the aggregation level of the Control Channel Element (CCE) of the information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of the information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying the information bit sequence;
a carrier frequency carrying the sequence of information bits.
According to the invention, whether bit interleaving is needed or not is determined according to specified conditions, when bit interleaving is carried out, a bit sequence to be interleaved is written into a matrix array according to columns, and bits in each modulation symbol in the matrix array are interleaved, wherein each column of the matrix array corresponds to one modulation symbol.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow chart of a method of bit interleaving according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of bit deinterleaving in accordance with an embodiment of the present invention;
fig. 3 is a block diagram of a structure of a bit interleaving apparatus according to an embodiment of the present invention;
fig. 4 is a block diagram of a structure of a bit deinterleaving apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an embodiment of the present invention using an interleaved pattern output.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example 1
In the present embodiment, a bit interleaving method is provided, and fig. 1 is a flowchart of a bit interleaving method according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:
step S102, when a specified condition is satisfied, carrying out bit interleaving, wherein the specified condition comprises at least one of the following conditions:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation and Coding Scheme (MCS) level of the information bit sequence;
an aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
a packet size of a Resource Element Group (REG) carrying an information bit sequence;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the Information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits.
In this embodiment, the information bit sequence is a bit sequence to be interleaved input to the interleaver.
In the above specified conditions, the information bit sequence is transmitted according to the working mode of the current information bit sequence, the link direction (Uplink or downlink, for example, downlink does not use interleaver, Uplink uses interleaver), the coding code rate used by the information bit sequence (for example, the code rate is higher than a certain preset value and does not use interleaver), the user equipment Type (URLLC (Low-Latency high-reliability), eMBB (enhanced Mobile internet, enhanced Mobile Broadband), mtc (massive Machine Type Communication ) user, etc.), the Channel Type (Control Channel or traffic Channel) transmitted by the information bit sequence, the application scenario of the information bit sequence, the format of the information bit sequence carried by the Control Channel (such as Physical Uplink Control Channel, abbreviated as PUCCH), long-length interleaving, and long-length interleaving, Short format non-interleaving, etc.), aggregation level of control channel unit carrying information bit sequence (e.g. interleaver is used for low aggregation level, interleaver is not used for high aggregation level), bundle size of REG carrying information bit sequence (e.g. bundle size is interleaving of 2, bundle size is non-interleaving of 6), modulation coding MCS level of information bit sequence, search space of control channel unit carrying information bit sequence (e.g. common search space is interleaving, UE specific search space is not interleaving), scrambling mode of information bit sequence (e.g. interleaving using Paging cell Radio Network Temporary Identifier (P-RNTI), system message SI-RNTI, T-RNTI (Temporary C-RNTI), scrambling information bit sequence using user service C-RNTI, non-interleaving), The method comprises the steps of determining the transmission times of an information bit sequence (an interleaver is used for initial transmission, an interleaver is not used for retransmission, and the like), a channel state CSI process corresponding to the information bit sequence, a subframe set for bearing the information bit sequence (some subframes are designated to use the interleaver and the like), a carrier frequency for bearing the information bit sequence and the like (the interleaver is not used in a high frequency band, the interleaver is used in a low frequency band, and the like), modulation coding MCS levels of the information bit sequence (for example, the interleaving is not performed on the extremely high and extremely low MCS levels, the interleaving is performed on the medium MCS level), and judging whether the interleaving is needed according to the coding rate of the information bit (for example, the interleaving is not performed on the high code rate and the low code rate, the interleaving is performed on the medium code rate, and the like). If interleaving is needed, the interleaving method proposed by the present embodiment is used.
When carrying out bit interleaving, the method comprises the following steps:
writing the bit sequence to be interleaved into a matrix array according to columns;
bits within each modulation symbol in the matrix array are interleaved, wherein each column of the matrix array corresponds to one modulation symbol.
Through the steps, whether bit interleaving is needed or not is determined according to the specified conditions, when the bit interleaving is carried out, the bit sequence to be interleaved is written into a matrix array according to columns, and bits in each modulation symbol in the matrix array are interleaved, wherein each column of the matrix array corresponds to one modulation symbol.
Alternatively, the main body of the above steps may be a base station, a terminal, an interleaver, a transmitter, etc., but is not limited thereto.
Optionally, after interleaving the bits in each modulation symbol in the matrix array, further comprising: and outputting the interleaved sequence in columns.
Optionally, the number of rows of the matrix array is m, and the number of columns is n, where m is one of: modulation order (the number of bits contained in one modulation symbol) and the maximum value of the modulation order allowed to be used by the system, wherein n is the minimum positive integer satisfying that M x n is more than or equal to M, wherein M is a preset positive integer and is the number of bits to be interleaved.
Optionally, interleaving the bits within each modulation symbol in the matrix array comprises:
s11, generating an interweaving pattern for each column of the matrix array;
s12, interleaving the bits within each modulation symbol using the interleaving pattern.
In this embodiment, generating an interleaving pattern for each column of the matrix array comprises one of:
using a specified interleaving pattern in a first column of the matrix array, and performing cyclic shift on the interleaving patterns of the other columns except the first column on the basis of the specified interleaving pattern by using a cyclic shift value;
using a specified interleaving pattern in a first column of the matrix array, and performing cyclic shift on the other columns except the first column on the basis of the previous column by using cyclic shift values;
a non-correlated interleaving pattern is used in each column of the matrix array.
In this embodiment, the cyclic shift value is one of the following: a value of the contract; the cyclic shift value of each column is represented using a specified pseudo-random sequence.
Optionally, interleaving the bits in each modulation symbol in the matrix array includes:
s21, calling a preset interweaving pattern set;
s22, selecting the interleaving pattern according to the random number indication;
s23, the traversal interleaves the bits within each modulation symbol using the selected interleaving pattern.
Alternatively, the set of interleaving patterns is arranged in a table.
Optionally, after interleaving the bits in each modulation symbol in the matrix array, the method further includes: and performing column permutation on the appointed column of the matrix array, and outputting after permutation.
Optionally, a pseudo-random sequence is generated using the assigned random number seed, and the interleaving pattern is generated using the pseudo-random sequence.
Optionally, the random number is the same as a random number used by a de-interleaving end, where the de-interleaving end is configured to receive and decode a bit sequence interleaved by columns.
In this embodiment, the pseudo-random sequence includes one of: gold sequence, PN sequence, M sequence, Golay sequence, Frank sequence, and pseudo-random sequences respectively generated by a transmitting end and a receiving end of the sequences using the same random number seed.
Optionally, the mutually unrelated interleaving patterns include: the interleaving pattern is generated by a specified pseudo-random sequence. Generating an interleaving pattern from a specified pseudo-random sequence comprises: the first value of the interleaving pattern for each column is sequentially taken out of log2(m) bits from one of the following random sequences: gold sequence, PN sequence (pseudo noise sequence), M sequence, Golay sequence, Frank sequence, pseudo random sequence generated by a random number seed assigned at the transmitting end of the sequence; wherein the interleaving pattern of each column has a corresponding relationship with the first value. Specifically, the corresponding relationship includes one of the following: an increasing relationship, a decreasing relationship.
Optionally, the interleaving pattern is a periodic pattern. For example, the first half of a sequence uses the same pattern as the second half of the sequence.
In the present embodiment, a bit deinterleaving method is provided, and fig. 2 is a flowchart of the bit deinterleaving method according to the embodiment of the present invention, and as shown in fig. 2, the flowchart includes the following steps:
step S202, receiving a matrix array to be deinterleaved;
step S204, reading bit sequences in a matrix array according to columns;
step S206, deinterleave bits in each modulation symbol in the matrix array, where each column of the matrix array corresponds to at most one modulation symbol.
Optionally, the deinterleaving the bits in each modulation symbol in the matrix array includes: generating a pseudo-random sequence appointed by a transmitting end, and obtaining an interleaving pattern according to a mode appointed by the transmitting end; or, generating a pseudo-random number array by using a specified random number seed to obtain an interleaving pattern; and de-interleaving the received data by using the interleaving pattern to recover the data which is not interleaved at the transmitting end.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 2
In this embodiment, a bit interleaving and deinterleaving apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description of the apparatus is already given and is not repeated. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 3 is a block diagram of a structure of a bit interleaving apparatus according to an embodiment of the present invention, as shown in fig. 3, the apparatus including:
an interleaving module 30, configured to perform bit interleaving when a specified condition is met, where the specified condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
a packet size of a Resource Element Group (REG) carrying an information bit sequence;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits.
The interleaving module 30 includes: a writing unit for writing the bit sequence to be interleaved into a matrix array in columns; and the interleaving unit is used for interleaving the bits in each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to one modulation symbol.
Optionally, the apparatus further comprises: and the output module is used for outputting the interleaved sequence according to columns after the interleaving module interleaves the bits in each modulation symbol in the matrix array.
Optionally, the number of rows of the matrix array is m, the number of columns is n, where m is one of the following: the modulation order and the maximum value of the modulation order allowed to be used by the system are determined, n is the minimum positive integer satisfying that M is greater than or equal to M, wherein M is a preset positive integer.
Fig. 4 is a block diagram of a structure of a bit deinterleaving apparatus according to an embodiment of the present invention, as shown in fig. 4, the apparatus including:
a receiving module 40, configured to receive a matrix array to be deinterleaved;
a reading module 42 for reading the bit sequence by columns in the matrix array;
and a de-interleaving module 44, configured to de-interleave bits in each modulation symbol in the matrix array, where each column of the matrix array corresponds to at most one modulation symbol.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Example 3
This embodiment is an alternative embodiment of the present invention, and is used to describe the present application in detail with reference to specific examples:
in this embodiment, bit interleaving is performed when a specified condition is met, the specified condition may be one or more, and optionally, according to the working mode of the current information bit sequence, the link direction (uplink or downlink, for example, downlink does not use an interleaver, uplink uses an interleaver) for transmitting the information bit sequence, the coding rate (for example, code rate higher than a certain preset value does not use an interleaver), the user equipment type (URLLC, eMBB, or mtc user and the like), the channel type (control channel or traffic channel) for transmitting the information bit sequence, the application scenario of the information bit sequence, the format of the information bit sequence carried by the control channel (for example, long format interleaving of PUCCH, short format interleaving, etc.), the aggregation level of the control channel unit carrying the information bit sequence (for example, low aggregation level uses an interleaver, a high aggregation level without using an interleaver, etc.), a bundle size of REG carrying the information bit sequence (e.g., the bundle size is 2 for interleaving and the bundle size is 6 for interleaving), a modulation coding MCS level of the information bit sequence, a search space of a control channel unit carrying the information bit sequence (e.g., a common search space is interleaved and a UE-specific search space is not interleaved), a scrambling method of the information bit sequence (e.g., an information bit sequence scrambled by using P-RNTI, SI-RNTI, and T-RNTI and an information bit sequence scrambled by using C-RNTI is not interleaved), a number of transmissions of the information bit sequence (e.g., an interleaver is used for initial transmission, an interleaver is not used for retransmission, etc.), a CSI process corresponding to the information bit sequence, a set of subframes carrying the information bit sequence (e.g., some subframes are designated to use an interleaver, etc.)), and a number of subframes, A carrier frequency and the like (the high frequency band does not use the interleaver, the low frequency band uses the interleaver and the like), a modulation coding MCS level of the information bit sequence (for example, the high and low MCS levels do not interleave, the medium MCS level does interleave), and whether interleaving is needed or not is judged according to the coding rate of the information bit (for example, the high code rate and the low code rate do not interleave, the medium code rate does interleave and the like). If interleaving is needed, the interleaving method proposed by the present invention is used.
The transmitting terminal judges whether interleaving is needed according to the working mode of the current information bit sequence, the link direction of the transmitted information bit sequence, the coding rate used by the information bit sequence, the type of user equipment, the type of a channel transmitted by the information bit sequence, the application scenario of the information bit sequence, the format of the information bit sequence carried by a control channel, the polymerization degree grade of a control channel unit carrying the information bit sequence, the search space of the control channel unit carrying the information bit sequence, the scrambling mode of the information bit sequence, the transmission times of the information bit sequence, the channel state CSI process corresponding to the information bit sequence, the subframe set carrying the information bit sequence, the carrier frequency carrying the information bit sequence and the like. If interleaving is required, the details of the implementation of the interleaver proposed by the present invention are described below.
The interleaver proposed in this embodiment is a "local" interleaver that first writes the sequence of bits to be interleaved into a rectangular interleaver in columns, such that the bits in each column are within one modulation symbol. The bits within each symbol are then interleaved. Theoretically, the closer the interleaving pattern is to the random number, the better the interleaving effect.
This embodiment proposes bit interleaving within one modulation symbol and using a pseudo-random sequence to represent the interleaving pattern, thereby achieving a complete randomization of the interleaving pattern or a close approximation to a random number. Meanwhile, the interleaver provided by the invention only performs interleaving in one symbol, the interleaving depth is small, the processing time delay is small, and the requirement of NR can be better met. The interleaving method provided by the invention comprises the following steps: the sequence to be interleaved is written into a rectangular array by columns, the bits within each modulation symbol (each column) are interleaved, and then output by columns.
Writing the sequence to be interleaved into a matrix with the number of rows M (M modulation order or the maximum value of the modulation order allowed by the system) according to columns, wherein the number of columns n of the matrix is the minimum positive integer satisfying that M is n and is more than or equal to M. The modulation order may be the number of bits carried by one modulation symbol. The matrix of this embodiment is shown as follows:
for the determination and generation of the interleaving pattern, the following modes are included:
the first method is as follows:
for each column, an interleaving pattern I is generated,
the generation of the interleaving pattern may be one of the following.
The first column (first symbol) uses a specified interleaving pattern, e.g., [ m-1m-2m-3]The remaining columns are cyclically shifted (left or right cyclically shifted) on the basis of the first or previous column by vshiftIs represented by vshiftThe value of (A) is 0 to m-1. The cyclic shift value may be a given value, e.g., starting at column 2, each column being cyclically shifted by 1 bit to the right on the basis of the previous column, etc., e.g., the interleaving pattern used for column 1 is [ m-1m-2m-3]Then the 2 nd column interleaved pattern is cyclically shifted 1 bit to the right by [ m-2m-3]。
The cyclic shift value may also be generated using a random number. The length of the sequence c is log2(m) × (n-1), and the binary representation of the shift values in column 2 is c (0), c (1),. ·, c (log2(m) -1)).
In particular, if the number of rows of the matrix is the maximum modulation order allowed to be used by the system, assuming that the modulation order actually used is m ', the interleaving pattern used in the first column may be the designated interleaving pattern minus a value greater than m'. The shift value of the remaining columns with respect to the 1 st column is vshift＝(c(0) c(1) … c(log2m-1))modm'。
The sequence generating the shift value may be a Gold sequence, a Golay sequence, an M sequence, a PN sequence, a Frank sequence, or the like, or may be calculated according to a Hash function. But also a sequence for pilot generated by the transmitting end. For Gold sequence c (n), the sum (modulo 2) of the two m-sequences x1 and x2 is used, assuming the sequence length of c (n)Degree of MPN,n＝0,1,...,MPN-1,
c(n)＝(x1(n+NC)+x2(n+NC))mod2
x1(n+31)＝(x1(n+3)+x1(n))mod2
x2(n+31)＝(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2
Wherein N isC＝1600，x1(0)＝1,x1(n)＝0,n＝1,2,...,30，
The sequence initialization may be a cell ID, ue ID, etc., or may be a specified value.
Assuming x2 uses an initialization with a cell ID of 6, the resulting Gold sequence is:
[0 1 0 0 0 0 1 0 0 0 1 1......]，
then if the shift value is represented using the generated Gold sequence using 16QAM, the shift value of the 2 nd column is 1, the shift values of the 3 rd and 4 th columns are both 0, the shift value of the 5 th column is 2, the shift value of the 6 th column is 0, the shift value of the 7 th column is 3, and so on. If the interleaving pattern of the 1 st column is designated as [ b3, b2, b1, b0], each column is cyclically shifted on the basis of the previous column from the 2 nd column, the order after the 2 nd column interleaving is [ b2, b1, b0, b3 ]. The shift values of the 3 rd column and the 4 th column are 0 and then their interleaved order is [ b2, b1, b0, b3 ]. The column 5 interleaved pattern is [ b0, b3, b2, b1], and so on.
And outputting the matrix after interleaving according to columns.
Correspondingly, after the receiving end receives the data, the receiving end also writes the received data into a matrix according to columns to generate the same Gold sequence, and the shift value of each column is obtained. For the first column, the actual coding sequence can be obtained by outputting the data in the reverse order, for the 2 nd column, the data is circularly shifted to the left by 1 bit and then output in the reverse order, and the rest is analogized in sequence.
The second method comprises the following steps:
each column uses an interleaving pattern with no association between columns. The transmitting end and the receiving end agree with a designated random number seed, the transmitting end uses the seed to generate an array formed by random numbers with the same size as the writing array, and each column in the array formed by the random numbers is an interleaving pattern. Interweaving the sequence to be interwoven by using an array formed by the random numbers; after receiving the data transmitted by the transmitting end, the receiving end also uses the appointed seed number to generate an array formed by random numbers with required length, namely, the receiving end can de-interleave (recover) the information bit sequence without interleaving. The interleaving pattern may be generated for a specified sequence. The designated sequence may be a Gold sequence, a Golay sequence, an M-sequence, a Frank sequence, or the like. For the sequence, the length of the generated sequence may be not less than the required length, or may be a specified length, and the sequence with the specified length is repeated to obtain the required pattern of the whole interleaving matrix in use. If a repeating interleaving pattern is used, the output sequence may be output in column order, or the data using the same interleaving pattern may be output in parallel in symbol or column interleaving. Fig. 5 is a schematic diagram of an output using an interleaving pattern according to an embodiment of the present invention, and as shown in fig. 5, the entire sequence is divided into 2 segments, and an interleaving pattern used in a previous segment is consistent with an interleaving pattern used in a subsequent segment, and the two segments are output in parallel. In practice, the data may be divided into more than 2 segments, each segment may be output sequentially in columns or in parallel in columns using the same interleaving pattern.
To explain the present solution in more detail. The Gold sequence generated in example 1 is still used as an example for illustration. The 1 st index in the interleaving pattern is represented by the generated Gold sequence, and the rest of the indexes are generated by the index inference, for example, the indexes are increased to m-1, and the rest of the bit positions are sorted from small to large. Assuming 16QAM is used, the 1 st value of the interleaving pattern of the 1 st column is 1, the interleaving pattern of the 1 st column is [ 1230 ], the interleaving patterns of the 2 nd and 3 rd columns are [ 0123 ], the interleaving pattern of the 4 th column is [ 2301 ], and so on.
The third method comprises the following steps:
all possible interleaving patterns are given and tabulated. Use ofThe random number indicates the interleaver pattern used for the current column. Specifically, 16QAM is taken as an example for explanation. There are 4 bits in each modulation symbol, there are 24 possibilities for bit ordering, and there are 24 elements in the table, requiring 24 indices. The length of the random number sequence to be generated is 5 × M/4, starting from the 1 st column, 5 bits are selected each time, that is, the index of the current column, and in practice, the index value is greater than 24, and at this time, the value is modulo 24 to obtain the corresponding index. For example, assume that the pseudo-random sequence generated is [ 010000100011.]Then, the index of the first column is [ 01000 ]]The corresponding decimal is 4, then the 4 th in the table is used, and so on. For example, if Quadrature Phase Shift Keying (QPSK) is taken as an example, the table of the interleaving patterns is only 2: i is0＝[0 1]And I1＝[1 0](ii) a Then the index values in the interleaving pattern table used can be represented by the binary pseudo-random sequence (the pseudo-random sequence mentioned in the first embodiment) starting from the 1 st column.
The table may also be sized to the highest modulation order allowed by the system. And (4) modulo m the interleaving pattern obtained by table lookup, wherein m is the modulation order currently used, and the interleaving pattern actually used can be obtained by removing the value larger than m.
In this embodiment, the transmitting end and the receiving end use the same random number seed. Each column uses a random number to generate an interleaving pattern.
Optionally, after intra-symbol interleaving, column permutation may also be performed on the designated columns.
Example 4
The embodiment of the invention also provides a storage medium. Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:
s1, performing bit interleaving when a predetermined condition is satisfied, wherein the predetermined condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits.
Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Optionally, in this embodiment, the processor executes, according to a program code stored in the storage medium, bit interleaving when a specified condition is satisfied, where the specified condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (16)
1. A bit interleaving method applied to a transmitting end, comprising:
performing bit interleaving when a specified condition is satisfied, wherein the specified condition comprises at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
a length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
a modulation coding, MCS, level of the information bit sequence;
carrying the aggregation level of the Control Channel Element (CCE) of the information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits;
wherein the bit interleaving comprises:
writing the bit sequence to be interleaved into a matrix array according to columns;
interleaving bits within each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol;
wherein interleaving bits within each modulation symbol in the matrix array comprises:
generating an interleaving pattern for each column of said matrix array;
interleaving bits within the modulation symbols of each column using a corresponding interleaving pattern;
wherein generating an interleaving pattern for each column of the matrix array comprises one of:
using a specified interleaving pattern in a first column of the matrix array, and performing cyclic shift on the interleaving patterns of the other columns except the first column on the basis of the specified interleaving pattern by using cyclic shift values;
using a prescribed interleaving pattern in a first column of the matrix array, and cyclically shifting the remaining columns except the first column on the basis of a previous column by using cyclic shift values;
a mutually uncorrelated interleaving pattern is used in each column of the matrix array.
2. The method of claim 1, wherein after interleaving the bits within each modulation symbol in the matrix array, the method further comprises: and outputting the interleaved sequence in columns.
3. The method of claim 1, wherein the matrix array has a number of rows m and a number of columns n, wherein m is one of: modulation order, maximum value of modulation order allowed to be used by system, n is satisfied
Wherein M is a preset positive integer and is the number of bits to be interleaved.
4. The method of claim 1, wherein the cyclic shift value is one of:
a value of the contract;
the cyclic shift value of each column is represented using a specified pseudo-random sequence.
5. The method of claim 1, wherein interleaving the bits within each modulation symbol in the matrix array comprises:
calling a preset interweaving pattern set;
indicating a current column selection interleaving pattern according to a random number;
the bits within the modulation symbols of each column are interleaved using a corresponding interleaving pattern.
6. The method of claim 1, wherein after interleaving the bits within each modulation symbol in the matrix array, the method further comprises:
and performing column permutation on a designated column of the matrix array.
7. The method of claim 5, wherein a pseudo-random sequence is generated using a specified random number seed, and wherein the pseudo-random sequence is used to generate the interleaving pattern.
8. The method of claim 1, wherein the uncorrelated interleaving patterns comprise: the interleaving pattern is generated by a specified pseudo-random sequence.
9. The method of claim 8, wherein generating the interleaving pattern from a specified pseudo-random sequence comprises:
taking logs sequentially from one of the following random sequences2(m) bits correspond to the first value of each column of the interleaving pattern: gold sequence, pseudo-random PN sequence, M sequence, M sequence, Golay sequence, Frank sequence, pseudo-random number generated by a random number assigned at the transmitting end of the sequenceA random sequence;
wherein the interleaving pattern of each column has a corresponding relationship with the first value.
10. The method of any of claims 1, 5, 8-9, wherein the interleaving pattern is a periodic pattern.
11. A bit deinterleaving method applied to a receiving end, comprising:
receiving a matrix array to be deinterleaved;
reading a sequence of bits in columns in the matrix array;
deinterleaving bits within each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol;
wherein the matrix array to be deinterleaved is obtained by performing bit interleaving when a specified condition is satisfied, wherein the specified condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits;
wherein the bit interleaving comprises:
writing the bit sequence to be interleaved into a matrix array to be interleaved according to columns;
interleaving bits in each modulation symbol in the matrix array to be interleaved, wherein each column of the matrix array to be interleaved corresponds to at most one modulation symbol;
wherein interleaving bits within each modulation symbol in the matrix array to be interleaved comprises:
generating an interleaving pattern for each column of the matrix array to be interleaved;
interleaving bits within the modulation symbols of each column using a corresponding interleaving pattern;
wherein generating an interleaving pattern for each column of the matrix array to be interleaved comprises one of:
using a specified interleaving pattern in a first column of the matrix array to be interleaved, and performing cyclic shift on the interleaving patterns of the other columns except the first column on the basis of the specified interleaving pattern by using a cyclic shift value;
using a specified interleaving pattern in a first column of the matrix array to be interleaved, and performing cyclic shift on the other columns except the first column on the basis of a previous column by using cyclic shift values;
and using a non-correlated interleaving pattern in each column of the matrix array to be interleaved.
12. The method of claim 11, wherein deinterleaving bits within each modulation symbol in the matrix array to be deinterleaved comprises:
generating a pseudo-random sequence appointed by a transmitting end, and obtaining an interleaving pattern according to a mode appointed by the transmitting end; or, generating a pseudo-random number array by using a specified random number seed to obtain an interleaving pattern;
and de-interleaving the received data by using the interleaving pattern to recover the data which is not interleaved at the transmitting end.
13. A bit interleaving apparatus, comprising:
an interleaving module, configured to perform bit interleaving when a specified condition is met, where the specified condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits;
wherein the interleaving module comprises:
a writing unit for writing the bit sequence to be interleaved into a matrix array in columns;
the interleaving unit is used for interleaving bits in each modulation symbol in the matrix array, wherein each column of the matrix array at most corresponds to one modulation symbol;
wherein interleaving bits within each modulation symbol in the matrix array comprises:
generating an interleaving pattern for each column of said matrix array;
interleaving bits within the modulation symbols of each column using a corresponding interleaving pattern;
wherein generating an interleaving pattern for each column of the matrix array comprises one of:
using a specified interleaving pattern in a first column of the matrix array, and performing cyclic shift on the interleaving patterns of the other columns except the first column on the basis of the specified interleaving pattern by using cyclic shift values;
using a prescribed interleaving pattern in a first column of the matrix array, and cyclically shifting the remaining columns except the first column on the basis of a previous column by using cyclic shift values;
a mutually uncorrelated interleaving pattern is used in each column of the matrix array.
14. A bit deinterleaving apparatus, comprising:
a receiving module, configured to receive a matrix array to be deinterleaved;
a reading module for reading a bit sequence by columns in the matrix array;
a de-interleaving module, configured to de-interleave bits in each modulation symbol in the matrix array, where each column of the matrix array corresponds to at most one modulation symbol;
wherein the matrix array to be deinterleaved is obtained by performing bit interleaving when a specified condition is satisfied, wherein the specified condition includes at least one of:
the working mode of the information bit sequence;
an application scenario of the information bit sequence;
a link direction of the information bit sequence;
the length of the information bit sequence;
the length of a mother code corresponding to the information bit sequence;
code rate corresponding to the information bit sequence;
modulation coding MCS level of the information bit sequence;
the aggregation level of a Control Channel Element (CCE) carrying an information bit sequence;
the size of the packet of the resource element group REG carrying the information bit sequence is bundle size;
a search space corresponding to the information bit sequence;
scrambling mode of information bit sequence;
the number of transmissions of the information bit sequence;
a channel type carrying the information bit sequence;
the control information format corresponding to the information bit sequence;
a Channel State Information (CSI) process corresponding to the information bit sequence;
a set of subframes carrying a sequence of information bits;
a carrier frequency carrying a sequence of information bits;
wherein the bit interleaving comprises:
writing the bit sequence to be interleaved into a matrix array to be interleaved according to columns;
interleaving bits in each modulation symbol summarized by the matrix array to be interleaved, wherein each column of the matrix array to be interleaved corresponds to at most one modulation symbol;
wherein interleaving bits within each modulation symbol in the matrix array to be interleaved comprises:
generating an interleaving pattern for each column of the matrix array to be interleaved;
interleaving bits within the modulation symbols of each column using a corresponding interleaving pattern;
wherein generating an interleaving pattern for each column of the matrix array to be interleaved comprises one of:
using a specified interleaving pattern in a first column of the matrix array to be interleaved, and performing cyclic shift on the interleaving patterns of the other columns except the first column on the basis of the specified interleaving pattern by using a cyclic shift value;
using a specified interleaving pattern in a first column of the matrix array to be interleaved, and performing cyclic shift on the other columns except the first column on the basis of a previous column by using cyclic shift values;
and using a non-correlated interleaving pattern in each column of the matrix array to be interleaved.
15. A storage medium, characterized in that the storage medium stores a program, wherein the program, when executed by a processor, performs the method of any one of claims 1 to 12.
16. A communications device comprising a processor and a memory, wherein the memory is configured to store a program, and wherein the processor executes the program to perform the method of any of claims 1 to 12.
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| CN106160971A (en) * | 2015-04-07 | 2016-11-23 | 电信科学技术研究院 | The transmission of a kind of data, the method and apparatus receiving signal detection |
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