CN109495206B - Method and equipment used in user and base station of wireless communication - Google Patents

Method and equipment used in user and base station of wireless communication Download PDF

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CN109495206B
CN109495206B CN201710811512.XA CN201710811512A CN109495206B CN 109495206 B CN109495206 B CN 109495206B CN 201710811512 A CN201710811512 A CN 201710811512A CN 109495206 B CN109495206 B CN 109495206B
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bit
subsequences
sequence
class
real number
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CN109495206A (en
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吴克颖
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Shanghai Langbo Communication Technology Co Ltd
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Shanghai Langbo Communication Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Abstract

The application discloses a method and a device used in a user and a base station of wireless communication. The first node performs a first operation. The first bit sequence and the second bit sequence are input and output of the first operation respectively, and the second bit sequence comprises the same bits as the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, and the first Q1-1 of the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, …, 2 times of Q1 and the difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any second-class bit subsequence pair comprises two second-class bit subsequences with the same length; at most one bit in any of the second class bit subsequences belongs to any of the first class bit subsequences. The interleaving scheme provided by the application has lower implementation complexity and better performance.

Description

Method and equipment used in user and base station of wireless communication
Technical Field
The present invention relates to a transmission scheme of a radio signal in a wireless communication system, and more particularly, to a method and apparatus for interleaved transmission.
Background
Polar Codes (Polar Codes) is a coding scheme first proposed by professor Erdal Arikan university of turkish birken in 2008, and is a code construction method that can realize the capacity of a symmetric binary input Discrete Memoryless Channel (B-DMC). At the 3GPP (3rd generation partner Project) RAN1#87 conference, the 3GPP has determined a control channel coding scheme that employs a polar coding scheme as a 5G eMBB (enhanced mobile broadband) scenario. For polar codes, the introduction of an interleaving operation between the channel encoder and the modulation mapper is important to the performance of the polar code, especially under high order modulation. On the 3gpp ran1#90 conference, a triangle-based interleaver design was adopted.
Disclosure of Invention
The inventor finds that the existing triangle-based interleaver is written in rows and read out in columns through research. The design scheme has the problems that the side length calculation is complex, element interweaving on a triangular angle is insufficient, and the performance is affected.
In view of the above, the present application discloses a solution. Without conflict, embodiments and features in embodiments in a first node of the present application may be applied to a second node and vice versa. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
The application discloses a method in a first node used for wireless communication, comprising:
-performing a first operation;
wherein a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
As an embodiment, the essence of the above method is that the first operation is an Interleaving (Interleaving) operation between channel coding (channelization) and modulation mapping (modulation mapping), and the Interleaving scheme proposed by the above method is based on a delta design. Different from the existing interleaving scheme based on triangle design, the elements in the interleaver in the method are written in a horizontal line mode from the obtuse vertex angle of the triangle and then read out in a vertical line mode from any vertex angle of the triangle; in the existing interleaving scheme based on the triangle design, elements are written in rows from one side of a quadrangle or a triangle and then read out in columns.
As an embodiment, the number of bits included in the first Q1-1 first-type bit subsequences of the Q1 sequentially arranged first-type bit subsequences is sequentially increased by 2, and the number of bits included in the last first-type bit subsequence of the Q1 sequentially arranged first-type bit subsequences is less than the difference obtained by subtracting 1 from Q1, which is 2 times.
As an embodiment, the number of bits included in the Q1 sequentially arranged first-type bit subsequences is sequentially increased by 2.
As an embodiment, the interleaving scheme proposed in the above method has the advantage of simpler implementation and better performance compared to the existing interleaving scheme.
As one embodiment, the first bit sequence includes a positive integer number of bits.
As an embodiment, the second bit sequence comprises a positive integer number of bits.
As an embodiment, the first bit sequence and the second bit sequence comprise the same number of bits.
For one embodiment, any one of the Q1 sequentially arranged first-type bit subsequences includes a positive integer number of bits.
For one embodiment, any one of the Q2 sequentially arranged subsequences of bits of the second type includes a positive integer number of bits.
As an embodiment, there is no bit belonging to any two of the Q1 sequentially arranged subsequences of bits of the first type at the same time.
As an embodiment, there is no bit belonging to any two of said Q2 sequentially arranged subsequences of bits of the second type simultaneously.
As an embodiment, the last one of the Q1 subsequences of bits of the first type that are sequentially arranged consists of P bits that are sequentially arranged, where P is a positive integer.
As an example, P is equal to 2 times the difference of Q1 minus 1.
As an example, the P is less than 2 times the difference of Q1 minus 1.
As one embodiment, the first operation is interleaving.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 1.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 2.
As an example, the Q2 is equal to the Q3 multiplied by 2 plus 1.
As an example, the Q2 is equal to the Q3 multiplied by 2 plus 2.
As an embodiment, the bits in any one of the Q1 sequentially arranged first-type bit subsequences are sequentially arranged.
As an embodiment, the bits in any one of the Q2 sequentially arranged sub-sequences of bits of the second type are sequentially arranged.
As an embodiment, two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are consecutive in the Q2 sequentially arranged second-type bit sub-sequences.
As an embodiment, two second-type bit sub-sequences in any one of the Q3 second-type bit-sequence pairs are discontinuous among the Q2 sequentially arranged second-type bit sub-sequences.
For one embodiment, there is at least one second-type bit subsequence in between two second-type bit subsequences in any one of the Q3 second-type bit subsequence pairs.
As an example, for a given one of the Q3 pairs of second analog bit-sub-sequences, there are Q5 sequentially arranged second-type bit-sub-sequences in between the two second-type bit-sub-sequences of the given pair of second analog bit-sub-sequences, the Q5 being a positive integer.
As a sub-embodiment of the above embodiment, the Q5 relates to the positions of the two second-type bit sub-sequences in the Q2 sequentially arranged second-type bit sub-sequences.
As a sub-embodiment of the above embodiment, the last first-type bit sub-sequence of the Q1 sequentially arranged first-type bit sub-sequences is composed of Q1 sequentially arranged bits, and Q5 is an odd number.
As a sub-embodiment of the above embodiment, the earlier the position of the first sequence in the second bit sequence is, the larger the Q5 is, and the first sequence is the earlier one of the two second-type bit subsequences in the second bit sequence.
As a sub-embodiment of the above embodiment, the Q5 is the same for all of the Q3 pairs of second analog bit sub-sequence pairs.
As a sub-embodiment of the foregoing embodiment, the indexes of the two second-class bit sub-sequences in the Q2 sequentially arranged second-class bit sub-sequences are a1 and a2, respectively, the a1 and the a2 are positive integers not greater than the Q2, the a1 is smaller than the a2, and the difference between the a2 and 1 is equal to the difference between the Q2 and the a 1.
As an embodiment, the number of bits included in the last first-type bit subsequence of the Q1 sequentially arranged first-type bit subsequences is equal to 2 times the difference obtained by subtracting 1 from Q1, the difference obtained by subtracting 1 from 2 times Q1 is equal to Q2, and the difference obtained by subtracting 1 from Q1 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As an embodiment, the number of bits included in the last first-type bit subsequence in the Q1 sequentially arranged first-type bit subsequences is less than or equal to Q1, a difference obtained by subtracting 2 from 2 times of Q1 is equal to Q2, and a difference obtained by subtracting 2 from Q1 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As an embodiment, the number of bits included in the last first-type bit subsequence in the Q1 sequentially arranged first-type bit subsequences is greater than Q1 and less than 2 times the difference between Q1 and 1, the difference between 2 times Q1 and 2 is equal to Q2, and the difference between Q1 and 2 is equal to Q3.
As a sub-embodiment of the foregoing embodiment, the number of bits included in one second-class bit sub-sequence of the Q3 second-class bit sub-sequence pairs is Q3 positive integers which are unequal two by two, the Q3 positive integers which are unequal two by two form a first integer set, the first integer set is composed of all positive integers from 1 to Q3 except Q8, and the difference obtained by subtracting 1 from Q1 and subtracting P from P by 2 times is equal to Q8, and P is the number of bits included in the last first-class bit sub-sequence of the Q1 sequentially arranged first-class bit sub-sequences.
As an example, the second class bit sub-sequence of the Q3 second class bit sub-sequence pairs that occurs first in the second bit sequence includes a number of bits of 1.
As an embodiment, a second class bit subsequence of the Q3 second class bit subsequence pairs that occurs first in the second bit sequence includes the number of bits that is the Q3.
As an embodiment, the first node is a UE (User Equipment).
As an embodiment, the first node is a base station.
According to one aspect of the application, the method is characterized by comprising the following steps:
-performing channel coding;
wherein the first bit sequence is an output of the channel coding.
As one embodiment, the channel coding includes rate matching (rate matching).
As an embodiment, the channel coding is based on Turbo coding.
As an example, the channel coding is based on LDPC (Low Density Parity Check) coding.
As an embodiment, the channel coding is based on polar (polar) coding.
As an embodiment, the channel coding is based on convolutional coding.
As an embodiment, the input of the channel coding is a third bit sequence comprising a positive integer number of bits.
As a sub-embodiment of the above embodiment, the bits in the third bit sequence are sequentially input into the channel encoder corresponding to the channel encoding.
According to one aspect of the application, the method is characterized by comprising the following steps:
-transmitting a first wireless signal;
wherein the second bit sequence is used to generate the first wireless signal.
As an embodiment, the first radio signal is an output of the second bit sequence after sequentially passing through a Modulation Mapper (Modulation Mapper), a Layer Mapper (Layer Mapper), a Precoding (Precoding), a Resource Element Mapper (Resource Element Mapper), and a multi-carrier symbol Generation (Generation).
As a sub-embodiment of the above-mentioned embodiment, the multi-carrier symbol is an OFDM (orthogonal frequency division Multiplexing) symbol.
As a sub-embodiment of the above-described embodiment, the multicarrier symbol is a DFT-S-OFDM (discrete fourier Transform Spread OFDM) symbol.
As a sub-embodiment of the above embodiment, the multi-carrier symbol is an FBMC (Filter Bank multi carrier) symbol.
As an embodiment, the first wireless signal is an output of the second bit sequence after sequentially passing through a modulation mapper, a layer mapper, a conversion precoder (for generating a complex-valued signal), a precoding, a resource element mapper, and a multi-carrier symbol generation.
As an example, the first wireless signal is transmitted on a physical layer control channel (i.e., a physical layer channel that cannot be used to transmit physical layer data).
As one embodiment, the first wireless signal is transmitted on a physical layer data channel (i.e., a physical layer channel that can be used to carry physical layer data).
As an embodiment, the first node is a UE.
As a sub-embodiment of the foregoing embodiment, the first radio signal is transmitted on a PUCCH (physical uplink control Channel).
As a sub-embodiment of the foregoing embodiment, the first wireless signal is transmitted on sPUCCH (short PUCCH).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NR-PUCCH (New radio PUCCH).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NB-PUCCH (narrow band PUCCH).
As a sub-embodiment of the above-mentioned embodiment, the first wireless signal is transmitted on a PUSCH (Physical uplink shared CHannel).
As a sub-embodiment of the above embodiment, the first wireless signal is transmitted on a short PUSCH (short PUSCH).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NR-PUSCH (new radio PUSCH).
As a sub-implementation of the above-described embodiment, the first radio signal is transmitted on NB-PUSCH (narrowband PUSCH).
As an embodiment, the first node is a base station.
As a sub-embodiment of the foregoing embodiment, the first radio signal is transmitted on a PDCCH (physical downlink control Channel).
As a sub-embodiment of the foregoing embodiment, the first wireless signal is transmitted on an sPDCCH (short PDCCH).
As a sub-embodiment of the above-mentioned embodiments, the first radio signal is transmitted on an NR-PDCCH (New radio PDCCH).
As a sub-embodiment of the above-mentioned embodiments, the first radio signal is transmitted on NB-PDCCH (narrow band PDCCH).
As a sub-embodiment of the above-mentioned embodiment, the first wireless signal is transmitted on a PDSCH (physical downlink Shared CHannel).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on sPDSCH (short PDSCH).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NR-PDSCH (new radio PDSCH).
As a sub-embodiment of the above embodiment, the first radio signal is transmitted on NB-PDSCH (narrowband PDSCH).
According to one aspect of the present application, the sum of Q2 plus 1 is equal to the product of Q1 and 2.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 1.
As an example, the Q3 is equal to the Q2 minus 1 and divided by 2.
As one example, the product of Q3 and 2 is equal to the difference equal to Q2 minus 1.
As an embodiment, the last one of the Q1 sequentially arranged subsequences of bits of the first type consists of P sequentially arranged bits, where P is equal to the difference between 2 times Q1 and 1.
According to one aspect of the present application, the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 2
As an example, the Q3 is equal to the Q2 minus 2 and divided by 2.
As one example, the product of Q3 and 2 is equal to the difference equal to Q2 minus 2.
As an embodiment, the last one of the Q1 subsequences of sequentially arranged first class bits is composed of P sequentially arranged bits, where P is a positive integer less than 2 times the difference between Q1 and 1.
According to an aspect of the application, it is characterized in that the first node is a base station.
As an embodiment, the first bit sequence includes downlink control information, and the first node is a base station.
As a sub-embodiment of the foregoing embodiment, the downlink control information includes at least one of corresponding Data { occupied time domain resource, occupied frequency domain resource, MCS (Modulation and Coding Scheme, Redundancy Version, RV (Redundancy Version), NDI (New Data Indicator), HARQ (hybrid automatic Repeat reQuest) process number }.
According to one aspect of the application, the first node is a user equipment
As an embodiment, the first bit sequence includes uplink control information, and the first node is a user equipment.
As a sub-embodiment of the foregoing embodiment, the uplink control information includes at least one of { HARQ-ACK (Acknowledgement), CSI (channel state information), SR (Scheduling Request), and CRI (CSI-RS resource indication) }.
The application discloses a method in a second node used for wireless communication, comprising:
-performing a second operation;
a first real sequence and a second real sequence are respectively an output and an input of the second operation, and real numbers included in the second real sequence are the same as real numbers included in the first real sequence; the first real number sequence consists of Q1 first-class real number subsequences which are sequentially arranged, and the first Q1-1 first-class real number subsequences in the Q1 first-class real number subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second real number sequence consists of Q2 second-type real number subsequences which are sequentially arranged, the Q2 second-type real number subsequences comprise Q3 second-type real number subsequence pairs, and any one second-type real number subsequence pair in the Q3 second-type real number subsequence pairs comprises two second-type real number subsequences with the same length; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
As an embodiment, the number of real numbers included in the first sequence of real numbers and the number of bits included in the first sequence of bits are equal, the real numbers included in the first sequence of real numbers and the bits included in the first sequence of bits have a one-to-one correspondence, and any real number in the first sequence of real numbers is soft information of the corresponding bit.
As an embodiment, the number of real numbers included in the second sequence of real numbers and the number of bits included in the second sequence of bits are equal, the number of real numbers included in the second sequence of real numbers and the number of bits included in the second sequence of bits are in one-to-one correspondence, and any real number in the second sequence of real numbers is soft information of the corresponding bit.
As one embodiment, the second operation is de-interleaving (de-interleaving).
As one embodiment, the first sequence of real numbers includes a positive integer number of real numbers.
As one embodiment, the second sequence of real numbers includes a positive integer number of real numbers.
As one embodiment, the first sequence of real numbers and the second sequence of real numbers comprise the same number of real numbers.
As an embodiment, any one of the Q1 subsequences of real numbers in the first type sequentially arranged includes a positive integer number of real numbers.
As an embodiment, any one of the Q2 subsequences of real numbers in the second type sequentially comprises positive integer numbers of real numbers.
As an embodiment, there is no real number belonging to any two real sub-sequences of the Q1 sequentially-arranged real sub-sequences simultaneously.
As an embodiment, there is no real number belonging to any two real sub-sequences of the second type among the Q2 sequentially-arranged real sub-sequences.
As an embodiment, the last real subsequence of the Q1 sequentially-ordered real subsequences of the first kind consists of Q1 sequentially-ordered real numbers.
As an embodiment, the last real subsequence of the Q1 real subsequences of the first type arranged in sequence consists of P real numbers arranged in sequence, where P is a positive integer smaller than Q1.
As an embodiment, the real numbers in any one of the Q1 real number sub-sequences of the first kind arranged in sequence are arranged in sequence.
In an embodiment, the real numbers in any one of the Q2 real number sub-sequences in the second type are sequentially arranged.
As one embodiment, two of any of the Q3 pairs of second-type real subsequences are consecutive in the second sequence of real numbers.
As one embodiment, two of any of the Q3 pairs of second-type real sub-sequences are discontinuous in the second sequence of real numbers.
As one embodiment, there is at least one second-type real subsequence in between two of any of the Q3 second-type real subsequence pairs.
As an embodiment, for a given pair of the Q3 pairs of real sub-sequences of the second type, Q5 subsequences of the second type sequentially arranged are present among two subsequences of the second type, and Q5 is a positive integer.
As a sub-embodiment of the above embodiment, the Q5 is related to the positions of the two second-type real sub-sequences in the Q2 second-type real sub-sequences arranged in sequence,
as a sub-embodiment of the foregoing embodiment, the last real subsequence of the Q1 sequentially-arranged real subsequences of the first type consists of Q1 sequentially-arranged real numbers, and Q5 is an odd number.
As a sub-embodiment of the foregoing embodiment, the earlier the position of the second sequence in the second real number sequence is, the larger the Q5 is, and the second sequence is one of the two second-type real number subsequences that is ranked earlier in the second real number sequence.
As a sub-embodiment of the foregoing embodiment, indexes of the two second-type real sub-sequences in the Q2 sequentially-arranged second-type real sub-sequences are a1 and a2, respectively, the a1 and the a2 are positive integers not greater than the Q2, the a1 is smaller than the a2, and the sum of the a2 plus 1 is equal to the difference between the Q2 and the a 1.
As an embodiment, the number of real numbers included in the last real number subsequence of the Q1 sequentially-arranged real number subsequences of the first type is equal to 2 times the difference obtained by subtracting 1 from Q1, the difference obtained by subtracting 1 from 2 times Q1 is equal to Q2, and the difference obtained by subtracting 1 from Q1 is equal to Q3.
As a sub-embodiment of the foregoing embodiment, the number of real numbers included in one real number subsequence of the second type in the Q3 pairs of real number subsequences of the second type is 1, 2, 3, …, and Q3 (i.e., starting from 1, increasing by 1 in sequence).
As an embodiment, the number of real numbers included in the last real number subsequence of the Q1 sequentially-arranged real number subsequences of the first type is less than or equal to Q1, a difference obtained by subtracting 2 from Q1 by 2 is equal to Q2, and a difference obtained by subtracting 2 from Q1 is equal to Q3.
As a sub-embodiment of the foregoing embodiment, the number of real numbers included in one real number subsequence of the second type in the Q3 pairs of real number subsequences of the second type is 1, 2, 3, …, and Q2 (i.e., starting from 1, increasing by 1 in sequence).
As an embodiment, the number of real numbers included in the last real number subsequence of the Q1 sequentially-arranged real number subsequences of the first type is greater than Q1 and less than 2 times the difference between Q1 and 1, the difference between 2 times Q1 and 2 is equal to Q2, and the difference between Q1 and 2 is equal to Q3.
As a sub-embodiment of the foregoing embodiment, the number of real numbers included in one real number subsequence of the Q3 pairs of real number subsequences of the second type is Q3 positive integers which are pairwise unequal, the Q3 positive integers which are pairwise unequal form a first integer set, the first integer set consists of all positive integers from 1 to Q3 except Q8, and the difference obtained by subtracting 1 from Q1 by 2 times and subtracting P from P is equal to Q8, where P is the number of real numbers included in the last real number subsequence of the real number subsequences of the first type which are sequentially arranged from Q1.
As an embodiment, the number of bits included in the second-type real subsequence of the Q3 second-type real subsequence pairs that occurs first in the second real sequence is 1.
As one embodiment, the second-type real subsequence of the Q3 pairs of second-type real subsequence pairs that occurs first in the second real sequence includes a number of bits of Q3.
As an embodiment, the second node is a base station.
As an embodiment, the second node is a UE (User Equipment).
According to one aspect of the application, the method is characterized by comprising the following steps:
-performing channel decoding;
wherein the first real sequence is an input to the channel coding.
As an embodiment, the first bit sequence is an input of a channel coding corresponding to the channel decoding.
According to one aspect of the application, the method is characterized by comprising the following steps:
-receiving a first wireless signal;
wherein the first wireless signal is used to generate the second real sequence.
As one embodiment, the second bit sequence is used to generate the first wireless signal.
As an embodiment, the second real sequence is obtained by sequentially performing DFT (discrete fourier Transform), multi-antenna detection, and constellation DeModulation (DeModulation) on the first wireless signal.
As an embodiment, the second real number sequence is obtained by sequentially performing DFT, equalization, multi-antenna detection, and constellation demodulation on the first wireless signal.
In one embodiment, the second real sequence is obtained by subjecting the first wireless signal to one or more of { DFT, equalization, multi-antenna detection, constellation demodulation }.
According to one aspect of the present application, the sum of Q2 plus 1 is equal to the product of Q1 and 2.
As one example, the product of Q3 and 2 is equal to the difference equal to Q2 minus 1.
As an embodiment, the last one of the Q1 sequentially arranged subsequences of bits of the first type consists of P sequentially arranged bits, where P is equal to the difference between 2 times Q1 and 1.
According to one aspect of the present application, the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As one example, the product of Q3 and 2 is equal to the difference equal to Q2 minus 2.
As an embodiment, the last one of the Q1 subsequences of sequentially arranged first class bits is composed of P sequentially arranged bits, where P is a positive integer less than 2 times the difference between Q1 and 1.
According to one aspect of the application, the second node is a user equipment.
According to an aspect of the application, it is characterized in that the second node is a base station.
The application discloses an apparatus in a first node used for wireless communication, comprising:
the first processing module executes a first operation;
wherein a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that said first processing module further performs channel coding; wherein the first bit sequence is an output of the channel coding.
As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the sum of said Q2 plus 1 is equal to the product of said Q1 and 2.
As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the first node is a base station.
As an embodiment, the apparatus in a first node for wireless communication as described above is characterized in that the first node is a user equipment.
As one embodiment, the apparatus in a first node for wireless communication described above is characterized by comprising:
a first transmitter module that transmits a first wireless signal;
wherein the second bit sequence is used to generate the first wireless signal.
The application discloses an apparatus in a second node used for wireless communication, comprising:
the second processing module executes a second operation;
a first real sequence and a second real sequence are respectively an output and an input of the second operation, and real numbers included in the second real sequence are the same as real numbers included in the first real sequence; the first real number sequence consists of Q1 first-class real number subsequences which are sequentially arranged, and the first Q1-1 first-class real number subsequences in the Q1 first-class real number subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second real number sequence consists of Q2 second-type real number subsequences which are sequentially arranged, the Q2 second-type real number subsequences comprise Q3 second-type real number subsequence pairs, and any one second-type real number subsequence pair in the Q3 second-type real number subsequence pairs comprises two second-type real number subsequences with the same length; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
As an embodiment, the apparatus in a second node for wireless communication as described above is characterized in that said second processing module further performs channel decoding; wherein the first real sequence is an input to the channel coding.
As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the sum of the Q2 plus 1 is equal to the product of the Q1 and 2.
As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the second node is a user equipment.
As an embodiment, the apparatus in the second node for wireless communication as described above is characterized in that the second node is a subscriber base station.
As one embodiment, the apparatus in a second node for wireless communication described above is characterized by comprising:
a first receiver module to receive a first wireless signal;
wherein the first wireless signal is used to generate the second real sequence.
As an example, compared with the conventional scheme, the method has the following advantages:
the present application proposes a new Interleaving scheme for Interleaving (Interleaving) operations between Channel Coding (Channel Coding) and modulation mapping (modulation mapping). Compared with the existing interleaving scheme, the interleaving scheme provided by the application has lower implementation complexity and better performance.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof with reference to the accompanying drawings in which:
FIG. 1 illustrates a flowchart for performing a first operation according to an embodiment of the present application;
FIG. 2 shows a schematic diagram of a network architecture according to an embodiment of the present application;
figure 3 shows a schematic diagram of an embodiment of a radio protocol architecture for the user plane and the control plane according to an embodiment of the present application;
figure 4 shows a schematic diagram of an evolved node and a UE according to an embodiment of the present application;
FIG. 5 shows a flow diagram of wireless transmission according to one embodiment of the present application;
FIG. 6 shows a flow diagram of wireless transmission according to another embodiment of the present application;
FIG. 7 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to an embodiment of the present application;
FIG. 8 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
FIG. 9 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
FIG. 10 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
FIG. 11 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
FIG. 12 shows a schematic diagram of generating a first wireless signal according to an embodiment of the present application;
FIG. 13 shows a block diagram of a processing device for use in a first node according to an embodiment of the present application;
figure 14 shows a block diagram of a processing arrangement for use in a second node according to an embodiment of the present application;
FIG. 15 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
FIG. 16 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application;
fig. 17 shows a schematic diagram of a relationship between a first bit sequence and a second bit sequence according to another embodiment of the present application.
Example 1
Embodiment 1 illustrates a flowchart for performing the first operation, as shown in fig. 1.
In embodiment 1, the first node in the present application performs a first operation. Wherein a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
As one embodiment, the first bit sequence includes a positive integer number of bits.
As an embodiment, the second bit sequence comprises a positive integer number of bits.
As an embodiment, the first bit sequence and the second bit sequence comprise the same number of bits.
For one embodiment, any one of the Q1 sequentially arranged first-type bit subsequences includes a positive integer number of bits.
For one embodiment, any one of the Q2 sequentially arranged subsequences of bits of the second type includes a positive integer number of bits.
As an embodiment, there is no bit belonging to any two of the Q1 sequentially arranged subsequences of bits of the first type at the same time.
As an embodiment, there is no bit belonging to any two of said Q2 sequentially arranged subsequences of bits of the second type simultaneously.
As an embodiment, the last first-type bit sub-sequence of the Q1 sequentially arranged first-type bit sub-sequences is composed of 2 times the difference of Q1 minus 1 sequentially arranged bits.
As an embodiment, the last one of the Q1 subsequences of sequentially arranged first class bits is composed of P sequentially arranged bits, where P is a positive integer less than 2 times the difference between Q1 and 1.
As one embodiment, the first operation is interleaving.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 1.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 2.
As an example, the Q2 is equal to the Q3 multiplied by 2 plus 1.
As an example, the Q2 is equal to the Q3 multiplied by 2 plus 2.
As an embodiment, the bits in any one of the Q1 sequentially arranged first-type bit subsequences are sequentially arranged.
As an embodiment, the bits in any one of the Q2 sequentially arranged sub-sequences of bits of the second type are sequentially arranged.
For one embodiment, the two second-type bit sub-sequences in any of the Q3 second-type bit sub-sequence pairs are adjacent in position in the Q2 sequentially arranged second-type bit sub-sequences.
For one embodiment, the positions of the two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs in the Q2 sequentially arranged second-type bit sub-sequences are not adjacent.
As an example, the second class bit sub-sequence of the Q3 second class bit sub-sequence pairs that occurs first in the second bit sequence includes a number of bits of 1.
As an embodiment, a second class bit subsequence of the Q3 second class bit subsequence pairs that occurs first in the second bit sequence includes the number of bits that is the Q3.
As an embodiment, the number of bits included in the last first-type bit subsequence of the Q1 sequentially arranged first-type bit subsequences is equal to 2 times the difference obtained by subtracting 1 from Q1, the difference obtained by subtracting 1 from 2 times Q1 is equal to Q2, and the difference obtained by subtracting 1 from Q1 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As an embodiment, the number of bits included in the last first-type bit subsequence in the Q1 sequentially arranged first-type bit subsequences is less than or equal to Q1, a difference obtained by subtracting 2 from 2 times of Q1 is equal to Q2, and a difference obtained by subtracting 2 from Q1 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As an embodiment, the number of bits included in the last first-type bit subsequence in the Q1 sequentially arranged first-type bit subsequences is greater than Q1 and less than 2 times the difference between Q1 and 1, the difference between 2 times Q1 and 2 is equal to Q2, and the difference between Q1 and 2 is equal to Q3.
As a sub-embodiment of the foregoing embodiment, the number of bits included in one second-class bit sub-sequence of the Q3 second-class bit sub-sequence pairs is Q3 positive integers which are unequal two by two, the Q3 positive integers which are unequal two by two form a first integer set, the first integer set is composed of all positive integers from 1 to Q3 except Q8, and the difference obtained by subtracting 1 from Q1 and subtracting P from P by 2 times is equal to Q8, and P is the number of bits included in the last first-class bit sub-sequence of the Q1 sequentially arranged first-class bit sub-sequences.
As an embodiment, the first node is a UE (User Equipment).
As an embodiment, the first node is a base station.
Example 2
Embodiment 2 illustrates a schematic diagram of a network architecture, as shown in fig. 2.
Fig. 2 illustrates a network architecture 200 of LTE (Long-Term Evolution), LTE-a (Long-Term Evolution Advanced), and future 5G systems. The LTE network architecture 200 may be referred to as EPS (Evolved Packet System) 200. The EPS 200 may include one or more UEs (User Equipment) 201, E-UTRAN-NR (Evolved UMTS terrestrial radio access network-new radio) 202, 5G-CN (5G-Core network, 5G Core network)/EPC (Evolved Packet Core) 210, HSS (Home Subscriber Server) 220, and internet service 230. The UMTS is compatible with Universal Mobile Telecommunications System (Universal Mobile Telecommunications System). The EPS may interconnect with other access networks, but these entities/interfaces are not shown for simplicity. As shown in fig. 2, the EPS provides packet-switched services, however, those skilled in the art will readily appreciate that the various concepts presented throughout this application may be extended to networks providing circuit-switched services. The E-UTRAN-NR includes NR node B (gNB)203 and other gNBs 204. The gNB203 provides user and control plane protocol termination towards the UE 201. The gNB203 may be connected to other gnbs 204 via an X2 interface (e.g., backhaul). The gNB203 may also be referred to as a base station, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a Basic Service Set (BSS), an Extended Service Set (ESS), a TRP (point of transmission reception), or some other suitable terminology. The gNB203 provides the UE201 with an access point to the 5G-CN/EPC 210. Examples of the UE201 include a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop, a Personal Digital Assistant (PDA), a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a gaming console, a drone, an aircraft, a narrowband physical network device, a machine type communication device, a land vehicle, an automobile, a wearable device, or any other similar functioning device. Those skilled in the art may also refer to UE201 as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless communication device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. The gNB203 is connected to the 5G-CN/EPC210 through an S1 interface. The 5G-CN/EPC210 includes an MME211, other MMEs 214, an S-GW (Service Gateway) 212, and a P-GW (Packet data Network Gateway) 213. The MME211 is a control node that handles signaling between the UE201 and the 5G-CN/EPC 210. In general, the MME211 provides bearer and connection management. All user IP (Internet protocol) packets are transmitted through S-GW212, and S-GW212 itself is connected to P-GW 213. The P-GW213 provides UE IP address allocation as well as other functions. The P-GW213 is connected to the internet service 230. The internet service 230 includes an operator-corresponding internet protocol service, and may specifically include the internet, an intranet, an IMS (IP multimedia subsystem), and a PS streaming service (PSs).
As an embodiment, the UE201 corresponds to the first node in this application, and the gNB203 corresponds to the second node in this application.
As an embodiment, the UE201 corresponds to the second node in this application, and the gNB203 corresponds to the first node in this application.
Example 3
Embodiment 3 illustrates a schematic diagram of an embodiment of radio protocol architecture for the user plane and the control plane, as shown in fig. 3.
Fig. 3 is a schematic diagram illustrating an embodiment of radio protocol architecture for the user plane and the control plane, fig. 3 showing the radio protocol architecture for the UE and the gNB in three layers: layer 1, layer 2 and layer 3. Layer 1(L1 layer) is the lowest layer and implements various PHY (physical layer) signal processing functions. The L1 layer will be referred to herein as PHY 301. Layer 2(L2 layer) 305 is above PHY301 and is responsible for the link between the UE and the gNB through PHY 301. In the user plane, the L2 layer 305 includes a MAC (media access Control) sublayer 302, an RLC (Radio Link Control) sublayer 303, and a PDCP (Packet Data Convergence Protocol) sublayer 304, which terminate at the gNB on the network side. Although not shown, the UE may have several protocol layers above the L2 layer 305, including a network layer (e.g., IP layer) that terminates at the P-GW213 on the network side and an application layer that terminates at the other end of the connection (e.g., far end UE, server, etc.). The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. The PDCP sublayer 304 also provides header compression for upper layer packets to reduce radio transmission overhead, security by ciphering the packets, and handover support for UEs between gnbs. The RLC sublayer 303 provides segmentation and reassembly of upper layer packets, retransmission of lost packets, and reordering of packets to compensate for out-of-order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical and transport channels. The MAC sublayer 302 is also responsible for allocating various radio resources (e.g., resource blocks) in one cell among the UEs. The MAC sublayer 302 is also responsible for HARQ operations. In the control plane, the radio protocol architecture for the UE and the gNB is substantially the same for the physical layer 301 and the L2 layer 305, but without the header compression function for the control plane. The Control plane also includes an RRC (Radio Resource Control) sublayer 306 in layer 3 (layer L3). The RRC sublayer 306 is responsible for obtaining radio resources (i.e., radio bearers) and configures the lower layers using RRC signaling between the gNB and the UE.
As an example, the wireless protocol architecture in fig. 3 is applicable to the first node in this application.
As an example, the radio protocol architecture in fig. 3 is applicable to the second node in this application.
As an example, the first bit sequence in this application is generated in the PHY 301.
As an example, the second bit sequence in this application is generated in the PHY 301.
As an example, the first wireless signal in this application is generated in the PHY 301.
Example 4
Embodiment 4 illustrates a schematic diagram of an evolved node and a UE, as shown in fig. 4.
The gNB410 includes a controller/processor 475, a memory 476, a receive processor 470, a transmit processor 416, a channel coder/interleaver 477, a channel decoder/deinterleaver 478, a transmitter/receiver 418, and antennas 420.
The UE450 includes a controller/processor 459, a memory 460, a data source 467, a transmit processor 468, a receive processor 456, a channel coder/interleaver 457, a channel decoder/deinterleaver 458, a transmitter/receiver 454, and antennas 452.
In the DL (Downlink), at the gNB, upper layer data packets from the core network are provided to a controller/processor 475. The controller/processor 475 implements the functionality of layer L2. In the DL, the controller/processor 475 provides header compression, ciphering, packet segmentation and reordering, multiplexing between logical and transport channels, and allocation of radio resources for the UE450 based on various priority metrics. Controller/processor 475 is also responsible for HARQ operations, retransmission of lost packets, and signaling to UE 450. The transmit processor 416 and the channel coder/interleaver 477 perform various signal processing functions for the L1 layer (i.e., the physical layer). Channel coder/interleaver 477 performs coding and interleaving to facilitate Forward Error Correction (FEC) at UE 450. Transmit processor 416 performs mapping for signal constellation based on various modulation schemes (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), M-phase-shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM)) and performs spatial precoding/beamforming on the encoded and modulated symbols to generate one or more spatial streams. Transmit processor 416 then maps each spatial stream to subcarriers, multiplexes with reference signals (e.g., pilots) in the time and/or frequency domain, and then uses an Inverse Fast Fourier Transform (IFFT) to generate the physical channels carrying the time-domain multicarrier symbol streams. Each transmitter 418 converts the baseband multi-carrier symbol stream provided by the transmit processor 416 into a radio frequency stream that is then provided to a different antenna 420.
In the DL (Downlink), at the UE450, each receiver 454 receives a signal through its respective antenna 452. Each receiver 454 recovers information modulated onto a radio frequency carrier and converts the radio frequency stream into a baseband multi-carrier symbol stream that is provided to a receive processor 456. The receive processor 456 and the channel decoder/deinterleaver 458 implement various signal processing functions of the L1 layer. Receive processor 456 converts the baseband multicarrier symbol stream from the time domain to the frequency domain using a Fast Fourier Transform (FFT). In the frequency domain, the physical layer data signals and the reference signals to be used for channel estimation are demultiplexed by the receive processor 456, and the physical layer data is recovered into spatial streams destined for the UE450 through multi-antenna detection in the receive processor 456. The symbols on each spatial stream are demodulated and recovered at a receive processor 456 and soft decisions are generated. A channel decoder/deinterleaver 458 then decodes and deinterleaves the soft decisions to recover the upper layer data and control signals transmitted by the gNB410 on the physical channels. The upper layer data and control signals are then provided to a controller/processor 459. The controller/processor 459 implements the functionality of the L2 layer. The controller/processor can be associated with a memory 460 that stores program codes and data. Memory 460 may be referred to as a computer-readable medium. In the DL, the controller/processor 459 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer data packets from the core network. The upper layer packet is then provided to all protocol layers above the L2 layer. Various control signals may also be provided to L3 for L3 processing. The controller/processor 459 is also responsible for error detection using an Acknowledgement (ACK) and/or Negative Acknowledgement (NACK) protocol to support HARQ operations.
In the UL (Uplink), at the UE450, a data source 467 is used to provide upper layer data packets to the controller/processor 459. Data source 467 represents all protocol layers above the L2 layer. Similar to the transmit function at the gNB410 described in the DL, the controller/processor 459 implements header compression, encryption, packet segmentation and reordering, and multiplexing between logical and transport channels based on the radio resource allocation of the gNB410, implementing L2 layer functions for the user plane and the control plane. The controller/processor 459 is also responsible for HARQ operations, retransmission of lost packets, and signaling to the gNB 410. Channel coder/interleaver 457 performs channel coding, and the coded data is modulated into a multi-carrier/single-carrier symbol stream by modulation performed by transmit processor 468 and multi-antenna spatial precoding/beamforming, and provided to different antennas 452 via transmitter 454. Each transmitter 454 first converts the baseband symbol stream provided by the transmit processor 468 into a radio frequency symbol stream that is provided to the antenna 452.
In UL (Uplink), the function at the gNB410 is similar to the reception function at the UE450 described in DL. Each receiver 418 receives radio frequency signals through its respective antenna 420, converts the received radio frequency signals to baseband signals, and provides the baseband signals to a receive processor 470. The receive processor 470 and the channel decoding/deinterleaver 478 collectively implement the functions of the L1 layer. Controller/processor 475 implements the L2 layer functions. The controller/processor 475 can be associated with a memory 476 that stores program codes and data. Memory 476 may be referred to as a computer-readable medium. In the UL, the controller/processor 475 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer packets from the UE 450. Upper layer packets from the controller/processor 475 may be provided to the core network. Controller/processor 475 is also responsible for error detection using the ACK and/or NACK protocol to support HARQ operations.
As an embodiment, the UE450 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor.
As an embodiment, the UE450 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: the first operation in the present application is performed, the channel coding in the present application is performed, and the first wireless signal in the present application is transmitted.
As an embodiment, the UE450 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: performing the second operation in the present application, performing the channel decoding in the present application, and receiving the first wireless signal in the present application.
As an embodiment, the gNB410 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor.
As an embodiment, the gNB410 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: performing the second operation in the present application, performing the channel decoding in the present application, and receiving the first wireless signal in the present application.
As an embodiment, the gNB410 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: the first operation in the present application is performed, the channel coding in the present application is performed, and the first wireless signal in the present application is transmitted.
As an embodiment, the UE450 corresponds to the first node in this application, and the gNB410 corresponds to the second node in this application.
As an embodiment, the UE450 corresponds to the second node in this application, and the gNB410 corresponds to the first node in this application.
As an example, at least one of the { the transmit processor 468, the channel coder/interleaver 457} is used to perform the first operation; at least one of the receive processor 470, the channel decoding/deinterleaver 478 is used to perform the second operation.
As an example, at least one of { the transmit processor 468, the channel coder/interleaver 457} is used to perform the channel coding; at least one of the receive processor 470, the channel decoding/deinterleaver 478 is used to perform the channel decoding.
As an embodiment, at least one of { the antenna 452, the transmitter 454, the transmission processor 468, the channel coder/interleaver 457, the controller/processor 459} is used for transmitting the first wireless signal; at least one of the antenna 420, the receiver 418, the reception processor 470, the channel decoding/deinterleaver 478, the controller/processor 475 is used to receive the first wireless signal.
For one embodiment, at least one of { the transmit processor 416, the channel coder/interleaver 477} is used to perform the first operation; at least one of the receive processor 456, the channel decoding/deinterleaver 458 is used to perform the second operation.
For one embodiment, at least one of { the transmit processor 416, the channel coder/interleaver 477} is used to perform the channel coding; at least one of the reception processor 456, the channel decoding/deinterleaver 458 is used to perform the channel decoding.
As an example, at least one of { the antenna 420, the transmitter 418, the transmit processor 416, the channel coder/interleaver 477, the controller/processor 475} is used to transmit the first wireless signal; at least one of the antenna 452, the receiver 454, the receive processor 456, the channel decoder/deinterleaver 458, and the controller/processor 459 is used to receive the first wireless signal.
Example 5
Embodiment 5 illustrates a flow chart of wireless transmission, as shown in fig. 5. In fig. 5, base station N1 is the serving cell maintenance base station for UE U2.
For N1, channel coding is performed in step S11; a first operation is performed in step S12; the first wireless signal is transmitted in step S13.
For U2, a first wireless signal is received in step S21; a second operation is performed in step S22; channel decoding is performed in step S23.
In embodiment 5, the first and second bit sequences are input and output, respectively, of the first operation, and the first and second real sequences are output and input, respectively, of the second operation. The bits included in the second bit sequence are the same as the bits included in the first bit sequence, and the real numbers included in the second real number sequence are the same as the real numbers included in the first real number sequence. The first bit sequence and the first real number sequence are composed of Q1 first-class bit subsequences arranged in sequence and Q1 first-class real number subsequences arranged in sequence respectively; the first Q1-1 first-class bit subsequences in the Q1 sequentially arranged first-class bit subsequences are respectively composed of 1, 3, …, and the difference obtained by subtracting 3 from 2 times of Q1; the first Q1-1 real number subsequences in the Q1 sequentially arranged real number subsequences consist of difference sequentially arranged real numbers obtained by subtracting 3 from 1, 3, … and 2 times of Q1. The second bit sequence and the second real number sequence are respectively composed of Q2 second-class bit subsequences arranged in sequence and Q2 second-class real number subsequences arranged in sequence; the Q2 second-class bit sub-sequences comprise Q3 second-class bit sub-sequence pairs, and any one of the Q3 second-class bit sub-sequence pairs comprises two second-class bit sub-sequences with the same length; the Q2 second-type real subsequence pairs sequentially arranged comprise Q3 second-type real subsequence pairs, and any one of the Q3 second-type real subsequence pairs comprises two second-type real subsequence pairs with the same length. At most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences. The Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2. The first bit sequence is the output of the channel coding and the first real sequence is the input of the channel coding. The second sequence of bits is used by the N1 to generate the first wireless signal, which is used by the U2 to generate the second sequence of real numbers.
As one embodiment, the first bit sequence includes a positive integer number of bits.
As an embodiment, the second bit sequence comprises a positive integer number of bits.
As one embodiment, the first sequence of real numbers includes a positive integer number of real numbers.
As one embodiment, the second sequence of real numbers includes a positive integer number of real numbers.
For one embodiment, any one of the Q1 sequentially arranged first-type bit subsequences includes a positive integer number of bits.
For one embodiment, any one of the Q2 sequentially arranged subsequences of bits of the second type includes a positive integer number of bits.
As an embodiment, any one of the Q1 subsequences of real numbers in the first type sequentially arranged includes a positive integer number of real numbers.
As an embodiment, any one of the Q2 subsequences of real numbers in the second type sequentially comprises positive integer numbers of real numbers.
As one embodiment, the first operation is interleaving.
As one embodiment, the second operation is de-interleaving (de-interleaving).
As an embodiment, the number of real numbers included in the first sequence of real numbers and the number of bits included in the first sequence of bits are equal, the real numbers included in the first sequence of real numbers and the bits included in the first sequence of bits have a one-to-one correspondence, and any real number in the first sequence of real numbers is soft information of the corresponding bit.
As an embodiment, the number of real numbers included in the second sequence of real numbers and the number of bits included in the second sequence of bits are equal, the number of real numbers included in the second sequence of real numbers and the number of bits included in the second sequence of bits are in one-to-one correspondence, and any real number in the second sequence of real numbers is soft information of the corresponding bit.
As an embodiment, the bits in any one of the Q1 sequentially arranged first-type bit subsequences are sequentially arranged.
As an embodiment, the bits in any one of the Q2 sequentially arranged sub-sequences of bits of the second type are sequentially arranged.
As an embodiment, the real numbers in any one of the Q1 real number sub-sequences of the first kind arranged in sequence are arranged in sequence.
In an embodiment, the real numbers in any one of the Q2 real number sub-sequences in the second type are sequentially arranged.
As one embodiment, the channel coding includes rate matching (rate matching).
As an embodiment, the channel coding is based on polar (polar) coding.
As an embodiment, the first wireless signal is transmitted on a downlink physical layer control channel (i.e. a downlink channel that can only be used for carrying physical layer signaling).
As a sub-embodiment of the foregoing embodiment, the downlink physical layer control channel is a PDCCH.
As a sub-embodiment of the foregoing embodiment, the downlink physical layer control channel is sPDCCH.
As a sub-embodiment of the above-mentioned embodiment, the downlink physical layer control channel is an NR-PDCCH.
As a sub-embodiment of the foregoing embodiment, the downlink physical layer control channel is an NB-PDCCH.
As an embodiment, the first wireless signal is transmitted on a downlink physical layer data channel (i.e., a downlink channel that can be used to carry physical layer data).
As a sub-embodiment of the above-mentioned embodiment, the downlink physical layer data channel is a PDSCH.
As a sub-embodiment of the above embodiment, the downlink physical layer data channel is sPDSCH.
As a sub-embodiment of the above embodiment, the downlink physical layer data channel is NR-PDSCH.
As a sub-embodiment of the above embodiment, the downlink physical layer data channel is an NB-PDSCH.
As an embodiment, the second real number sequence is obtained by sequentially performing DFT, multi-antenna detection, and constellation demodulation on the first wireless signal.
As an embodiment, the second real number sequence is obtained by sequentially performing DFT, equalization, multi-antenna detection, and constellation demodulation on the first wireless signal.
In one embodiment, the second real sequence is obtained by subjecting the first wireless signal to one or more of { DFT, equalization, multi-antenna detection, constellation demodulation }.
As an example, the sum of Q2 plus 1 is equal to the product of Q1 and 2, and the difference of Q2 minus 1 is equal to the product of Q3 and 2.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 1, and the Q3 is equal to the Q2 minus 1 divided by 2.
As an example, the sum of Q2 plus 2 is equal to the product of Q1 and 2, and the difference of Q2 minus 2 is equal to the product of Q3 and 2.
As one example, the Q2 is equal to the Q1 multiplied by 2 minus 2, and the Q3 is equal to the Q2 minus 2 divided by 2.
As an embodiment, the first bit sequence includes downlink control information.
As a sub-embodiment of the foregoing embodiment, the downlink control information includes at least one of corresponding data { occupied time domain resource, occupied frequency domain resource, MCS, RV, NDI, HARQ process number }.
Example 6
Embodiment 6 illustrates a flow chart of wireless transmission, as shown in fig. 6. In fig. 6, base station N3 is the serving cell maintenance base station for UE U4.
For N3, a first wireless signal is received in step S31; a second operation is performed in step S32; channel decoding is performed in step S33.
For U4, channel coding is performed in step S41; a first operation is performed in step S42; the first wireless signal is transmitted in step S43.
In embodiment 6, the first and second bit sequences are input and output, respectively, of the first operation, and the first and second real sequences are output and input, respectively, of the second operation. The bits included in the second bit sequence are the same as the bits included in the first bit sequence, and the real numbers included in the second real number sequence are the same as the real numbers included in the first real number sequence. The first bit sequence and the first real number sequence are composed of Q1 first-class bit subsequences arranged in sequence and Q1 first-class real number subsequences arranged in sequence respectively; the first Q1-1 first-class bit subsequences in the Q1 sequentially arranged first-class bit subsequences are respectively composed of 1, 3, …, and the difference obtained by subtracting 3 from 2 times of Q1; the first Q1-1 real number subsequences in the Q1 sequentially arranged real number subsequences consist of difference sequentially arranged real numbers obtained by subtracting 3 from 1, 3, … and 2 times of Q1. The second bit sequence and the second real number sequence are respectively composed of Q2 second-class bit subsequences arranged in sequence and Q2 second-class real number subsequences arranged in sequence; the Q2 second-class bit sub-sequences comprise Q3 second-class bit sub-sequence pairs, and any one of the Q3 second-class bit sub-sequence pairs comprises two second-class bit sub-sequences with the same length; the Q2 second-type real subsequence pairs sequentially arranged comprise Q3 second-type real subsequence pairs, and any one of the Q3 second-type real subsequence pairs comprises two second-type real subsequence pairs with the same length. At most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences. The Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2. The first bit sequence is the output of the channel coding and the first real sequence is the input of the channel coding. The second bit sequence is used by the U4 to generate the first wireless signal, which is used by the N3 to generate the second real sequence.
As an embodiment, the first wireless signal is transmitted on an uplink physical layer control channel (i.e. an uplink channel that can only be used to carry physical layer signaling).
As a sub-embodiment of the foregoing embodiment, the uplink physical layer control channel is a PUCCH.
As a sub-embodiment of the foregoing embodiment, the uplink physical layer control channel is sPUCCH.
As a sub-embodiment of the above-mentioned embodiments, the uplink physical layer control channel is NR-PUCCH.
As a sub-embodiment of the above embodiment, the uplink physical layer control channel is NB-PUCCH.
As an example, the first wireless signal is transmitted on an uplink physical layer data channel (i.e., an uplink channel that can be used to carry physical layer data).
As a sub-embodiment of the foregoing embodiment, the uplink physical layer data channel is a PUSCH.
As a sub-embodiment of the foregoing embodiment, the uplink physical layer data channel is an sPUSCH.
As a sub-embodiment of the above-mentioned embodiment, the uplink physical layer data channel is NR-PUSCH.
As a sub-embodiment of the above-mentioned embodiment, the uplink physical layer data channel is NB-PUSCH.
As an embodiment, the first bit sequence includes uplink control information.
As a sub-embodiment of the foregoing embodiment, the uplink control information includes at least one of { HARQ-ACK, CSI, SR, CRI }.
Example 7
Embodiment 7 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 7.
In embodiment 7, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, and the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, … and 2 times of difference sequentially arranged bits obtained by subtracting 1 from Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 2, the sum of the Q2 plus 1 is equal to the product of the Q1 and 2, and the difference of the Q2 minus 1 is equal to the product of the Q3 and 2. The positions of the two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs in the Q2 sequentially arranged second-type bit sub-sequences are discontinuous.
In fig. 7, the first bit sequence is composed of 25 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x25Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in each ellipse with the dotted border is one second-type bit subsequence in the Q2 sequentially-arranged second-type bit subsequencesThe sequence, the sequence number of the dashed border is the index of the Q2 sequentially arranged sub-sequences of the second type bits. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
As an embodiment, the bits in any one of the Q1 sequentially arranged first-type bit subsequences are sequentially arranged.
As an embodiment, the bits in any one of the Q2 sequentially arranged sub-sequences of bits of the second type are sequentially arranged.
As an embodiment, there is no bit belonging to any two of the Q1 sequentially arranged subsequences of bits of the first type at the same time.
As an embodiment, there is no bit belonging to any two of said Q2 sequentially arranged subsequences of bits of the second type simultaneously.
As an example, for a given one of the Q3 pairs of second analog bit-sub-sequences, there are Q5 sequentially arranged second-type bit-sub-sequences in between the two second-type bit-sub-sequences of the given pair of second analog bit-sub-sequences, the Q5 being a positive integer.
As a sub-embodiment of the above embodiment, the Q5 relates to the positions of the two second-type bit sub-sequences in the Q2 sequentially arranged second-type bit sub-sequences,
as a sub-embodiment of the above embodiment, the Q5 is an odd number smaller than the Q3.
As a sub-embodiment of the above embodiment, the earlier the position of the first sequence in the Q2 sequentially arranged second-class bit subsequences, the larger the Q5 is; the first sequence is a previous one of the two second-type bit subsequences in the Q2 sequentially arranged second-type bit subsequences.
As an embodiment, for a given pair of the Q3 pairs of second-class bit-sequences, the indices of the two subsequences of the given pair of second-class bit-sequences in the Q2 sequentially ordered subsequences of second-class bit-sequences are a1 and a2, respectively, the a1 and the a2 are positive integers not greater than the Q2, the a1 is smaller than the a2, and the a2 is equal to the Q2 minus the a1 plus 1.
Example 8
Embodiment 8 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 8.
In embodiment 8, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, and the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, … and 2 times of difference sequentially arranged bits obtained by subtracting 1 from Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 2, the sum of the Q2 plus 1 is equal to the product of the Q1 and 2, and the difference of the Q2 minus 1 is equal to the product of the Q3 and 2. Two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are consecutive in the second bit sequence.
In fig. 8, the first bit sequence is composed of 25 bits arranged in sequence, and the first bit sequence includes 25 bitsIs composed of { x }1，x2，...，x25Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the index of the Q2 sequentially arranged second-class bit subsequences. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
As an embodiment, the first subsequence and the second subsequence are any two second-type bit subsequences in the Q2 second-type bit subsequences, the position of the first subsequence in the Q2 second-type bit subsequences is before the second subsequence, and the number of bits included in the second subsequence is not less than the number of bits included in the first subsequence.
As an example, the second class bit sub-sequence of the Q3 second class bit sub-sequence pairs that occurs first in the second bit sequence includes a number of bits of 1.
Example 9
Example 9 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 9.
In embodiment 9, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, and the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, … and 2 times of difference sequentially arranged bits obtained by subtracting 1 from Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 2, the sum of the Q2 plus 1 is equal to the product of the Q1 and 2, and the difference of the Q2 minus 1 is equal to the product of the Q3 and 2. Two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are consecutive in the second bit sequence.
In fig. 9, the first bit sequence is composed of 25 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x25Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the index of the Q2 sequentially arranged second-class bit subsequences. Any one of the Q3 second analog bit-subsequence pairsThe two pairs of second-type bit sub-sequences include two second-type bit sub-sequences of the same length connected by a solid curve, and the sequence number without frame is the index of the Q3 second-type bit sub-sequence pairs.
As an embodiment, the first subsequence and the second subsequence are any two second-type bit subsequences in the Q2 second-type bit subsequences, the position of the first subsequence in the Q2 second-type bit subsequences is before the second subsequence, and the number of bits included in the second subsequence is not greater than the number of bits included in the first subsequence.
As an embodiment, a second class bit subsequence of the Q3 second class bit subsequence pairs that occurs first in the second bit sequence includes the number of bits that is the Q3.
Example 10
Embodiment 10 illustrates a schematic diagram of a relationship between a first bit sequence and a second bit sequence, as shown in fig. 10.
In embodiment 10, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, and the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, … and 2 times of difference sequentially arranged bits obtained by subtracting 1 from Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 1, the sum of the Q2 plus 1 is equal to the product of the Q1 and 2, and the difference of the Q2 minus 1 is equal to the product of the Q3 and 2. The positions of the two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs in the Q2 sequentially arranged second-type bit sub-sequences are consecutive.
In fig. 10, the first bit sequence is composed of 25 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x25Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the index of the Q2 sequentially arranged second-class bit subsequences. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
As an embodiment, the first subsequence and the second subsequence are any two second-type bit subsequences in the Q2 second-type bit subsequences, the position of the first subsequence in the Q2 second-type bit subsequences is before the second subsequence, and the number of bits included in the second subsequence is not less than the number of bits included in the first subsequence.
As an example, the second class bit sub-sequence of the Q3 second class bit sub-sequence pairs that occurs first in the second bit sequence includes a number of bits of 1.
Example 11
Embodiment 11 illustrates a schematic diagram of the relationship between a first bit sequence and a second bit sequence, as shown in fig. 11.
In embodiment 11, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, the first Q1-1 first-class bit subsequences in the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the first-class bit subsequences, the last first-class bit subsequence in the Q1 sequentially arranged first-class bit subsequences consists of P sequentially arranged bits, and P is a positive integer of the difference obtained by subtracting 1 from Q1 which is less than 2 times of the first-class bit subsequence; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 1, the sum of Q2 plus 2 is equal to the product of Q1 and 2, and the difference of Q2 minus 2 is equal to the product of Q3 and 2. Two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are discontinuous in the second bit sequence.
In fig. 11, the first bit sequence is composed of 22 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x22Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the Q2 second bits arranged in sequenceThe indices of the subsequences are # {1, 2,. ang., Q2-1, Q2}, respectively; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the index of the Q2 sequentially arranged second-class bit subsequences. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
Example 12
Example 12 illustrates a schematic diagram of generating a first wireless signal, as shown in fig. 12.
In embodiment 12, the third bit sequence is an input of the channel coding in this application, the first bit sequence is an output of the channel coding, the first bit sequence and the second bit sequence are an input and an output of the first operation in this application, respectively, and the first wireless signal is an output of the second bit sequence after the second bit sequence sequentially passes through a modulation mapper, a layer mapper, a conversion precoder, a precoding, a resource element mapper, and a multicarrier symbol; wherein the conversion precoder is optional.
As one embodiment, the first operation is interleaving.
As one embodiment, the channel coding includes rate matching (rate matching).
As an embodiment, the channel coding is based on polar (polar) coding.
As an embodiment, the channel coding is based on Turbo coding.
As an embodiment, the channel coding is based on LDPC coding.
As an embodiment, the channel coding is based on convolutional coding.
As an embodiment, the third bit sequence includes a positive integer number of sequentially arranged bits.
As an embodiment, the bits in the third bit sequence are sequentially input into the channel encoder corresponding to the channel coding.
As one embodiment, the multicarrier symbol is an OFDM symbol.
As one embodiment, the multicarrier symbol is a DFT-S-OFDM symbol.
As one embodiment, the multicarrier symbol is an FBMC symbol.
Example 13
Embodiment 13 is a block diagram illustrating a configuration of a processing apparatus used in a first node, as shown in fig. 13. In fig. 13, the processing means 1300 in the first node is mainly composed of a first processing module 1301 and a first transmitter module 1302.
In embodiment 13, the first processing module 1301 performs a first operation; the first transmitter module 1302 transmits a first wireless signal.
In embodiment 13, a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2. The second bit sequence is used by the first transmitter module 1302 to generate the first wireless signal.
For one embodiment, the first processing module 1301 further performs channel coding; wherein the first bit sequence is an output of the channel coding.
As an example, the sum of Q2 plus 1 is equal to the product of Q1 and 2.
As an example, the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As an embodiment, the first node is a base station.
As a sub-embodiment of the above embodiment, the first processing module 1301 includes at least one of { transmit processor 416, channel coder/interleaver 477, controller/processor 475, and memory 476} in embodiment 4.
As a sub-embodiment of the above embodiment, the first transmitter module 1302 includes at least one of { antenna 420, transmitter 418, transmit processor 416, channel coder/interleaver 477, controller/processor 475, memory 476} of embodiment 4.
For one embodiment, the first node is a user equipment.
As a sub-embodiment of the above embodiment, the first processing module 1301 includes at least one of { transmit processor 468, channel coder/interleaver 457, controller/processor 459, memory 460, data source 467} in embodiment 4.
As a sub-embodiment of the above embodiment, the first transmitter module 1302 includes at least one of { antenna 452, transmitter 454, transmit processor 468, channel encoder/interleaver 457, controller/processor 459, memory 460, data source 467} of embodiment 4.
Example 14
Embodiment 14 is a block diagram illustrating a processing apparatus used in the second node, as shown in fig. 14. In fig. 14, the processing means 1400 in the second node is mainly composed of a second processing module 1401 and a first receiver module 1402.
In embodiment 14, the second processing module 1401 performs the second operation; the first receiver module 1402 receives a first wireless signal.
In embodiment 14, a first sequence of real numbers and a second sequence of real numbers are an output and an input of the second operation, respectively, and a real number included in the second sequence of real numbers is the same as a real number included in the first sequence of real numbers; the first real number sequence consists of Q1 first-class real number subsequences which are sequentially arranged, and the first Q1-1 first-class real number subsequences in the Q1 first-class real number subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second real number sequence consists of Q2 second-type real number subsequences which are sequentially arranged, the Q2 second-type real number subsequences comprise Q3 second-type real number subsequence pairs, and any one second-type real number subsequence pair in the Q3 second-type real number subsequence pairs comprises two second-type real number subsequences with the same length; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2. The first wireless signal is used by the second processing module 1401 to generate the second real sequence.
As an example, the second processing module 1401 also performs channel decoding; wherein the first real sequence is an input to the channel coding.
As an example, the sum of Q2 plus 1 is equal to the product of Q1 and 2.
As an example, the sum of Q2 plus 2 is equal to the product of Q1 and 2.
As an embodiment, the number of bits included for the second-type real subsequence in the first occurrence of the second real sequence of the Q3 second-type real subsequence pairs is 1.
As one embodiment, the number of bits included for the second-type real subsequence in the first occurrence of the second real sequence of the Q3 pairs of second-type real subsequences is Q3.
As an embodiment, the second node is a user equipment.
As a sub-embodiment of the above embodiment, the second processing module 1401 includes at least one of { receiving processor 456, channel decoding/deinterleaver 458, controller/processor 459, memory 460, data source 467} in embodiment 4.
As a sub-embodiment of the above embodiment, the first receiver module 1402 includes at least one of { antenna 452, receiver 454, receive processor 456, channel decoder deinterleaver 458, controller/processor 459, memory 460, data source 467} in embodiment 4.
As an embodiment, the second node is a user base station.
As a sub-embodiment of the above embodiment, the second processing module 1401 includes at least one of { receiving processor 470, channel decoding deinterleaver 478, controller/processor 475, memory 476} in embodiment 4.
As a sub-embodiment of the above-mentioned embodiments, the first receiver module 1402 includes at least one of { antenna 420, receiver 418, reception processor 470, channel decoding deinterleaver 478, controller/processor 475, and memory 476} of embodiment 4.
Example 15
Embodiment 15 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 15.
In embodiment 15, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, the first Q1-1 first-class bit subsequences in the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the first-class bit subsequences, the last first-class bit subsequence in the Q1 sequentially arranged first-class bit subsequences consists of P sequentially arranged bits, and P is a positive integer of the difference obtained by subtracting 1 from Q1 which is less than 2 times of the first-class bit subsequence; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 1, the sum of Q2 plus 2 is equal to the product of Q1 and 2, and the difference of Q2 minus 2 is equal to the product of Q3 and 2. Two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are discontinuous in the second bit sequence.
In fig. 15, the first bit sequence is composed of 22 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x22Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the Q2Indexes of the sequentially arranged sub-sequences of bits of the second type. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
As an example, for any one of the Q3 pairs of second analog bit-sequence pairs, between which there are Q5 sequentially arranged second analog bit-sequences, the Q5 is the same for all of the Q3 pairs of second analog bit-sequence pairs, the Q5 being a positive integer.
Example 16
Embodiment 16 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 16.
In embodiment 16, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 sequentially arranged first-class bit subsequences, the first Q1-1 first-class bit subsequences in the Q1 sequentially arranged first-class bit subsequences respectively consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the first-class bit subsequences, the last first-class bit subsequence in the Q1 sequentially arranged first-class bit subsequences consists of P sequentially arranged bits, and P is a positive integer of the difference obtained by subtracting 1 from Q1 which is less than 2 times of the first-class bit subsequence; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 1, the sum of Q2 plus 2 is equal to the product of Q1 and 2, and the difference of Q2 minus 2 is equal to the product of Q3 and 2. Two second-type bit sub-sequences in any one of the Q3 second-type bit sub-sequence pairs are consecutive in the second bit sequence.
In fig. 16, the first bit sequence is composed of 22 bits arranged in sequence, and the bits in the first bit sequence are composed of { x }1，x2，...，x22Represents it. The indexes of the Q1 sequentially arranged first-class bit subsequences are # {1, 2,.. multidot., Q1-1, and Q1 }; the indexes of the Q2 sequentially arranged second-class bit subsequences are # {1, 2,. multidot., Q2-1, and Q2 }; the indices of the Q3 second-class bit-subsequence pairs are # {1, 2,.. multidot.q 3}, respectively. The bit sequence in the ellipse of each solid line frame is one of the Q1 bit subsequences of the first type arranged in sequence, and the serial number of the solid line frame is the index of the Q1 bit subsequences of the first type arranged in sequence. The bit sequence in the ellipse of each dashed-line border is one of the Q2 sequentially arranged second-class bit subsequences, and the serial number of the dashed-line border is the index of the Q2 sequentially arranged second-class bit subsequences. Any one of the Q3 second analog bit sub-sequence pairs comprises two second analog bit sub-sequences with the same length, which are connected by a solid curve, and the sequence number without frame is the index of the Q3 second analog bit sub-sequence pairs.
As an embodiment, the first subsequence and the second subsequence are any two second-type bit subsequences in the Q2 second-type bit subsequences, the position of the first subsequence in the Q2 second-type bit subsequences is before the second subsequence, and the number of bits included in the second subsequence is not greater than the number of bits included in the first subsequence.
As an embodiment, a second class bit subsequence of the Q3 second class bit subsequence pairs that occurs first in the second bit sequence includes the number of bits that is the Q3.
Example 17
Example 17 illustrates a schematic diagram of the relationship between the first bit sequence and the second bit sequence, as shown in fig. 17.
In embodiment 17, the first bit sequence and the second bit sequence are input and output of the first operation in the present application, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1, and the last first-class bit subsequence in the Q1 first-class bit subsequences consists of P bits which are sequentially arranged; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; the Q1 is a positive integer greater than 1 and the P is a positive integer no greater than 2 times the difference of Q1 minus 1.
In fig. 17, the first bit sequence corresponds to { x ═ x1,x2,x3,x4,…,x(Q1-1)^2+PZ ^2 where z represents the square of z; the Q1 sequentially arranged first-class bit subsequences are sequentially:
first type bit subsequence # 1: { x1 };
first type bit subsequence # 2: { x2,x3,x4}；
…；
First type bit subsequence # Q1-1:{x(Q1-2)^2+1,x(Q1-2)^2+2,…,x(Q1-1)^2}；
first type bit subsequence # Q1: { x(Q1-1)^2+1,x(Q1-1)^2+2,…,x(Q1-1)^2+P}
As an example, the P is equal to 2 times the difference of Q1 minus 1, 2 times the difference of Q1 minus 1 is equal to Q2, and the difference of Q1 minus 1 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As a sub-embodiment of the above embodiment, the Q3 second analog bit subsequence pairs are:
second-order bit subsequence pair # 1: { x(Q1-1)^2+1}，{x(Q1-1)^2+P}；
Second-order bit subsequence pair # 2: { x(Q1-1)^2+2,x(Q1-2)^2+1}，{x(Q1-1)^2+P-1,x(Q1-1)^2}；
…；
Second-order bit subsequence pair # Q3: { x(Q1-1)^2+(P-1)/2,xQ1^2-3Q1+2,…,x2},{x(Q1-1)^2+(P-1)/2+2,xQ1^2-3Q1+4,…,x4}；
As one example, P is less than or equal to Q1, 2 times the difference of Q1 minus 2 is equal to Q2, and the difference of Q1 minus 2 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second class bit sub-sequence of the Q3 second class bit sub-sequences is 1, 2, 3, …, and Q3 (i.e. sequentially increasing by 1 from 1).
As a sub-embodiment of the above embodiment, the Q3 second analog bit subsequence pairs are:
second-order bit subsequence pair # 1: { x(Q1-1)^2+1}，{x(Q1-1)^2}；
Second analogyBit sequence pair # 2: { x(Q1-1)^2+2,x(Q1-2)^2+1}，{x(Q1-1)^2-1,x(Q1-2)^2(said P is greater than 1); or, { x(Q1-2)^2+2,x(Q1-3)^2+1}，{x(Q1-1)^2-1,x(Q1-2)^2(said P equals 1);
…；
second-order bit subsequence pair # Q3: { x(Q1-1)^2+Q1-1,xQ1^2-3Q1+2,…,x2},{x(Q1-2)^2+Q1-1,x(Q1-2)^2-Q1+3,…,x1(P equals the difference of Q1 minus 1); or, { x(Q1-1)^2+Q1-2,xQ1^2-3Q1+1,…,x5},{x(Q1-2)^2+Q1,x(Q1-3)^2+Q1-1,…,x4(said P equals said Q1); or, { x(Q1-2)^2+Q1-2,x(Q1-3)^2+Q1-3,…,x2},{x(Q1-2)^2+Q1,x(Q1-3)^2+Q1-1,…,x4(the P is less than the difference of Q1 minus 1).
As an example, the P is greater than Q1 and less than 2 times the difference of Q1 minus 1, 2 times the difference of Q1 minus 2 is equal to Q2, and Q1 minus 2 is equal to Q3.
As a sub-embodiment of the above embodiment, the number of bits included in one second-class bit subsequence of the Q3 second-class bit subsequence pairs is Q3 positive integers which are unequal two by two, the Q3 positive integers which are unequal two by two form a first integer set, the first integer set comprises all positive integers from 1 to Q3 except Q8, and the difference obtained by subtracting 1 from 2 times the Q1 and subtracting P from P is equal to the Q8.
It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing relevant hardware through a program, and the program may be stored in a computer readable storage medium, such as a read-only memory, a hard disk or an optical disk. Alternatively, all or part of the steps of the above embodiments may be implemented by using one or more integrated circuits. Accordingly, the module units in the above embodiments may be implemented in a hardware form, or may be implemented in a form of software functional modules, and the present application is not limited to any specific form of combination of software and hardware. User equipment, terminal and UE in this application include but not limited to unmanned aerial vehicle, Communication module on the unmanned aerial vehicle, remote control plane, the aircraft, small aircraft, the cell-phone, the panel computer, the notebook, vehicle-mounted Communication equipment, wireless sensor, network card, thing networking terminal, the RFID terminal, NB-IOT terminal, Machine Type Communication (MTC) terminal, eMTC (enhanced MTC) terminal, the data card, network card, vehicle-mounted Communication equipment, low-cost cell-phone, equipment such as low-cost panel computer. The base station in the present application includes, but is not limited to, a macro cell base station, a micro cell base station, a home base station, a relay base station, a gNB (NR node B), a TRP (Transmitter Receiver Point), and other wireless communication devices.
The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (24)

1. A method in a first node used for wireless communication, comprising:
-performing a first operation;
wherein a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; writing the first bit sequence in a horizontal line mode from the obtuse vertex angle of the triangle to obtain Q1 first-class bit subsequences which are sequentially arranged; reading from any vertex angle of the triangle to obtain the Q2 second-class bit subsequences which are sequentially arranged; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
2. The method of claim 1, comprising:
-performing channel coding;
wherein the first bit sequence is an output of the channel coding.
3. The method according to claim 1 or 2, comprising:
-transmitting a first wireless signal;
wherein the second bit sequence is used to generate the first wireless signal.
4. The method of claim 1 or 2, wherein the sum of Q2 plus 1 is equal to the product of Q1 and 2.
5. The method of claim 1 or 2, wherein the sum of Q2 plus 2 is equal to the product of Q1 and 2.
6. The method according to claim 1 or 2, characterized in that the first node is a base station; or the first node is a user equipment.
7. A method in a second node used for wireless communication, comprising:
-performing a second operation;
a first real sequence and a second real sequence are respectively an output and an input of the second operation, and real numbers included in the second real sequence are the same as real numbers included in the first real sequence; the first real number sequence consists of Q1 first-class real number subsequences which are sequentially arranged, and the first Q1-1 first-class real number subsequences in the Q1 first-class real number subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second real number sequence consists of Q2 second-type real number subsequences which are sequentially arranged, the Q2 second-type real number subsequences comprise Q3 second-type real number subsequence pairs, and any one second-type real number subsequence pair in the Q3 second-type real number subsequence pairs comprises two second-type real number subsequences with the same length; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences; writing the second real number sequence from any vertex angle of the triangle to obtain the Q2 second real number subsequences which are sequentially arranged; reading out the real number subsequence of the first type from the obtuse vertex angle of the triangle in a horizontal line mode to obtain the Q1 sequentially arranged real number subsequences of the first type; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
8. The method of claim 7, comprising:
-performing channel decoding;
wherein the first real sequence is an input to the channel coding.
9. The method according to claim 7 or 8, comprising:
-receiving a first wireless signal;
wherein the first wireless signal is used to generate the second real sequence.
10. The method of claim 7 or 8, wherein the sum of Q2 plus 1 is equal to the product of Q1 and 2.
11. The method of claim 7 or 8, wherein the sum of Q2 plus 2 is equal to the product of Q1 and 2.
12. The method according to claim 7 or 8, wherein the second node is a user equipment; or the second node is a base station.
13. An apparatus in a first node for wireless communication, comprising:
the first processing module executes a first operation;
wherein a first bit sequence and a second bit sequence are input and output of the first operation, respectively, and bits included in the second bit sequence are the same as bits included in the first bit sequence; the first bit sequence consists of Q1 first-class bit subsequences which are sequentially arranged, and the first Q1-1 first-class bit subsequences in the Q1 first-class bit subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second bit sequence consists of Q2 second-class bit subsequences which are arranged in sequence, the Q2 second-class bit subsequences comprise Q3 second-class bit subsequence pairs, and any one of the Q3 second-class bit subsequence pairs comprises two second-class bit subsequences with the same length; at most one bit in any one of the Q2 sequentially arranged second-class bit subsequences belongs to any one of the Q1 sequentially arranged first-class bit subsequences; writing the first bit sequence in a horizontal line mode from the obtuse vertex angle of the triangle to obtain Q1 first-class bit subsequences which are sequentially arranged; reading from any vertex angle of the triangle to obtain the Q2 second-class bit subsequences which are sequentially arranged; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
14. The apparatus in the first node according to claim 13, wherein the first processing module performs channel coding; wherein the first bit sequence is an output of the channel coding.
15. An arrangement in a first node according to claim 13 or 14, comprising:
a first transmitter module that transmits a first wireless signal;
wherein the second bit sequence is used to generate the first wireless signal.
16. An arrangement in a first node according to claim 13 or 14, characterised in that the sum of Q2 plus 1 equals the product of Q1 and 2.
17. An arrangement in a first node according to claim 13 or 14, characterised in that the sum of Q2 plus 2 equals the product of Q1 and 2.
18. An arrangement in a first node according to claim 13 or 14, characterised in that the first node is a base station; or the first node is a user equipment.
19. An apparatus in a second node for wireless communication, comprising:
the second processing module executes a second operation;
a first real sequence and a second real sequence are respectively an output and an input of the second operation, and real numbers included in the second real sequence are the same as real numbers included in the first real sequence; the first real number sequence consists of Q1 first-class real number subsequences which are sequentially arranged, and the first Q1-1 first-class real number subsequences in the Q1 first-class real number subsequences consist of 1, 3, …, 2 times of Q1 and a difference obtained by subtracting 3 from the Q1; the second real number sequence consists of Q2 second-type real number subsequences which are sequentially arranged, the Q2 second-type real number subsequences comprise Q3 second-type real number subsequence pairs, and any one second-type real number subsequence pair in the Q3 second-type real number subsequence pairs comprises two second-type real number subsequences with the same length; at most one real number in any one of the Q2 sequentially-arranged second-type real number subsequences belongs to any one of the Q1 sequentially-arranged first-type real number subsequences; writing the second real number sequence from any vertex angle of the triangle to obtain the Q2 second real number subsequences which are sequentially arranged; reading out the real number subsequence of the first type from the obtuse vertex angle of the triangle in a horizontal line mode to obtain the Q1 sequentially arranged real number subsequences of the first type; the Q1 and the Q2 are each positive integers greater than 1, the Q3 is a non-negative integer less than the Q2.
20. The apparatus in the second node according to claim 19, wherein the second processing module performs channel coding; wherein the first real sequence is an input to the channel coding.
21. An arrangement in a second node according to claim 19 or 20, comprising:
a first receiver module to receive a first wireless signal;
wherein the first wireless signal is used to generate the second real sequence.
22. An arrangement in a second node according to claim 19 or 20, characterised in that the sum of Q2 plus 1 equals the product of Q1 and 2.
23. An arrangement in a second node according to claim 19 or 20, characterised in that the sum of Q2 plus 2 equals the product of Q1 and 2.
24. An arrangement in a second node according to claim 19 or 20, characterised in that the second node is a user equipment; or the second node is a base station.
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