CN109493892B

CN109493892B - Buffer device, memory module including the same, and memory system including the same

Info

Publication number: CN109493892B
Application number: CN201810966711.2A
Authority: CN
Inventors: 李将雨; 任政炖; 郑秉勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-09-13
Filing date: 2018-08-23
Publication date: 2023-10-03
Anticipated expiration: 2038-08-23
Also published as: SG10201805698YA; KR102365110B1; US10824575B2; US20190079699A1; CN109493892A; KR20190030030A

Abstract

The present application provides a buffer device including a structure for performing a training operation on a plurality of memory devices to ensure data reliability, and a memory module and a memory system including the buffer device. The memory controller is configured to control a memory operation to the plurality of memory devices. The memory module includes a plurality of memory devices and a buffer device connected between the memory devices and the memory controller. The buffer device performs a training operation on the memory device, the buffer device includes a training block having a signal delay circuit, and the memory controller performs the training operation by controlling the training block.

Description

Buffer device, memory module including the same, and memory system including the same

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2017-017232 filed in the korean intellectual property office on 13/9/2017, the disclosure of which is incorporated herein by reference.

Technical Field

The present inventive concept relates to a memory system performing a training operation on a plurality of memory devices, and more particularly, to a buffer device supporting a training operation on a plurality of memory devices, and a memory module and a memory system each including the same.

Background

Memory systems for writing and reading large amounts of data have been under development due to the development of memory technology. In this case, the plurality of memory devices are connected to a memory controller included in the memory system so as to control a storage operation including a write operation and a read operation. However, in a structure in which a plurality of memory devices are connected to one memory controller, the memory controller has a high output impedance, and thus, a signal output from the memory controller is insufficient to reach the plurality of memory devices.

In such a memory system, a buffer device may be connected between the memory controller and the plurality of memory devices. The buffer device may drive a signal received from the memory controller and send the driven signal to the memory device with sufficient signal strength.

The memory controller performs a training operation on the memory device after power-up to compensate for timing of at least one of a data signal (or DQ signal) sent via the data DQ line and a data strobe signal (or DQs signal) sent via the data strobe DQs line to establish optimal calibration conditions and control the memory operation.

In this way, research has been conducted to provide a memory system including a buffer device in which a training operation can be efficiently performed on a plurality of memory devices.

Disclosure of Invention

Embodiments of the inventive concept provide a memory module in which a training operation can be effectively performed on a plurality of memory devices using a buffer device, and a memory system including the same.

According to an embodiment of the inventive concept, there is provided a memory system including: a memory module including a plurality of memory devices; a memory controller configured to control a memory operation to a plurality of memory devices; and a buffer device connected between the memory device and the memory controller, the buffer device including a training block configured to perform training operations on the plurality of memory devices; wherein the memory controller is configured to control the training block to perform the training operation.

According to an embodiment of the inventive concept, there is provided a memory system including: a memory controller configured to control a memory operation to a plurality of memory devices; and a memory module including a plurality of memory devices and a buffer device connected between the plurality of memory devices and the memory controller, wherein the buffer device includes a training block configured to perform a training operation on the plurality of memory devices, and the training block performs the training operation using first training data and a first data strobe signal, both of which are received from a target memory device for the training operation among the plurality of memory devices, and the training block timing generates first timing compensation information for reference by the buffer device during a timing compensation operation for signals related to the memory operation transmitted/received for the plurality of memory devices.

According to an embodiment of the inventive concept, there is provided a memory module including: a plurality of memory devices; and a plurality of buffer devices configured to route signals to and from the plurality of memory devices, wherein the plurality of buffer devices comprises: a first sub-buffer device connected to a first memory device of the plurality of memory devices; a second sub-buffer device connected to a second memory device of the plurality of memory devices; and a main buffer device connected to the first sub buffer device and the second sub buffer device, and configured to perform a first training operation on the first sub buffer device and the second sub buffer device, the first sub buffer device configured to perform a second training operation on the first memory device, and the second sub buffer device configured to perform a third training operation on the second memory device. The first training operation, the second training operation, and the third training operation include generating timing compensation information for one or more of a read training operation and a write training operation.

According to an embodiment of the inventive concept, there is provided a semiconductor package including: a buffer layer configured to communicate with the memory controller; at least one memory layer stacked on the buffer layer and including at least one memory core; and at least one Through Silicon Via (TSV) passing through the at least one memory layer, wherein the buffer layer includes a training block having a signal delay circuit, and the training block is configured to perform a training operation on at least one memory core of the memory layer, and the memory controller controls a delay degree of the signal delay circuit for the training operation to be performed.

According to an embodiment of the inventive concept, there is provided a semiconductor package including: a buffer layer configured to route signals between the memory controller and the memory core; at least one memory layer stacked on the buffer layer and including at least one memory core; and at least one Through Silicon Via (TSV) passing through the at least one memory layer, wherein the buffer layer performs a training operation on the at least one memory core of the at least one memory layer and generates timing compensation information for transmitting/receiving signals between the buffer layer and the at least one memory layer according to the at least one memory core.

According to an embodiment of the inventive concept, there is provided a method of manufacturing a semiconductor package including a memory system having a structure configured to perform a training operation, the method including: forming a memory system as part of a semiconductor package, the memory system including one or more memory chips having a memory cell array, a memory controller, and a buffer chip for routing transmission/reception signals between the one or more memory chips and the memory controller, and the buffer chip including a training block having a decision circuit that determines a degree of timing compensation of signals transmitted and received between the buffer chip and the memory chip; and the buffer chip performs training operations on the one or more memory chips independent of the memory controller.

According to an embodiment of the inventive concept, training operations between a buffer chip and a memory controller and between one or more memory chips and the buffer chip are performed simultaneously.

According to an embodiment of the inventive concept, training operations between a buffer chip and a memory controller and between one or more memory chips and the buffer chip are performed overlapping each other.

According to an embodiment of the inventive concept, there is provided a method of manufacturing a semiconductor package including a memory system having a structure configured to perform a training operation, the method including: forming a memory system as part of a semiconductor package, the memory system including one or more memory chips having a memory cell array, a memory controller, and a buffer chip for routing transmit/receive signals between the one or more memory chips and the memory controller; and performing a training operation on the buffer chip by the memory controller, and then performing the training operation on one or more memory chips using the buffer chip under the control of the memory controller.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a memory system according to an embodiment of the inventive concept;

FIG. 2 is a flowchart illustrating performing a training operation in the memory system of FIG. 1, according to an embodiment of the inventive concept;

fig. 3A and 3B are block diagrams showing a read training operation performed on a buffer apparatus, and fig. 3C and 3D are block diagrams showing a write training operation performed on a buffer apparatus;

Fig. 4A and 4B are block diagrams illustrating read training operations performed on a plurality of memory devices using a training block of a buffer device, and fig. 4C and 4D are block diagrams illustrating write training operations performed on a plurality of memory devices using a training block of a buffer device;

FIG. 5 is a flowchart illustrating performing a training operation in the memory system of FIG. 1, according to an embodiment of the inventive concept;

fig. 6A to 6C are block diagrams showing a read training operation of the memory device by the buffer device, and fig. 6D and 6E are block diagrams for explaining a write training operation of the memory device by the buffer device;

fig. 7 is a block diagram illustrating a training operation of a memory device when a buffer device according to an embodiment of the inventive concept supports a timing adjustment function;

fig. 8A and 8B are diagrams showing the configuration and operation of the timing adjustment controller of the buffer apparatus.

FIG. 9 is a block diagram illustrating a memory controller performing a training operation on a buffer device, wherein the buffer device generates timing compensation information, according to an embodiment of the inventive concept;

fig. 10A and 10B are block diagrams illustrating a training operation of a memory bank by a buffer apparatus generating timing compensation information according to an embodiment of the inventive concept;

FIG. 11 is a block diagram of a memory system according to an embodiment of the inventive concept;

FIG. 12 is a block diagram of a method of memory operation of a memory system according to an embodiment of the inventive concept;

FIGS. 13A and 13B are diagrams illustrating an embodiment of the memory device of FIG. 1;

FIG. 14 is a block diagram of a memory system according to an embodiment of the inventive concept;

fig. 15 is a block diagram of a semiconductor package having a stacked structure including a plurality of layers according to an embodiment of the inventive concept; and

fig. 16 is a diagram of a semiconductor package including stacked semiconductor chips according to an embodiment of the inventive concept;

fig. 17 is a flowchart illustrating a method of manufacturing a semiconductor package having a buffer chip configuration according to an embodiment of the inventive concept.

Detailed Description

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram schematically illustrating a memory system 100 according to an embodiment of the inventive concept.

Referring now to FIG. 1, a memory system 100 may include a memory controller 120 and a memory module MM. The memory module MM may include a buffer device 140 (or buffer chip) and a plurality of memory devices 160 (or memory chips). The buffer device 140 may be connected between the memory controller 120 and the plurality of memory devices 160. The buffer device 140 may provide, among other things, impedance matching such that signals output from the memory controller 120 are provided to a plurality of memory devices with sufficient strength.

Memory controller 120 may control the storage operation of a plurality of memory devices 160. In more detail, the memory controller 120 may transmit signals including an address signal ADDR, a command CMD, and DATA to the memory module MM via predetermined DATA DQ lines. The buffer device 140 may receive the address signal ADDR, the command CMD, and the DATA and route these signals to the memory device 160. In an embodiment, the address signal ADDR may include a selection signal (e.g., a chip enable signal) for the memory device 160, and the buffer device 140 may route the address signal ADDR, the command CMD, and the DATA to the memory device corresponding to the selection signal. The memory device 160 may receive signals including an address signal ADDR, a command CMD, and DATA related to a storage operation from the buffer device 140, and perform a storage operation including a write operation and a read operation based on the signals related to the storage operation.

Hereinafter, a signal transmitted via a data DQ line between the memory controller 120 and the memory module MM or a data DQ line between the buffer device 140 and each memory device 160 is referred to as a data signal. Further, a signal transmitted via the data strobe DQS line between the memory controller 120 and the memory module MM or the data strobe DQS line between the buffer device 140 and each memory device 160 is referred to as a data strobe signal.

With continued reference to fig. 1, the memory device 160 may include a memory cell array (not shown) and the memory cell array may include a plurality of memory cells disposed in regions where a plurality of word lines and a plurality of bit lines cross each other.

In embodiments of the inventive concept, the plurality of memory cells included in each memory device 160 may include volatile memory cells or nonvolatile memory cells. For example, the plurality of memory cells may be nonvolatile memory cells (e.g., flash memory, resistive Read Access Memory (RAM), phase change RAM (PRAM), or Magnetic RAM (MRAM)) or may further be volatile memory cells (e.g., dynamic RAM (DRAM)).

The memory controller 120 according to an embodiment of the inventive concept may include a Training Control Unit (TCU), and the buffer device 140 may include a Training Block (TB). In an embodiment, the Training Control Unit (TCU) includes circuitry configured for operation, which may control the training operation of the buffer device 140. For example, the buffer device 140 may further include a buffer memory 141 for temporarily storing signals received from the memory controller 120 or buffering. Accordingly, a training operation for the buffer apparatus 140 may be performed. The TCU may perform training operations on the buffer device 140 so that the memory controller 120 may determine a timing compensation degree for signals transmitted to the buffer device 140 and a timing compensation degree for signals received from the buffer device 140. Fig. 3A to 3D will provide a detailed description.

The timing compensation operation of the signal, which will be described later herein, may be interpreted as an operation of delaying the signal using a delay circuit or the like. For example, the timing compensation degree may be understood to correspond to, for example, a delay degree.

According to an embodiment of the inventive concept, the training operation of the memory device 160 may be differently performed according to various configurations of the training block TB.

For example, in an embodiment, the training block TB may not include a decision circuit configured to determine a timing compensation degree for a signal transmitted by the buffer device 140 to the memory controller 160 and a timing compensation degree for a signal received from the memory device 160. If the training block TB does not include decision circuitry, the TCU may perform training operations on the memory device 160 by controlling the training block TB. An exemplary description of these operations will be provided with the descriptions of fig. 4A through 4D.

Conversely, when the training block TB includes the decision circuit, the training block TB may perform the training operation of the memory device 160 and the training operation of the buffer device 140 by the memory controller 120 in parallel. Fig. 6A to 6D will provide a detailed description of these operations.

In fig. 1, a training block TB of the buffer device 140 and the TCU of the memory controller 120 are elements for performing a training operation. However, embodiments of the inventive concept are not limited thereto, and of course, at least one element included in the TCU and at least one element included in the training block TB may be used when performing a storage operation on the memory system 100. Further, each of the TCU and the training block TB may be a hardware block comprising analog circuitry and/or digital circuitry, or a software block comprising a plurality of instructions executed by the memory controller 120 or the buffer device 140.

Accordingly, the memory system 100 according to the present inventive concept uses the buffer device 140 when performing a training operation on the plurality of memory devices 160, so that the reliability of the training operation can be improved.

Fig. 2 is a flowchart illustrating a training operation performed in the memory system 100 of fig. 1 according to an embodiment of the inventive concept. Hereinafter, a case where the training block TB does not include an element such as a decision circuit will be assumed and described. In this embodiment, a training operation is performed on both the buffer device and the memory device using the memory controller.

Referring now to fig. 1 and 2, the memory controller 120 may perform a training operation on the buffer device 140 at operation S100. For example, for the memory controller 120 to perform a training operation on the memory device 160 using the training block TB of the buffer device 140, first, signal calibration (e.g., calibration between a data signal and a data strobe signal) between the memory controller 120 and the buffer device 140 is optimized. Accordingly, the memory controller 120 may perform a training operation on the buffer device 140 before starting the training operation on the memory device 160 using the training block TB, and may determine a timing compensation degree for a signal transmitted from the memory controller 120 to the buffer device 140 and a timing compensation degree for a signal received from the buffer device 140. The memory controller 120 may store timing compensation information indicating the determined timing compensation degree in a predetermined memory area (e.g., a register).

At operation S120, the memory controller 120 may perform a training operation on the memory device 160 using the buffer device 140 after performing the training operation on the buffer device 140. In detail, the memory controller 120 performs a training operation on the memory device 160 using the training block TB, so that the timing compensation degree can be determined for the signal transmitted to the memory device 160 by the buffer device 140 and the timing compensation degree can be determined for the signal received from the memory device 160. The memory controller 120 may transmit timing compensation information indicating the determined degree of timing compensation to the buffer device 140, and the buffer device 140 may store the timing compensation information in a predetermined memory area (e.g., the buffer memory 141 or a register).

At operation S140, a storage operation may be performed on the plurality of memory devices 160 based on the result of the training operation sequentially performed. The memory operation is performed based on timing compensation information determined based on training operations performed on the buffer device and the memory device. In detail, during a storage operation, an offset between signals generated in a high frequency operation is reduced by performing timing compensation on the signals by referring to timing compensation information generated as a result of performing a training operation.

Fig. 3A and 3B are block diagrams showing a read training operation performed on the buffer apparatus 240, and fig. 3C and 3D are block diagrams for explaining a write training operation performed on the buffer apparatus 240.

Referring to fig. 3A, a memory system 200 according to an embodiment of the inventive concept may include a memory controller 220 and a memory module MM, and the memory module MM may include at least one buffer device 240. As described above, the memory controller 220 may include a Training Control Unit (TCU), and the TCU may include a pattern data generator 221 for generating arbitrary pattern data (or pattern sequence).

The TCU may transmit the first pattern data pt_d1 (generated by the pattern data generator 221) to the buffer device 240 via the data signal line. The TCU may divide the data strobe signal DQS with a sufficiently low frequency _FL Is transmitted to the buffer device 240 at which no mismatch occurs due to an offset from the transmitted first pattern data pt_d1. The buffer device 240 may use the data strobe signal DQS _FL For the first mode numberThe sampling is performed according to pt_d1 to write the first pattern data pt_d1 to the buffer memory 241.

Referring now to fig. 3b, the tcu may include a sampling circuit 222, a comparison circuit 223, a delay adjustment circuit 224, and a signal delay circuit 225. As previously described in fig. 3A, the buffer device 240 may transmit a signal generated in response to sampling the first pattern data pt_d1. For example, as shown in fig. 3B, the buffer device 240 may transmit the first read training data rt_d1 to the sampling circuit 222 and the high frequency data strobe signal DQS to the signal delay circuit 225. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the read operation.

The sampling circuit 222 may receive the delayed data strobe signal d_dqs from the signal delay circuit 225, and may SAMPLE the first read training data rt_d1 using the delayed data strobe signal d_dqs to generate the first sampling data sample_d1. The comparison circuit 223 may compare the first pattern data pt_d1 with the first sampling data sample_d1, thereby generating a first comparison result com_r1. The delay adjustment circuit 224 may generate a first delay control signal d_cs1 for controlling the degree of delay of the signal delay circuit 225 based on the first comparison result com_r1. The signal delay circuit 225 may change a delay degree of delaying the data strobe signal DQS based on the first delay control signal d_cs1.

The TCU may perform operations through the correspondingly named components in fig. 3A and 3B as part of repeating read training operations on the buffer device 240 a plurality of times. The delay adjusting circuit 224 may generate the first timing compensation information (TCI 1) based on the first comparison result com_r1. The first timing compensation information TCI1 generated by performing the read training operation on the buffer device 240 may be information indicating an optimal degree of timing compensation for at least one of the data signal and the data strobe signal received from the buffer device 240 by the memory controller 220. In an example, when the data signal and the data strobe signal are received from the buffer device 240, the memory controller 220 may perform a read operation after compensating for the timing of the data strobe signal based on the first timing compensation information TCI1 that may be stored in the register 227.

Referring now to fig. 3c, the tcu may transmit the second mode data pt_d2 to the buffer device 240 via the data signal line. The TCU may provide the high frequency data strobe signal DQS to the buffer device 240 via the data strobe signal line. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation. The buffer device 240 may sample the second mode data pt_d2 using the data strobe signal DQS. The buffer device 240 may then write the second mode data pt_d2 to the buffer memory 241.

Referring now to fig. 3D, the TCU may also include compensation circuitry 226 as compared to fig. 3B. The buffer device 240 may transmit a signal generated by sampling the second pattern data pt_d2 as the second write training data wt_d2 to the sampling circuit 222, as shown in fig. 3C. In addition, the buffer device 240 may transmit the data strobe signal DQS to the compensation circuit 226. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation.

The compensation circuit 226 may compensate the timing of the data strobe signal DQS by referring to the first timing compensation information TCI 1 to generate a compensated data strobe signal c_dqs. The sampling circuit 222 may SAMPLE the second write training data wt_d2 using the compensated data strobe signal c_dqs to generate second sampling data sample_d2. The comparison circuit 223 may compare the second pattern data pt_d2 with the second sampling data sample_d2, thereby generating a second comparison result com_r2. The delay adjusting circuit 224 may generate the second delay control signal d_cs2 for controlling the degree of delay of the signal delay circuit 225 based on the second comparison result com_r2. The signal delay circuit 222 may change a delay degree based on the second delay control signal d_cs2, may delay the data strobe signal DQS, and may transmit the delayed data strobe signal d_dqs to the buffer device 240 via the data strobe signal line.

The TCU may perform the operational loops described in fig. 3C and 3D as part of a write training operation to the buffer device 240 multiple times. The delay adjusting circuit 224 may generate the second timing compensation information TCI2 based on the second comparison result com_r2. The second timing compensation information TCI2 generated as a result of performing the write training operation on the buffer apparatus 240 may be stored in the register 227 and may be information indicating an optimal timing compensation degree for at least one of the data signal and the data strobe signal transmitted to the buffer apparatus 240. In an example, the memory controller 220 may compensate the timing of the data strobe signal by referring to the second timing compensation information TCI2 before transmitting the data signal and the data strobe signal for the write operation to the buffer device 240, and may then transmit the data signal and the compensated data strobe signal, thereby performing the write operation.

Fig. 4A and 4B are block diagrams for explaining a read training operation performed on the plurality of memory devices 260 using the training block TB of the buffer device 240, and fig. 4C and 4D are block diagrams for explaining a write training operation performed on the plurality of memory devices 260 using the training block TB of the buffer device 240.

As shown in fig. 2 and the like, it is assumed that the training operation for the memory device 260 is performed after the training operation for the buffer device 240 has been completed.

Referring now to fig. 4A, a memory system 200 may include a memory controller 220 and a memory module MM, and the memory module MM may include at least one buffer device 240 and at least one memory device 260. Hereinafter, a training operation performed on the memory device 260 selected as a training object among the plurality of memory devices will be described, and a training method to be described later may also be used in other memory devices. The memory device may be selected as a training object by the memory controller 220 or the buffer device 240. For example, the memory controller 220 may send a selection signal for a memory device to the memory module MM to select the memory device as a training object. In other examples, when receiving a signal related to a training operation (e.g., a training command), buffer device 240 may sequentially select one or more memory devices from a plurality of memory devices in a predetermined order as a training object.

The buffer means 240 may comprise a training block TB. The training block TB may include a pattern data generator 242 for generating arbitrary pattern data (or pattern sequence). However, it should be understood by those skilled in the art that other embodiments of the inventive concept are not limited to generating any pattern data. For example, predetermined pattern data generated by the pattern data generator 242 included in the TCU of the memory controller 220 may be received and used.

The training block TB may transmit the third pattern data pt_d3 generated by the pattern data generator 242 to the memory device 260 via the data signal line. The training block TB may apply the data strobe signal DQS _FL Is sent to the memory device 260 via the data strobe signal line. Data strobe signal DQS _FL Has a sufficiently low frequency at which no mismatch occurs due to an offset from the transmitted third pattern data pt_d3. In an embodiment of the inventive concept, the training block TB may divide the data strobe signal DQS' received from the memory controller 220 to generate a low frequency data strobe signal DQS _FL . However, the above is an embodiment of the inventive concept, and the scope of the inventive concept is not limited thereto. The buffer device 240 may include an additional clock generator or may receive a clock signal from an additional clock source. The memory device 260 may use the data strobe signal DQS _FL The third pattern data pt_d3 is sampled to write the third pattern data pt_d3 to the memory cell array 262.

Referring to fig. 4B, the training block TB may further include a sampling circuit 243 and a signal delay circuit 244. The memory device 260 may transmit a signal generated by sampling the third pattern data pt_d3 as the third read training data rt_d3 to the sampling circuit 243, and may transmit the high frequency data strobe signal DQS to the signal delay circuit 244, as described in fig. 4B. In an example, the data strobe signal DQS of fig. 4B may have the same frequency as the data strobe signal used in the read operation.

The sampling circuit 243 may receive the delayed data strobe signal d_dqs from the signal delay circuit 244 and may generate the third sampling data sample_d3 using the delayed data strobe signal d_dqs. Subsequently, the training block TB may transmit the third sampling data sample_d3 and the third pattern data pt_d3 to the TCU of the memory controller 220. Since the training operation is completed between the memory controller 220 and the buffer device 240, the TCU can precisely receive the third sampling data sample_d3 and the third pattern data pt_d3, and only the core operation of the TCU will be described hereinafter.

The TCU may include a comparison circuit 223 and a delay adjustment circuit 224. The comparison circuit 223 may compare the third pattern data pt_d3 with the third sampling data sample_d3, thereby generating a third comparison result com_r3. The delay adjustment circuit 224 may generate a delay control signal d_cs3 for controlling the degree of delay of the signal delay circuit 244 of the training block TB based on the third comparison result com_r3. The TCU may send a third delay control signal d_cs3 to the training block TB. As described above, since the training operation is completed between the memory controller 220 and the buffer device 240, the training block TB can accurately receive the delay control signal d_cs3. The signal delay circuit 244 may change a delay degree based on the third delay control signal d_cs1, thereby delaying the data strobe signal DQS.

The training blocks TB and TCU may perform the operations described in fig. 4A and 4B as part of a read training operation that is repeated multiple times for the memory device 260. The delay adjusting circuit 224 may generate the third timing compensation information TCI3 based on the third comparison result com_r3. The third timing compensation information TCI3 generated as a result of performing the read training operation on the memory device 260 may be information indicating an optimal degree of timing compensation for at least one of the data signal and the data strobe signal received from the memory device 260 by the buffer device 240, and the timing compensation information TCI3 may be stored in the register 246. In an example, when the data signal and the data strobe signal are received from the memory device 260, the buffer device 240 may compensate the timing of the data strobe signal by referring to the third timing compensation information TCI3 and then perform a read operation.

Referring to fig. 4C, the training block TB may transmit the fourth mode data pt_d4 to the memory device 260 via the data signal line. The training block TB may supply the high-frequency data strobe signal DQS to the memory device 260 via the data strobe signal line. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation. In addition, the training block TB may generate the data strobe signal DQS using the data strobe signal DQS' received from the memory controller 220. It will be appreciated and understood by those of ordinary skill in the art that embodiments of the inventive concept are not limited to the examples described above. The buffer device 240 may include an additional clock generator or may receive a clock signal from an additional clock source.

Referring now to fig. 4D, the training block TB may further include a compensation circuit 245 not shown in the training block TB of fig. 4B. As illustrated in fig. 4C, the memory device 260 may supply a signal generated by sampling the fourth pattern data pt_d4 as the fourth write training data wt_d4 to the sampling circuit 243, and may transmit the high frequency data strobe signal DQS to the compensation circuit 245. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation.

The compensation circuit 245 may compensate the timing of the data strobe signal DQS by referring to the third timing compensation information TCI3, thereby generating a compensated data strobe signal c_dqs. The sampling circuit 243 may SAMPLE the fourth write training data wt_d4 using the compensated data strobe signal c_dqs to generate fourth sampling data sample_d4. Subsequently, the training block TB may transmit the fourth sampling data sample_d4 and the fourth pattern data pt_d4 to the TCU.

The comparison circuit 223 of the TCU may compare the fourth pattern data pt_d4 with the fourth sampling data sample_d4 to generate a fourth comparison result com_r4. The delay adjustment circuit 224 may generate a fourth delay control signal d_cs4 for controlling the degree of delay of the signal delay circuit 244 of the training block TB based on the fourth comparison result com_r4. The TCU may send a fourth delay control signal d_cs4 to the training block TB. The signal delay circuit 244 may change a delay degree based on the fourth delay control signal d_cs4, may delay the data strobe signal DQS, and may provide the delayed data strobe signal d_dqs to the buffer device 260 via the data strobe signal line.

The training blocks TB and TCU may perform the operations of the configuration shown in fig. 4C and 4D as part of a write training operation that is repeated multiple times on the memory device 260. The delay adjusting circuit 224 may generate the fourth timing compensation information TCI4 based on the fourth comparison result com_r4. The fourth timing compensation information TCI4 generated as a result of performing the write training operation on the memory device 260 may be, for example, information indicating an optimal timing compensation degree for at least one of the data signal and the data strobe signal transmitted to the memory device 260 by the buffer device 240. In an example, the buffer device 240 may perform the write operation by compensating the timing of the data strobe signal transmitted to the memory device 260 by referring to the fourth timing compensation information TCI4 and then transmitting the compensated data strobe signal and data signal to the memory device 260.

Accordingly, the buffer device 240 according to an embodiment of the inventive concept includes a minimum training block TB that can support a training operation on the memory device 260, so that the memory controller 220 can perform an efficient training operation on the memory device 260 using the buffer device 240. In addition, the size of the buffer device 240 may be minimized.

Fig. 5 is a flowchart illustrating a training operation performed in the memory system 100 of fig. 1 according to an embodiment of the inventive concept. Hereinafter, a case where the training block TB includes elements such as a decision circuit will be assumed and described.

Referring now to fig. 1 and 5, the memory controller 120 may perform a training operation on the buffer apparatus 140 at operation S200. Concurrently with the training operation of the buffer apparatus 140, the buffer apparatus 140 may perform the training operation on the memory apparatus 160 at operation S220. The reason why the training operation can be performed simultaneously is that, unlike the configuration shown in fig. 2, the buffer device 140 can determine the timing compensation degree of the signal to be transmitted to the memory device 160 and the timing compensation degree of the signal to be received from the memory device 160 (e.g., to and from the memory device). Thus, the training operation of the buffer device 140 to the memory device 160 and the training operation of the memory controller 120 to the buffer device 140 may be performed in parallel.

Subsequently, at operation S240, a storage operation may be performed on the memory device 160 based on the result of the training operation performed in parallel.

Fig. 6A to 6C are block diagrams showing a read training operation of the buffer device 340 on the memory device 360, and fig. 6D and 6E are block diagrams for explaining a write training operation of the buffer device 340 on the memory device 360.

As described in the foregoing paragraphs discussing the flowchart of fig. 5, the training operation of the buffer device 340 on the memory device 360 may be performed simultaneously with the training operation of the memory controller 320 on the buffer device 340, and the training operation of the memory controller 320 on the buffer device 340 has been described in detail with reference to fig. 3A to 3D, so a description thereof will be omitted.

Referring now to fig. 6A, a memory module 300 may include a buffer device 340 and a memory device 360. The buffer device 340 may include a training block TB, and the training block TB may include a pattern data generator 342 and a clock generator 349. The memory device 360 may include a memory cell array 362 that writes/reads predetermined data.

The training block TB may transmit the third pattern data pt_d3 generated by the pattern data generator 342 to the memory device 360 via the data signal line. The training block TB may transmit the data strobe signal DQS with a sufficiently low frequency to the memory device 360 _FL At this frequency, mismatch does not occur due to an offset from the transmitted third pattern data pt_d3. In embodiments of the inventive concept, the training block TB may divide the clock signal generated by the clock generator 349 to generate a low frequency data strobe signal DQS _FL . The memory device 360 may use the data strobe signal DQS _FL The third pattern data pt_d3 is sampled to write the third pattern data pt_d3.

In another embodiment of the inventive concept, referring to fig. 6B, the training block TB may not include the clock generator 349 and may receive the data strobe signal DQS' from the memory controller or the clock signal clk_ext from an external clock source. Thus, the buffer device 340 may receive the data strobe signal DQS 'or the clock signal clk_ext from the outside, and may perform a training operation on the memory device using the data strobe signal DQS' or the clock signal clk_ext.

Referring now to fig. 6C, the training block TB may further include a sampling circuit 343, a comparing circuit 346, a delay adjusting circuit 347, and a signal delay circuit 344. As illustrated in fig. 6A, the memory device 360 may supply a signal generated by sampling the third pattern data pt_d3 as the third read training data rt_d3 to the sampling circuit 343, and may transmit the high frequency data strobe signal DQS. In an example, the data strobe signal DQS of fig. 6C may have the same frequency as the data strobe signal used in the read operation.

The sampling circuit 343 may receive the delayed data strobe signal d_dqs from the signal delay circuit 344 and may SAMPLE the third read training data rt_d3 using the delayed data strobe signal d_dqs to generate third sampling data sample_d3. The comparison circuit 346 may compare the third pattern data pt_d3 with the third sampling data sample_d3 to generate a third comparison result com_r3. The delay adjustment circuit 347 may generate a third delay control signal d_cs3 for controlling the degree of delay of the signal delay circuit 344 based on the third comparison result com_r3. The signal delay circuit 344 may change a delay degree based on the third delay control signal d_cs3 to delay the data strobe signal DQS.

The training block TB may perform the operations described in fig. 6A through 6C as part of a read training operation that is repeated multiple times for the memory device 360. The delay adjusting circuit 347 may generate the third timing compensation information TCI3 based on the third comparison result com_r3, and the third timing compensation information TCI3 may be stored in the register 345. The description of the third timing compensation information TCI3 is the same as that described above, and thus a detailed description thereof will be omitted.

Referring now to fig. 6D, the training block TB may transmit the fourth mode data pt_d4 to the memory device 360 via the data signal line. The training block TB may supply the high-frequency data strobe signal DQS to the memory device 360 via the data strobe signal line. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation. The memory device 360 may sample the fourth mode data pt_d4 using the data strobe signal DQS to write the fourth mode data pt_d4 to the memory cell array 362.

Referring now to fig. 6E, training block TB may also include compensation circuit 348 (as compared to fig. 6C). As previously described in fig. 6D, the memory device 360 may transmit a signal generated by sampling the fourth pattern data pt_d4 as the fourth write training data wt_d4 to the sampling circuit 343, and may transmit the high frequency data strobe signal DQS to the compensation circuit 348. In an example, the data strobe signal DQS may have the same frequency as the data strobe signal used in the write operation.

The compensation circuit 348 may compensate the timing of the data strobe signal DQS by referring to the third timing compensation information TCI3 to generate a compensated data strobe signal c_dqs. The sampling circuit 343 may SAMPLE the fourth write training data wt_d4 using the compensated data strobe signal c_dqs to generate fourth sampling data sample_d4. The comparison circuit 346 may compare the fourth pattern data pt_d4 with the fourth sampling data sample_d4 to generate a fourth comparison result com_r4. The delay adjustment circuit 347 may generate a fourth delay control signal d_cs4 for controlling the degree of delay of the signal delay circuit 344 based on the fourth comparison result com_r4. The signal delay circuit 344 may change a delay degree based on the fourth delay control signal d_cs4, may delay the data strobe signal DQS, and may transmit the delayed data strobe signal d_dqs to the buffer device 340 via the data strobe signal line.

The training block TB may perform the operation loops described in fig. 6D and 6E as part of a write training operation performed multiple times on the memory device 360. The delay adjusting circuit 347 may generate the fourth timing compensation information TCI4 based on the fourth comparison result com_r4. The description of the fourth timing compensation information TCI4 is the same as that described above, and a detailed description thereof will be omitted hereinafter.

Fig. 7 is a block diagram showing a training operation of the memory device 360 when the buffer device 440 according to an embodiment of the inventive concept supports a timing adjustment function, and fig. 8A and 8B are diagrams illustrating an example of the configuration and operation of a timing adjustment control unit (RCU) of the buffer device 440.

Referring to fig. 7, a memory system 400 may include a memory controller 420 and a memory module MM, and the memory module MM may include a buffer device 440 and a memory device 460. Unlike the buffer device 340 previously described in fig. 6A and the like, the buffer device 440 may further include a timing adjustment control unit (RCU). The RCU may recalibrate the data signals and data strobe signals received from the memory controller 420, and the RCU may provide the recalibrated data signals and data strobe signals in the buffer device 440 to the memory device 460. By using the RCU, the offset of the data signal and the data strobe signal generated between the memory controller 420 and the buffer device 440 is compensated by recalibrating the data signal and the strobe signal. Accordingly, the buffer device 440 may transmit the data signal and the data strobe signal to the memory device 460 considering only the signal transmission characteristics between the buffer device 440 and the memory device 460. The timing adjustment function described above may be used when buffer device 440 performs a training operation on memory device 460.

Referring now to fig. 8a, the rcu may include a sampling circuit SAM and a serializer SL (or multiplexer). The sampling circuit SAM may include, for example, a first flip-flop FF1 and a second flip-flop FF2, and the serializer SL may include a plurality of logic circuits LC1 to LC3. In an example, the logic circuits LC1 to LC3 may be NAND (NAND) gates. The first flip-flop FF1 and the second flip-flop FF2 may receive the mode data pt_d from the memory controller 420 via the first terminal. In addition, the first flip-flop FF1 and the second flip-flop FF2 may receive the data strobe signal DQS and the data strobe inverse signal/DQS from the memory controller 420 via the second terminal. Each of the first flip-flop FF1 and the second flip-flop FF2 may transmit an output signal to the serializer SL via an output terminal. Meanwhile, the first flip-flop FF1 may transmit a signal generated by sampling the pattern data pt_d using the data strobe signal DQS as the training data t_d to the memory controller 420. The training data t_d may be used to perform training operations on the buffer device 440.

The serializer SL may generate the timing adjustment mode data re_pt_d using the output signal, the data strobe signal DQS, and the data strobe inverted signal/DQS received from the sampling circuit SAM. Referring to fig. 8B, the pattern data pt_d may include first to third data D1 to D3, and the serializer SL may recalibrate the first to third data D1 to D3 based on the data strobe signal. In an example, the serializer SL may recalibrate the first to third data D1 to D3 according to a rising edge of the data strobe signal DQS, and may generate the timing adjustment mode data re_pt_d. Referring back to fig. 8A, the serializer SL may transmit the timing adjustment pattern data re_pt_d to the memory device 460. The timing adjustment pattern data re_pt_d may be used to perform a training operation on the memory device 460. Further, the memory device 460 may generate training data t_d' for a training operation of the memory device 460 to the buffer device 440 based on the timing adjustment pattern data re_pt_d.

Thus, by using the RCU, the training operation for the buffer device 440 and the training operation for the memory device 460 can be performed simultaneously. In addition, the buffer device 440 may perform a training operation on the memory device 460 using the mode data pt_d and the data strobe signal DQS received from the memory controller 420. Accordingly, the buffer device 440 may not include an additional pattern data generator and an additional clock generator, so that the size of the buffer device 440 may be minimized.

Fig. 9 is a block diagram illustrating a training operation of the buffer apparatus 540 by the memory controller 520 generating timing compensation information according to an embodiment of the inventive concept.

Referring now to fig. 9, a memory system 500 may include a memory controller 520 and a buffer device 540. As described above, the training control unit TCU of the memory controller 520 may perform read/write training operations on the buffer device 540. As a result, the TCU may generate the first timing compensation information TCI1 and the second timing compensation information TCI2. The TCU may store the timing compensation information TCI1 and TCI2 in the register 526 of the memory controller 520. In an example, the timing compensation information TCI1 and TCI2 may indicate a timing compensation degree wr_tc for a signal (e.g., a data signal or a data strobe signal) for a write operation transmitted by the memory controller 520 to the buffer device 540 and a timing compensation degree rd_tc for a signal (e.g., a data signal or a data strobe signal) for a read operation received by the memory controller 520 from the buffer device 540. Subsequently, the memory controller 520 may perform a memory operation by referring to the timing compensation information TC11 and TC12 stored in the register 526.

Fig. 10A and 10B are block diagrams illustrating training operations of the memory groups 560_1 to 560—n by the buffer device 540 generating the timing compensation information according to an embodiment of the inventive concept.

Referring now to fig. 10A, a memory system 500 may include a buffer device 540 and a plurality of memory banks 560_1 through 560—n. Each of the plurality of memory groups 560_1 to 560—n may include a plurality of memory devices. Each of the memory banks 560_1 to 560—n may be connected to the buffer device 540 via channels CH1 to CHn.

As described above, the training block TB of the buffer device 540 may perform the read/write training operation on the memory groups 560_1 to 560—n. In an embodiment, the buffer device 540 may further include a switching circuit sw_ckt, and may be selectively connected to each of the memory banks 560_1 to 560—n via the switching circuit sw_ckt. The training block TB may transmit a selection signal ds_s for selecting a specific memory device from a plurality of memory devices as a training object to the switching circuit sw_ckt together with the training related signal tr_s. The switching circuit sw_ckt may connect the memory bank including the memory device selected based on the selection signal ds_s to the buffer device 540 via the channel. For example, when the memory device md1_1 is selected as the training object, the switching circuit sw_ckt may connect the first memory group 560_1 to the buffer device 540 via the first channel CH 1. Subsequently, the selection signal ds_s may be sent to the memory devices of the first memory group 560_1 via the first channel CH1, and only the memory device md1_1 corresponding to the selection signal ds_s is enabled so that the training block TB may perform a training operation on the memory device md1_1. Regardless, the foregoing description is of embodiments that fall within the inventive concept. Accordingly, other embodiments of the inventive concept are not so limited, and the training block TB may perform a training operation on a memory device by selecting the memory device in various ways.

Thus, the training block TB may perform a training operation on the memory groups 560_1 to 560—n. As a result, the training block TB may generate the third timing compensation information TCI3 and the fourth timing compensation information TCI4. The training block TB may store the timing compensation information TCI3 and TCI4 in a register 545 of the buffer device 540. Subsequently, the buffer device 540 may perform a storage operation (e.g., a read operation or a write operation) with reference to the timing compensation information TC13 and TC14 stored in the register 545.

In an example, the timing compensation information TCI3 and TCI4 may indicate a timing compensation degree wr_tc for a signal (e.g., a data signal or a data strobe signal) for a write operation transmitted to the memory device by the buffer device 540 and a timing compensation degree rd_tc for a signal (e.g., a data signal or a data strobe signal) for a read operation received from the memory device by the buffer device 540 according to the memory devices md_1 to md_m_n. Subsequently, the buffer device 540 may perform a storage operation by referring to the timing compensation information TC13 and TC14 stored in the register 545.

When the storage operation is performed at a low frequency equal to or less than the threshold frequency value, an offset may occur due to the characteristics of each channel instead of the characteristics of each memory device. Accordingly, the offset generation patterns of signals transmitted/received between the memory devices and the buffer device 540 included in the same memory group 560_1 to 560—n may be the same or similar. Unlike in fig. 10A, in fig. 10B, the timing compensation information TCI3 'to TCI4' generated as a result of performing the training operation on the memory groups 560_1 to 560—n may indicate a timing compensation degree wr_tc for a signal (e.g., a data signal or a data strobe signal) for a write operation transmitted from the buffer device 540 to the memory device. Further, the timing compensation degree rd_tc for the signal (e.g., data signal or data strobe signal) for the read operation received by the buffer device 540 from the memory device may be indicated according to the channels CH1 to CHn.

In an embodiment of the inventive concept, after performing the training operation on the first memory group 560_1 connected to the first channel CH1 is completed, the training block TB may generate timing compensation information corresponding to the first channel CH 1. Of course, unlike in fig. 10A, in fig. 10B, the data strobe signal used when the training block TB performs the training operation may have a low frequency equal to or less than the threshold. In detail, the training operation is performed on only one memory device included in the first memory group 560_1, so that the timing compensation information corresponding to the first channel CH1 may be generated, or the training operation may be performed on at least two memory devices included in the first memory group 560_1, and an average value of the generated timing compensation information may be generated as the timing compensation information corresponding to the first channel CH 1. Thus, the training block TB may generate timing compensation information corresponding to the second through nth channels CH2 through CHn to store the generated timing compensation information in the register 545. Other embodiments of the inventive concept are not limited to the above-described embodiments, as the timing compensation information may be generated according to the channel in various ways. Subsequently, the buffer device 540 may perform a storage operation based on a low frequency equal to or less than the threshold value by referring to the timing compensation information TC13 'and TC14' stored in the register 545.

Fig. 11 is a block diagram of a memory system 600 according to an embodiment of the inventive concept.

Referring to fig. 11, the memory system 600 may include a memory controller 620 and a memory module MM, and the memory module MM may include a plurality of buffer devices 640_1 to 640_7 and a plurality of memory devices 660_3 to 660_7. The memory controller 620 may perform a training operation on the first buffer device 640_1 using a Training Control Unit (TCU), and may store timing compensation information generated as a result of performing the training operation in the register rg_a.

In an embodiment of the inventive concept, the buffer devices 640_1 to 640_7 may form a predetermined tree structure. As shown in fig. 11, each of the buffer devices 640_1 to 640_7 may include a respective switching circuit sw_ckt. The first buffer device 640_1 may be connected to the second buffer device 640_2 and the fifth buffer device 640_5 via a switching circuit sw_ckt. The second buffer device 640_2 and the fifth buffer device 640_5 connected to the first buffer device 640_1 may be referred to as sub-buffer devices of the first buffer device 640_1, and the first buffer device 640_1 may be referred to as main buffer device. As in the above-described embodiment, the first buffer device 640_1 may perform a training operation on the second buffer device 640_2 and the fifth buffer device 640_5 using the training block TB, and timing compensation information generated as a result of performing the training operation may be stored in the register rg_b1.

Further, the second buffer device 640_2 may be connected to the third buffer device 640_3 and the fourth buffer device 640_4 via a switching circuit sw_ckt. The third buffer device 640_3 and the fourth buffer device 640_4 connected to the second buffer device 640_2 may be referred to as sub-buffer devices of the second buffer device 640_2, and the second buffer device 640_2 may be referred to as a main buffer device. The third buffer device 640_3 may be connected to the first memory device 660_3 via the switching circuit sw_ckt, and the fourth buffer device 640_4 may be connected to the second memory device 660_4 via the switching circuit sw_ckt. As in the above-described embodiment, the second buffer device 640_2 may perform a training operation on the third buffer device 640_3 and the fourth buffer device 640_4 using the training block TB, and may store timing compensation information generated as a result of performing the training operation. The third and fourth buffer devices 640_3 and 640_4 may perform a training operation on the corresponding first and second memory devices 660_3 and 660_4 using the training block TB, and may store timing compensation information generated as a result of performing the training operation in the registers rg_b3 and rg_b4. The relationship between the fifth to seventh buffer devices 640_5 to 640_7 and the third and fourth memory devices 660_6 and 660_7 is similar to that between the second to fourth buffer devices 640_2 to 640_4 and the first and second memory devices 660_3 and 660_4, and thus a detailed description thereof will be omitted. In addition, while each of the buffer devices shown in fig. 11 has its own switching circuit, other configurations are possible within the contemplation of the present invention, e.g., switches may be arranged that receive inputs from more than one buffer device.

Fig. 12 is a block diagram illustrating a storage operation method of the memory system 700 according to an embodiment of the inventive concept.

Referring to fig. 12, a memory system 700 may include a memory controller 720 and a memory module MM, and the memory module MM may include at least one buffer device 740 and a plurality of memory devices 760. Memory controller 720 may include registers 722 and compensation circuitry 724. As described above, timing compensation information generated as a result of performing a training operation on the buffer apparatus 740 may be stored in the register 722. The compensation circuit 724 may compensate for the timing of a signal to be transmitted to the buffer device 740 by referring to the timing compensation information in the register 722, and may then transmit the signal to the buffer device 740. Further, the compensation circuit 724 may compensate for the timing of the signal received from the buffer device 740 by referring to the timing compensation information in the register 722.

The buffer device 740 may include a register 742, a compensation circuit 744, and a switching circuit 746. As described above, timing compensation information generated as a result of performing a training operation on memory device 760 may be stored in register 742. The compensation circuit 744 may compensate for the timing of a signal to be sent to the memory device 760 by referring to the timing compensation information in the register 742, and may then send the signal to the memory device 760. In addition, the compensation circuit 744 may compensate for timing of signals received from the memory device 760.

The memory system 700 according to an embodiment of the inventive concept may perform a storage operation including timing compensation information for the above-described signals.

Fig. 13A and 13B are diagrams illustrating an embodiment of a memory device 160.

Referring to fig. 13A, the memory device MD may include a memory cell array MCA, and the memory cell array MCA may include a plurality of memory blocks BLK1 to BLKz.

Referring to fig. 13B, the memory block BLKa may include a plurality of cell strings CS11 to CS21 and CS12 to CS22. The plurality of cell strings CS11 to CS21 and CS12 to CS22 may be arranged along a row direction and a column direction and may form rows and columns. For example, the cell strings CS11 and CS12 arranged in the row direction may form a first row, and the cell strings CS21 and CS22 arranged in the row direction may form a second row. The cell strings CS11 and CS21 arranged along the column direction may form a first column, and the cell strings CS12 and CS22 arranged along the column direction may form a second column. Each of the cell strings CS11 and CS12 and CS21 and CS22 may include a plurality of cell transistors. The plurality of cell transistors may include ground selection transistors GSTa and GSTb, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistors GSTa and GSTb, the memory cells MC1 to MC6, and the string selection transistors SSTa and GSTb of each cell string may be stacked in a direction perpendicular to the height of a plane (e.g., the plane of the substrate of the memory block BLKa) in which the cell strings CS11 to CS21 and CS12 to CS22 are arranged along rows and columns.

With continued reference to fig. 13B, the plurality of cell transistors may be, for example, charge trap type transistors having a threshold voltage that varies according to the amount of charge trapped in the insulating layer. The bottommost ground selection transistor GSTa may be commonly connected to the common source line CSL. The ground selection transistors GSTa and GSTb of the plurality of cell strings CS11 to CS21 and CS12 to CS22 may be commonly connected to the ground selection line GSL. Memory cells disposed at the same height (or order) from the substrate (or ground selection transistor GST) may be commonly connected to one word line, and memory cells disposed at different heights (or orders) may be connected to different word lines WL1 to WL6. Among the first string selection transistors SSTa at the same height (or order) of the plurality of cell strings CS11 to CS21 and CS12 to CS22, the first string selection transistors SSTa in different rows may be connected to different string selection lines SSL1a to SSL2a. Among the second string selection transistors SSTb at the same height (or order) of the plurality of cell strings CS11 to CS21 and CS12 to CS22, the second string selection transistors SSTb in different rows may be connected to different string selection lines SSL1b to SSL2b.

Fig. 14 is a block diagram of a memory system 1000 according to an embodiment of the inventive concept.

Referring to fig. 14, a memory system 1000 may include a memory controller 1200 and a memory module 1400. The memory module 1400 may include at least one memory chip 1800 and buffer chips 1600, each memory chip 1800 including a memory cell array, the buffer chips 1600 for routing transmit/receive signals between the memory chip 1800 and the memory controller 1200 or managing memory operations to the memory chip 1800. The memory chips 1800 of the memory module 1400 may be classified into a first level R1 and a second level R2. The buffer chip 1600 may include a training block 1620.

Training block 1620, which is part of buffer chip 1600, may perform training operations on memory chip 1800 when embodiments such as those described in fig. 1-11 are applied to training block 1620. In the example of fig. 14, a portion of the functions of the memory controller 1200 are performed in a memory module having an LRDIMM shape. However, embodiments of the inventive concept are not so limited. For example, when a memory module having an FBDIMM shape is used, an Advanced Memory Buffer (AMB) chip as a buffer chip may also be mounted on the memory module. Also, memory modules having different shapes may be used, and at least a portion of the functions of the memory controller described above may be performed.

According to this embodiment of the inventive concept, the training operation for the plurality of memory chips 1800 may be performed in different manners according to the elements of the buffer chip 1600.

For example, if the buffer chip 1600 does not include a decision circuit, the memory controller 1200 may perform a training operation on the memory chip 1800 using the buffer chip after performing the training operation on the buffer chip.

In another example, if the buffer chip 1600 includes a decision circuit, the buffer chip 1600 may perform training operations on the memory device independently of the memory controller 1200. Further, the training operation between the memory controller 1200 and the buffer chip 1600 and the training operation between the buffer chip and the memory chip may be performed simultaneously. By simultaneously performing the training operations, the time required for the training operations can be reduced.

Fig. 15 is a block diagram of a semiconductor package 2000 having a stacked structure including a plurality of layers according to an embodiment of the inventive concept.

Referring to fig. 15, the semiconductor package 2000 may include a plurality of layers LA1 to LAn. Each of the first through (n-1) -th layers LAn-1 may be a memory layer (or a memory chip) including a plurality of memory cores MC. The plurality of memory cores MC may include a memory cell array for storing data, a row decoder, a column decoder, and a sense amplifier. The nth layer LAn may be a buffer layer (or buffer chip). The layers LA1 to LAn having a stacked structure in the semiconductor package 2000 may be connected to each other via a Through Silicon Via (TSV) 2300.

The buffer layer LAn may communicate with external memory controllers and memory layers LA1 to LAn-1, and may route transmission/reception signals between the memory layers LA1 to LAn-1 and the memory controllers. In addition, the buffer layer LAn may queue signals received from the memory controllers or memory layers LA1 through LAn-1.

Further, the buffer layer LAn may include a training block 2200. The buffer layer LAn may perform training operations on the memory layers LA1 to LAn-1 using the training block 2200. The embodiments described in fig. 1 to 11 may be applied to the training operation method of the buffer layer LAn. In an embodiment, the buffer layer LAn may perform a training operation on the memory layers LA1 to LAn-1, and may generate timing compensation information for transmission/reception signals between the base layer LAn and the memory layers LA1 to LAn-1 according to the memory core MC.

Fig. 16 is a diagram of a semiconductor package including stacked semiconductor chips according to an embodiment of the inventive concept.

Referring to fig. 16, a semiconductor package 3000 may be a memory module including at least one stacked semiconductor chip 3300 and a system on a chip (SOC) 3400 mounted on a package substrate 3100, such as a Printed Circuit Board (PCB). The interposer 3200 may optionally be disposed on the package substrate 3100. The stacked semiconductor chip 3300 may be formed as a Chip On Chip (COC). Stacking the semiconductor chips 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310 such as a logic chip. The buffer chip 3310 and the at least one memory chip 3320 may be connected to each other via TSVs. The buffer chip 3310 may perform a training operation on the memory chip 3320, and embodiments such as those described in fig. 1 to 11 may be applied to the training operation method of the buffer chip 3310. For example, the stacked semiconductor chip 3300 may be a High Bandwidth Memory (HBM) of 500 GB/sec to 1 TB/sec or higher.

Fig. 17 is a flowchart illustrating a method of manufacturing a semiconductor package having a buffer chip constructed according to an embodiment of the inventive concept.

The operations in fig. 17 may be applied to various configurations of the inventive concept as shown in fig. 14 to 16, for example. However, it will be appreciated and understood by those of ordinary skill in the art that the embodiments of the inventive concept are not limited to the examples shown and described.

Referring to operation S1700 and fig. 14, a memory system including one or more memory chips 1800 arranged as a part of a semiconductor package is formed. For example, the memory system 1000 may include one or more memory chips 1800, each of which may have a memory cell array, a buffer chip 1600, which may have a training block TB, and a memory controller 1200 that controls the memory operations of the memory modules via the buffer chip 1600. The buffer chip 1600 routes transmit and receive signals from one or more memory chips and a memory controller.

In step S1710, the training operation depends on whether the buffer chip 1600 has a decision circuit such as that previously shown and described herein.

If the buffer chip 1600 has a decision circuit, the buffer chip may independently perform a training operation on the memory device controlled by the memory controller at step S1720 a. The training operation may be one of the types previously disclosed.

The inventive concept is an improvement over known memory structures at least because training operations, for example, between a buffer chip and a memory device, can be performed simultaneously so that the time to perform the training operations can be reduced.

If the buffer chip does not include the decision circuit, the memory controller 1200 may first perform a training operation on the buffer chip 1600 at S1720b, unlike, for example, the independent execution in operation S1720 a. Subsequently, under the control of the memory controller 1200, a training operation for one or more memory devices may be performed through the buffer chip 1600.

Although in the above-described example of fig. 17, various training operations are performed according to whether the determination circuit is included in the buffer chip, the inventive concept is not limited thereto. Thus, depending on the various elements of the buffer chip, the training operations for the memory device may be performed in various ways, e.g., as described above.

While the present inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A memory system, comprising:

a memory module including a plurality of memory devices;

a memory controller configured to control a memory operation to the plurality of memory devices; and

a buffer device connected between the plurality of memory devices and the memory controller, the buffer device including a training block including a first signal delay circuit configured to perform a training operation on the plurality of memory devices;

wherein the memory controller is configured to control the training block to perform the training operation on the plurality of memory devices, and includes a training block of a second signal delay circuit that performs a training operation on the buffer device.

2. The memory system according to claim 1, wherein the memory controller is configured to compare pattern data corresponding to training data with sampling data generated by sampling training data from a memory device selected as an object of the training operation for the plurality of memory devices, generate a delay control signal for controlling a degree of delay of the first signal delay circuit based on a result of the comparison of the pattern data with the sampling data, and transmit the delay control signal to the buffer device.

3. The memory system of claim 2, wherein the sample data is received from the buffer device and the training block comprising the first signal delay circuit samples the training data using a data strobe signal for the training operation on the plurality of memory devices to generate the sample data.

4. The memory system of claim 2, wherein the first signal delay circuit is to delay a signal for performing the training operation on the plurality of memory devices for the selected memory device based on the delay control signal.

5. The memory system according to claim 1, wherein when performing a storage operation on the plurality of memory devices, the memory controller generates first timing compensation information for reference by the buffer device during a timing compensation operation for signals transmitted/received by the plurality of memory devices, based on a result of performing the training operation on the plurality of memory devices, the first timing compensation information being transmitted to the buffer device.

6. The memory system of claim 5, wherein the signals transmitted/received by the plurality of memory devices include a first data strobe signal transmitted to the plurality of memory devices by the buffer device and a second data strobe signal received from the plurality of memory devices by the buffer device.

7. The memory system of claim 5, wherein the first timing compensation information comprises timing compensation information corresponding to each of the plurality of memory devices.

8. The memory system according to claim 5, wherein the buffer device is connected to the plurality of memory devices via at least two channels, and the first timing compensation information includes timing compensation information corresponding to each of the channels.

9. The memory system according to claim 5, wherein the buffer device compensates timing of the signal received from the memory controller and the signal received from the plurality of memory devices based on the first timing compensation information, and transmits the signal received from the memory controller to the plurality of memory devices and transmits the signal received from the plurality of memory devices to the memory controller.

10. The memory system according to claim 1, wherein when the training operation is performed on the buffer device and the storing operation is performed on the plurality of memory devices, the memory controller generates second timing compensation information for reference by the memory controller during a timing compensation operation for a signal transmitted/received by the buffer device based on a result of the training operation performed on the buffer device.

11. The memory system according to claim 10, wherein the memory controller compensates timing of a signal to be transmitted to the buffer device and a signal received from the buffer device based on the second timing compensation information.

12. The memory system of claim 10, wherein the memory controller is configured to first perform the training operation on the buffer device, and the memory controller is further configured to subsequently perform the training operation on the plurality of memory devices by controlling operation of the training block.

13. A memory system, comprising:

a memory controller configured to control a memory operation to a plurality of memory devices; and

A memory module including the plurality of memory devices and a buffer device connected between the plurality of memory devices and the memory controller,

wherein the buffer device includes a training block configured to perform training operations on the plurality of memory devices, an

Wherein the training block performs the training operation using first training data and a first data strobe signal received from a target memory device for the training operation among the plurality of memory devices, and generates first timing compensation information for reference by the buffer device during a timing compensation operation for signals related to a storage operation transmitted/received for the plurality of memory devices.

14. The memory system of claim 13, wherein when performing a read training operation on the target memory device, the training block comprises:

a signal delay circuit configured to delay the first data strobe signal;

a sampling circuit configured to sample the first training data using the delayed first data strobe signal and generate first sampled data;

A comparison circuit configured to compare first pattern data corresponding to the first training data with the first sampling data and generate a first comparison result; and

and a delay adjustment circuit configured to generate a first delay control signal for controlling a degree of delay of the first data strobe signal based on the first comparison result and to supply the first delay control signal to the signal delay circuit.

15. The memory system of claim 13, wherein when performing a write training operation on the target memory device, the training block comprises:

a sampling circuit configured to sample the first training data corresponding to second pattern data using the first data strobe signal and generate second sampled data;

a comparison circuit configured to compare the second sampling data with the second pattern data and generate a second comparison result;

a delay adjustment circuit configured to generate a second delay control signal for controlling a degree of delay of the first data strobe signal based on the second comparison result; and

a signal delay circuit configured to delay the first data strobe signal based on the second delay control signal and transmit the delayed first data strobe signal to a target memory device of the plurality of memory devices.

16. The memory system according to claim 13, wherein the memory controller is configured to perform a training operation on the buffer device and generate second timing compensation information for reference by the memory controller during a timing compensation operation for a signal related to a storage operation transmitted/received by the buffer device based on a result of the training operation performed on the buffer device.

17. The memory system of claim 13, wherein the training block comprises a timing adjustment control unit configured to receive second mode data and a second data strobe signal from the memory controller, recalibrate the second mode data based on the second data strobe signal, and provide the recalibrated second mode data and the second data strobe signal to the target memory device to perform a training operation on the target memory device.

18. The memory system according to claim 13, wherein, when a fourth data strobe signal is received from a selected memory device among the plurality of memory devices during a storage operation performed on the selected memory device, the buffer device compensates for timing of the fourth data strobe signal based on the first timing compensation information.

19. A memory module, comprising:

a plurality of memory devices; and

a plurality of buffer devices configured to route signals to and from the plurality of memory devices,

wherein the plurality of buffer devices includes:

a first sub-buffer apparatus connected to a first memory apparatus of the plurality of memory apparatuses and including a first training block configured to perform a second training operation on the first memory apparatus;

a second sub-buffer apparatus connected to a second memory apparatus of the plurality of memory apparatuses and including a second training block configured to perform a third training operation on the second memory apparatus; and

a main buffer device connected to the first and second sub-buffer devices, and

wherein the main buffer device is configured to perform a first training operation on the first sub-buffer device and the second sub-buffer device, and wherein the first training operation, the second training operation, and the third training operation include generating timing compensation information for one or more of a read training operation and a write training operation; and

Wherein the first training block performs the second training operation using first training data and a first data strobe signal received from a first target memory device among the first memory devices for the second training operation; and

the second training block performs the third training operation using second training data and a second data strobe signal received from a second target memory device among the second memory devices for the third training operation.

20. The memory module of claim 19, wherein the main buffer means includes a first register configured to store timing compensation information corresponding to each of the first sub-buffer means and the second sub-buffer means generated as a result of performing the first training operation, and

the first sub-buffer apparatus includes a second register configured to store timing compensation information corresponding to each of the first memory apparatuses generated as a result of performing the second training operation, and

the second sub-buffer apparatus includes a third register configured to store timing compensation information corresponding to each of the second memory apparatuses generated as a result of performing the third training operation.