CN109492306A - A kind of associated layers reactionary slogan, anti-communist poster method of design rule verification result - Google Patents
A kind of associated layers reactionary slogan, anti-communist poster method of design rule verification result Download PDFInfo
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- CN109492306A CN109492306A CN201811338930.2A CN201811338930A CN109492306A CN 109492306 A CN109492306 A CN 109492306A CN 201811338930 A CN201811338930 A CN 201811338930A CN 109492306 A CN109492306 A CN 109492306A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A kind of associated layers reactionary slogan, anti-communist poster method of design rule verification result, comprising the following steps: design rule corresponding to analysis layout verification result obtains the association figure layer of its correspondence proving；Hide the dereferenced figure layer on domain；Reactionary slogan, anti-communist poster height reveals the errors present of verification result.The associated layers reactionary slogan, anti-communist poster method of design rule verification result of the invention, the only association figure layer that highlighted design rule is relied on, hide the every other figure layer in addition to being associated with figure layer, avoiding reactionary slogan, anti-communist poster region and overlaping there are multi-layer graphical influences design engineer's analytical judgment, so as to shorten proving period.
Description
Technical field
The present invention relates to semiconductor integrated circuit the Automation Design fields more particularly to semiconductor integrated circuit automation to set
Rear end layout design, design rule verification and domain debugging analysis in meter.
Background technique
Layout design and verifying are a rings important in design flow of integrated circuit, and the verifying of efficiently and accurately can be effective
The efficiency of IC design is improved, the risk of design failure is greatly reduced.It is constantly grading towards nanometer however as technique
Exhibition, in the design of ultra-large or even very large scale integration, domain scale sharply expands, and layout verification is required each time
Time it is increasingly longer, and the modification of domain is also become because of domain scale after verifying each time it is increasingly complex with it is time-consuming,
Therefore the iteration cycle of layout verification and modification domain is also longer.At this stage, mainstream layout verification generally use layered verification,
The technologies such as parallel accelerate layout verification, but due to scale all too is big, layout verification is still time-consuming each time.
Conventional layout verification includes design rule verification and domain and schematic diagram consistency checking.Design rule is tested each time
After card, the result that design engineer needs to be reported according to verification tool carries out debugging analysis to domain, usually uses debugging tool
The highlighted position that makes mistake, the All Layers figure in region that customer analysis errors present institute height is revealed, and then analyze separated
The figure of mimetic design rule simultaneously accordingly modifies domain, but according to the difference of layout design technique, figure layer layer used in domain
Number is also different, often the high region put forward can in the presence of several layers graphics overlay together, the analysis to design engineer
Some obstacles be will cause to influence efficiency.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of design rule verification results
Associated layers reactionary slogan, anti-communist poster method, the association figure layer that highlighted design rule is relied on, and hide the institute on domain other than being associated with figure layer
There are other figure layers, avoiding reactionary slogan, anti-communist poster region from overlaping there are multi-layer graphical influences design engineer's analytical judgment.
To achieve the above object, the associated layers reactionary slogan, anti-communist poster method of design rule verification result provided by the invention, including it is following
Step:
1) design rule corresponding to layout verification result is analyzed, the association figure layer of its correspondence proving is obtained；
2) the dereferenced figure layer on domain is hidden；
3) reactionary slogan, anti-communist poster height reveals the errors present of verification result.
Further, the step 1) further includes steps of
21) traversal and analytical design method rule file, record operation generate the original figure layer and intermediate figure layer of each intermediate figure layer, note
Record the intermediate figure layer of every design rule check；
22) all original figure layers that each intermediate figure layer of recursive analysis is relied on；
23) merge the original layers that all intermediate figure layers of each design rule check are relied on, the pass as the design rule
Join figure layer.
Further, the dereferenced figure layer in the step 2 refers to the figure in domain in addition to the association figure layer
Layer.
To achieve the above object, the present invention also provides a kind of computer readable storage mediums, are stored thereon with computer and refer to
The step of order, the computer instruction executes the associated layers reactionary slogan, anti-communist poster method of above-mentioned design rule verification result when running.
It, can be according to the affiliated design rule of verification result, certainly when the present invention carries out design rule verification after layout design
Row analysis obtains the association figure layer that the design rule is relied on, and hides the every other figure on domain other than being associated with figure layer
Then layer just carries out reactionary slogan, anti-communist poster and highlights, figure layer only associated with the verification result in this way can just be shown, unrelated figure layer overlapping is made
It there would not be at the problem of disturbance of analysis.
Therefore, the present invention can remove unrelated figure layer, and only display association figure layer, has greatly facilitated design engineer to setting
The analysis for counting rule verification result has very big practicability to the shortening in whole layout design period.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart of the associated layers reactionary slogan, anti-communist poster method of design rule verification result according to the present invention；
Fig. 2 is the design layout schematic diagram according to embodiments of the present invention；
Fig. 3 is the figure layer result schematic diagram according to embodiments of the present invention；
Fig. 4 is to highlight result schematic diagram according to the reactionary slogan, anti-communist poster of embodiments of the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the flow chart of the associated layers reactionary slogan, anti-communist poster method of design rule verification result according to the present invention, below with reference to
The associated layers reactionary slogan, anti-communist poster method of design rule verification result of the invention is described in detail in Fig. 1.
Fig. 2 is the design layout schematic diagram according to embodiments of the present invention.In the present invention, with domain shown in Fig. 2
It is illustrated with for " the RULE checkrule1 " in following design rule content.
layer( L1 1 )
layer( L2 2 )
layer( L3 3 )
layer( L4 4 )
layer( L5 5 )
AA0 = geom_inside( L4 L1 )
AA1 = geom_and( AA0 L3 )
RULE checkrule1 { space( AA1 < 2 region) }
AA2 = geom_not ( L2 L1 )
AA3 = geom_and ( L1 L5 )
RULE checkrule2 { space( AA2 AA3 < 5 region ) }
In order to describe conveniently, the domain and design rule of present embodiment have all done simplification, it is assumed that L1, L2, L3, L4 and L5 are versions
All original figure layers occurred in figure, and only explained in the present embodiment with rule " checkrule1 ".
Firstly, determining the association figure layer of layout verification result in step 101.
In this step, design rule corresponding to verification result is analyzed, to obtain the association figure layer of its correspondence proving.Tool
Body, comprising the following steps:
1) traversal and analytical design method rule file record each intermediate figure layer and are produced by which original figure layer and intermediate figure layer operation
It is raw, it records every design rule and which intermediate figure layer is checked；
In the present embodiment, it records intermediate figure layer AA0 to be generated by original layers L1 and L4 operation, the figure layer result that domain generates is such as
In Fig. 3 shown in AA0；Intermediate figure layer AA1 is generated by intermediate figure layer AA0 and original layers L3 operation, and the figure layer result that domain generates is such as
In Fig. 3 shown in AA1；Intermediate figure layer AA2 is generated by original layers L1 and L2 operation, and intermediate figure layer AA3 is by original layers L1 and L5 operation
It generates.The inspection carried out in design rule " checkrule1 " is related to intermediate figure layer AA1, the inspection carried out in " checkrule2 "
It looks into and is related to intermediate figure layer AA2 and AA3.
2) to each intermediate figure layer, recursive analysis goes out all original figure layers that the intermediate figure layer is relied on；
Intermediate figure layer AA0 relies on original figure layer L1 and L4；Intermediate figure layer AA1 relies on intermediate figure layer AA0 and L3, then, middle graph
The original layers that layer AA1 is relied on are L1, L3 and L4.Intermediate figure layer AA2 relies on original figure layer L1 and L2；Intermediate figure layer AA3 relies on former
Beginning figure layer L1 and L5.
3) to each design rule, merge the original layers that all intermediate figure layers of the design rule check are relied on, i.e.,
For the association figure layer of the design rule；
By taking design rule " checkrule1 " as an example, the intermediate figure layer being related in inspection is AA1, the original layers that AA1 is relied on
It is L1, L3 and L4, then, all original layers that design rule checkrule1 is relied on are L1, L3 and L4, i.e. L1, L3 and L4 is
The association figure layer of the design rule " checkrule1 ".
In step 102, the dereferenced figure layer on domain is hidden.
In this step, the every other figure layer on domain other than being associated with figure layer is hidden, i.e., only shows association
Figure layer specifically in the present embodiment, hides the L2 and L5 in domain, only shows the pass of design rule " checkrule1 "
Join figure layer L1, L3 and L4.
It is highlighted to the errors present reactionary slogan, anti-communist poster of verification result in step 103.
In this step, reactionary slogan, anti-communist poster height reveals the errors present of verification result.
Specifically, Fig. 4 is to highlight result schematic diagram according to the reactionary slogan, anti-communist poster of embodiments of the present invention.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer instruction, the computer
The step of executing the associated layers reactionary slogan, anti-communist poster method of above-mentioned design rule verification result when instruction operation, the design rule verification knot
The associated layers reactionary slogan, anti-communist poster method of fruit is repeated no more referring to the introduction of preceding sections.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (4)
1. a kind of associated layers reactionary slogan, anti-communist poster method of design rule verification result, which comprises the following steps:
1) design rule corresponding to layout verification result is analyzed, the association figure layer of its correspondence proving is obtained；
2) the dereferenced figure layer on domain is hidden；
3) reactionary slogan, anti-communist poster height reveals the errors present of verification result.
2. the associated layers reactionary slogan, anti-communist poster method of design rule verification result according to claim 1, which is characterized in that the step
1) it further includes steps of
21) traversal and analytical design method rule file, record operation generate the original figure layer and intermediate figure layer of each intermediate figure layer；Note
Record the intermediate figure layer of every design rule check；
22) all original figure layers that each intermediate figure layer of recursive analysis is relied on；
23) merge the original layers that all intermediate figure layers of each design rule check are relied on, the pass as the design rule
Join figure layer.
3. the associated layers reactionary slogan, anti-communist poster method of design rule verification result according to claim 1, which is characterized in that the step
2) the dereferenced figure layer in refers to the figure layer in domain in addition to the association figure layer.
4. a kind of computer readable storage medium, is stored thereon with computer instruction, which is characterized in that the computer instruction fortune
Perform claim requires the step of associated layers reactionary slogan, anti-communist poster method of 1 to 3 described in any item design rule verification results when row.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811338930.2A CN109492306B (en) | 2018-11-12 | 2018-11-12 | Association layer denotation method for design rule verification result |
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| CN201811338930.2A CN109492306B (en) | 2018-11-12 | 2018-11-12 | Association layer denotation method for design rule verification result |
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| CN109492306B CN109492306B (en) | 2020-04-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113642286A (en) * | 2021-08-12 | 2021-11-12 | 长鑫存储技术有限公司 | Test pattern verification method, device, equipment and storage medium |
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| CN109492306B (en) | 2020-04-07 |
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Effective date of registration: 20210329 Address after: 518100 1001, building 5, Shenjiu science and Technology Pioneer Park, northwest, intersection of Taohua road and Binglang Road, Fubao community, Fubao street, Futian District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |