CN109491659B

CN109491659B - Instruction conversion method and device

Info

Publication number: CN109491659B
Application number: CN201710813786.2A
Authority: CN
Inventors: 张利霞; 余银
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2017-09-11
Filing date: 2017-09-11
Publication date: 2022-06-21
Anticipated expiration: 2037-09-11
Also published as: CN109491659A

Abstract

The embodiment of the invention provides an instruction conversion method, which comprises the following steps: acquiring an arithmetic instruction of an intermediate code of a LLVM compiler of a bottom layer virtual machine; determining operands and operation codes of arithmetic instructions of the LLVM compiler intermediate code; determining the system digit of a target platform; in an instruction set of the target platform, determining an arithmetic instruction operation code of the LLVM compiler intermediate code and a target operation code corresponding to the system bit number; and generating an arithmetic instruction of the target platform by adopting the operand and the target operation code. In the embodiment of the present invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the target platform, the LLVM compiler may generate the arithmetic instruction matching the system bit number of the target system according to the system bit number of the target platform.

Description

Instruction conversion method and device

Technical Field

The present invention relates to the field of computer technologies, and in particular, to an instruction conversion method and an instruction conversion apparatus.

Background

An LLVM (Low Level Virtual Machine) compiler is a compiler that can convert high-Level language code into target platform code. The LLVM compiler first converts the high-level language code into the intermediate language instructions IR of the LLVM, and then converts the intermediate instructions into the target platform code.

The intermediate language instruction IR of the LLVM compiler needs to be converted into an instruction with a SelectionDAG node through the SelectionDAG node selector. The ISD command space includes an enumeration list that records all selectordag node types and value types, where selectordag nodes include: the multi-precision add-subtract instructions ADDC, SUBC, ADDE, SUBE.

In the prior art, only the conversion operation of converting multi-precision addition and subtraction instructions ADDC, subsc, ADDE, and subscribe into instructions on a 32-bit MIPS platform is realized, and the conversion operation of a 64-bit MIPS platform is not realized.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are proposed to provide an instruction converting method and a corresponding instruction converting apparatus that overcome or at least partially solve the above problems.

In order to solve the above problem, an embodiment of the present invention discloses an instruction conversion method, including:

acquiring an arithmetic instruction of an intermediate code of a LLVM compiler of a bottom layer virtual machine;

determining operands and operation codes of arithmetic instructions of the LLVM compiler intermediate code;

determining the system digit of a target platform;

in an instruction set of the target platform, determining an arithmetic instruction operation code of the LLVM compiler intermediate code and a target operation code corresponding to the system bit number;

and generating an arithmetic instruction of the target platform by adopting the operand and the target operation code.

Preferably, the target platform is an MIPS platform, and the arithmetic instruction includes: ADDC add instructions and subs subtract instructions; the operation code of the ADDC addition instruction is an ADDC operation code; the operation code of the SUBC subtraction instruction is an SUBC operation code;

the step of determining a target operation code corresponding to an operation code of an arithmetic instruction of the LLVM compiler intermediate code in a target instruction set of the target platform includes:

if the arithmetic instruction is an ADDC addition instruction, the system digit of the target platform is 64 bits, and the operand of the ADDC addition instruction does not contain an immediate number, determining an addition operation code DADDu corresponding to the ADDC operation code;

if the arithmetic instruction is an SUBC subtraction instruction, the system digit of a target platform is 64 bits, and the operand of the SUBC subtraction instruction does not contain an immediate number, determining a subtraction operation code DSUBu corresponding to the SUBC operation code;

if the arithmetic instruction is an ADDC addition instruction, the system digit of the target platform is 64 bits, and the operand of the ADDC addition instruction comprises an immediate number, determining an addition operation code DADDiu corresponding to the ADDC operation code;

if the arithmetic instruction is a SUBC subtraction instruction, the system number of the target platform is 64 bits, and the operand of the SUBC subtraction instruction comprises an immediate number, determining a subtraction operation code DSUBiu corresponding to the SUBC operation code.

Preferably, operands of the ADDC add instruction and the subs subtract instruction include: a first operand and a second operand; the step of generating the arithmetic instruction of the target platform by adopting the operand and the target operation code comprises the following steps:

generating an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by adopting the first operand, the second operand and the addition operation code DADDu; or the like, or, alternatively,

generating a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform by adopting the first operand, the second operand and the subtraction operation code DSUBu; or the like, or, alternatively,

generating an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by adopting the first operand, the second operand and the addition operation code DADDiu; or the like, or a combination thereof,

and generating a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform by adopting the first operand, the second operand and the subtraction operation code DSUBiu.

Preferably, the target platform is an MIPS platform, and the arithmetic instruction includes: ADDE add and subscribe subtract instructions; the operation code of the ADDE addition instruction is an ADDE operation code; the operation code of the SUBE subtraction instruction is a SUBE operation code;

the step of determining, in the instruction set of the target platform, an arithmetic instruction opcode corresponding to the LLVM compiler intermediate code and a target opcode corresponding to the system bit number includes:

if the arithmetic instruction is an ADDE addition instruction, the system digit of the target platform is 64 bits, and the operand of the ADDE addition instruction does not contain an immediate number, determining an addition operation code DADDu corresponding to the ADDE operation code;

if the arithmetic instruction is a SUBE subtraction instruction, the system digit of the target platform is 64 bits, and the operand of the SUBE subtraction instruction does not contain an immediate number, determining a subtraction operation code DSUBu corresponding to the SUBE operation code;

if the arithmetic instruction is an ADDE addition instruction, the system digit of the target platform is 64 bits, and the operand of the ADDE addition instruction comprises an immediate number, determining an addition operation code DADDiu corresponding to the ADDE operation code;

if the arithmetic instruction is a SUBE subtraction instruction, the system number of bits of the target platform is 64 bits, and the operand of the SUBE subtraction instruction includes an immediate, a subtraction opcode DSUBiu corresponding to the SUBE opcode is determined.

Preferably, operands of the ADDE add instruction and the subscribe subtract instruction include: a first operand, a second operand, an input carry value;

the step of generating the arithmetic instruction of the target platform by adopting the operand and the target operation code comprises the following steps:

generating a DADDu addition instruction by adopting the first operand, the second operand and the addition operation code DADDu; or the like, or, alternatively,

generating a DSUBu subtraction instruction by using the first operand, the second operand and the subtraction operation code DSUBu; or the like, or, alternatively,

generating a DADDiu addition instruction by using the first operand, the second operand and the addition operation code DADDiu; or the like, or a combination thereof,

generating a DSUBiu subtraction instruction by using the first operand, the second operand and the subtraction operation code DSUBiu;

generating an output carry value calculation instruction by adopting the input carry value, the first operand and the second operand;

combining the DADDu addition instruction and the output carry value calculation instruction to serve as an addition instruction corresponding to the ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

combining the DSUBu subtraction instruction and the output carry value calculation instruction to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform; or the like, or, alternatively,

combining the DADDiu addition instruction and the output carry value calculation instruction to serve as an addition instruction corresponding to the ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

and combining the DSUBiu subtraction instruction and the output carry value calculation instruction to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform.

Preferably, the step of generating an output carry value calculating instruction using the input carry value, the first operand and the second operand comprises:

for the DADDu addition instruction, generating a first output carry value calculation instruction; the first output carry value calculation instruction is used for executing the operation result of the DADDu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

for the DSUBu subtraction instruction, generating a second output carry value calculation instruction; the second output carry value calculation instruction is used for comparing the first operand and the second operand and determining a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

generating a third output carry value calculation instruction for the DADDiu addition instruction; the third output carry value calculation instruction is used for executing the operation result of the DADDiu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

generating a fourth output carry value calculation instruction for the DSUBiu subtraction instruction; the fourth output carry value calculation instruction is for performing a comparison of the first operand and the second operand to determine a subtraction borrowing value; and subtracting the subtraction borrowing value from the input carry value to obtain the operation of outputting the carry value.

Preferably, the step of generating an output carry value calculation instruction using the input carry value, the first operand, and the second operand further comprises:

generating a specific output carry value calculation instruction; the specific output carry value calculation instruction is used for executing the operation of taking the input carry value as the output carry value if the second operand of the ADDE addition instruction or the SUBE subtraction instruction is 0.

The embodiment of the invention also discloses an instruction conversion device, which comprises:

the arithmetic instruction acquisition module is used for acquiring an arithmetic instruction of an LLVM compiler intermediate code;

an operation parameter determining module, configured to determine an operand and an operation code of an arithmetic instruction of the LLVM compiler intermediate code;

the system digit determining module is used for determining the system digit of the target platform;

a target operation code determining module, configured to determine, in an instruction set of the target platform, a target operation code corresponding to an arithmetic instruction operation code of the LLVM compiler intermediate code and the system bit number;

and the arithmetic instruction generating module is used for generating an arithmetic instruction of the target platform by adopting the operand and the target operation code.

the target opcode determination module includes:

a first operation code determining submodule, configured to determine an addition operation code DADDu corresponding to the ADDC operation code if the arithmetic instruction is an ADDC addition instruction, the system bit number of the target platform is 64 bits, and an operand of the ADDC addition instruction does not include an immediate number;

a second operation code determining submodule, configured to determine a subtraction operation code DSUBu corresponding to the subs operation code if the arithmetic instruction is a subs subtraction instruction, the system bit number of the target platform is 64 bits, and an operand of the subs subtraction instruction does not include an immediate number;

a third operation code determining submodule, configured to determine an addition operation code DADDiu corresponding to the ADDC operation code if the arithmetic instruction is an ADDC addition instruction, the system bit number of the target platform is 64 bits, and an operand of the ADDC addition instruction includes an immediate number;

and the fourth operation code determining submodule is used for determining a subtraction operation code DSUBiu corresponding to the SUBC operation code if the arithmetic instruction is an SUBC subtraction instruction, the system bit number of the target platform is 64 bits, and the operand of the SUBC subtraction instruction contains an immediate number.

Preferably, operands of the ADDC add instruction and the subs subtract instruction include: a first operand and a second operand; the arithmetic instruction generation module comprises:

the first arithmetic instruction generation submodule is used for generating an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by adopting the first operand, the second operand and the addition operation code DADDu; or the like, or, alternatively,

the second arithmetic instruction generation submodule is used for generating a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform by adopting the first operand, the second operand and the subtraction operation code DSUBu; or the like, or, alternatively,

a third operand instruction generation submodule, configured to generate an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by using the first operand, the second operand, and the addition opcode DADDiu; or the like, or, alternatively,

and the fourth arithmetic instruction generation submodule is used for generating a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform by adopting the first operand, the second operand and the subtraction operation code DSUBiu.

the target opcode determination includes:

a fifth operation code determining submodule, configured to determine an addition operation code DADDu corresponding to the ADDE operation code if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 64 bits, and an operand of the ADDE addition instruction does not include an immediate number;

a sixth opcode determining sub-module, configured to determine a subtraction opcode DSUBu corresponding to the subscribe opcode if the arithmetic instruction is a subscribe subtraction instruction, the system bits of the target platform are 64 bits, and an operand of the subscribe subtraction instruction does not include an immediate;

a seventh operation code determining submodule, configured to determine an addition operation code DADDiu corresponding to the ADDE operation code if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 64 bits, and an operand of the ADDE addition instruction includes an immediate number;

an eighth opcode determining sub-module, configured to determine a subtraction opcode DSUBiu corresponding to the subscribe opcode if the arithmetic instruction is a subscribe subtraction instruction, the system bits of the target platform are 64 bits, and an operand of the subscribe subtraction instruction includes an immediate.

the arithmetic instruction generation module comprises:

a fifth arithmetic instruction generation submodule, configured to generate a DADDu addition instruction by using the first operand, the second operand, and the addition operation code DADDu; or the like, or, alternatively,

a sixth arithmetic instruction generation submodule, configured to generate a DSUBu subtraction instruction by using the first operand, the second operand, and the subtraction operation code DSUBu; or the like, or, alternatively,

a seventh arithmetic instruction generating submodule, configured to generate a DADDiu addition instruction by using the first operand, the second operand, and the addition operation code DADDiu; or the like, or, alternatively,

an eighth arithmetic instruction generation submodule, configured to generate a DSUBiu subtraction instruction by using the first operand, the second operand, and the subtraction operation code DSUBiu;

the output carry value calculation instruction generation submodule is used for generating an output carry value calculation instruction by adopting the input carry value, the first operand and the second operand;

a ninth arithmetic instruction generation submodule, configured to combine the DADDu addition instruction and the output carry value calculation instruction, and use the result as an addition instruction corresponding to the ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

a tenth arithmetic instruction generation submodule, configured to combine the DSUBu subtraction instruction and the output carry value calculation instruction, and use the calculation result as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform; or the like, or, alternatively,

an eleventh arithmetic instruction generation submodule, configured to combine the DADDiu addition instruction and the output carry value calculation instruction, and use the result as an addition instruction corresponding to the ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

and the twelfth arithmetic instruction generation submodule is used for combining the DSUBiu subtraction instruction and the output carry value calculation instruction to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform.

Preferably, the output carry value calculation instruction generation submodule includes:

a first output carry value calculation unit configured to generate a first output carry value calculation instruction for the DADDu addition instruction; the first output carry value calculation instruction is used for executing the operation result of the DADDu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

a second output carry value calculation unit for generating a second output carry value calculation instruction for the DSUBu subtraction instruction; the second output carry value calculation instruction is used for comparing the first operand and the second operand and determining a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

a third output carry value calculation unit configured to generate a third output carry value calculation instruction for the DADDiu addition instruction; the third output carry value calculation instruction is used for executing the operation result of the DADDiu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

a fourth output carry value calculation unit for generating a fourth output carry value calculation instruction for the DSUBiu subtraction instruction; the fourth output carry value calculation instruction is for performing a comparison of the first operand and the second operand to determine a subtraction borrowing value; and subtracting the subtraction borrowing value from the input carry value to obtain the operation of outputting the carry value.

Preferably, the output carry value calculation instruction generation submodule further includes:

a specific output carry value calculation unit for generating a specific output carry value calculation instruction; the specific output carry value calculation instruction is used for executing the operation of taking the input carry value as the output carry value if the second operand of the ADDE addition instruction or the SUBE subtraction instruction is 0.

The embodiment of the invention also discloses an electronic device, which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and is characterized in that the processor executes the program to realize the following steps:

acquiring an arithmetic instruction of an LLVM compiler intermediate code;

determining the system digit of a target platform;

The embodiment of the invention also discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer readable storage medium is characterized in that the computer readable storage medium is used for realizing the steps of the method when the computer program is executed by a processor.

The embodiment of the invention has the following advantages:

in the embodiment of the present invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the target platform, the arithmetic instruction matched with the system bit number of the target system can be generated according to the system bit number of the target platform.

In the embodiment of the invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the MIPS platform, for the 32-bit MIPS platform, the LLVM compiler can convert the arithmetic instruction (ADDC/SUBC/ADDE/SUBE instruction) of the intermediate code into the arithmetic instruction on the 32-bit MIPS platform. For a 64-bit MIPS platform, the LLVM compiler may convert the intermediate code arithmetic instructions (ADDC/subsc/ADDE/subscribe instructions) into arithmetic instructions on the 64-bit MIPS platform.

Drawings

FIG. 1 is a flowchart of the steps of an embodiment 1 of a method for instruction translation according to the present invention;

FIG. 2 is a flowchart illustrating steps of an embodiment 2 of a method for instruction translation according to the present invention;

FIG. 3 is a flowchart of the steps of an embodiment 3 of a method for instruction translation according to the present invention;

FIG. 4 is a block diagram of an embodiment of an instruction converting apparatus according to the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 1, a flowchart illustrating steps of embodiment 1 of an instruction conversion method according to the present invention is shown, which may specifically include the following steps:

step 101, acquiring an arithmetic instruction of an LLVM compiler intermediate code;

in the process of converting the instructions of the high-level language into the instructions of the target platform by the LLVM compiler, the LLVM compiler firstly converts the instructions of the high-level language into the instructions of the intermediate language IR, and then converts the instructions of the intermediate language IR into the instructions with SelectionDAG nodes.

In the embodiment of the present invention, the arithmetic instruction of the intermediate code is an arithmetic instruction with a selectordag node. The SelectionDAG node of the arithmetic instruction may include: multi-precision addition nodes ADDC and ADDE, and multi-precision subtraction nodes SUBC and SUBE.

ADDC/subsc is a carry-setting node for multi-precision addition and subtraction, has two operands of the same type, and produces two results, the first being the result of normal addition or subtraction, and the second being the carry-flag result.

ADDE/subscribe is a carry-applying node for multi-precision addition and subtraction, which has three operands, the first two being left and right numbers that are normally added or subtracted, the third operand being an input to a carry flag, and which produces two results, the first being the normally added or subtracted result, and the second being an output of the carry flag. These nodes both read and write a carry flag to allow them to concatenate the addition and subtraction of arbitrarily large numbers together.

102, determining an operand and an operation code of an arithmetic instruction of the LLVM compiler intermediate code;

an arithmetic instruction with a selectordag node includes an operand and an opcode, where the opcode is the selectordag node.

Operands correspond to the inputs to the instruction, and opcodes describe the way the inputs are processed.

103, determining the system digit of the target platform;

in an embodiment of the present invention, the target platform may include a MIPS platform. The number of system bits for the MIPS platform may include 32 bits and 62 bits.

Specifically, the number of system bits of the MIPS platform can be determined by an ABI (Application Binary Interface).

On mips platforms, the system bit number is 32 bits or 64 bits, which are distinguished by ABI of o32 or n 64.

104, determining an arithmetic instruction operation code of the LLVM compiler intermediate code and a target operation code corresponding to the system bit number in an instruction set of the target platform;

the essence of converting the instructions of the intermediate code into instructions of the target platform is that the instructions having the same function as the arithmetic of the intermediate code are generated by using the operation codes in the instruction set of the target platform.

The target operation code may be a preset operation code that can implement the function of the algorithm instruction of the intermediate code.

The operation codes for implementing the function of the algorithm instructions of the intermediate code may be different for target platforms of different system bit numbers. Therefore, it is necessary to select an operation code matching the system bit number of the target platform.

And 105, generating an arithmetic instruction of the target platform by adopting the operand and the target operation code.

And generating the instruction of the target platform by adopting the operand of the arithmetic instruction of the intermediate code and the target operation code in the instruction set of the target platform.

For example, an instruction of the MIPS platform is generated by using an operand of an arithmetic instruction of the intermediate code and a target opcode in an instruction set of the MIPS platform.

In the embodiment of the present invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the target platform, the LLVM compiler may generate the arithmetic instruction matching the system bit number of the target system according to the system bit number of the target platform.

Referring to fig. 2, a flowchart of steps of embodiment 2 of an instruction conversion method according to the present invention is shown, where the target platform is an MIPS (Microprocessor without interlocked pipeline stages) platform, and the method specifically includes the following steps:

step 201, acquiring an arithmetic instruction of an LLVM compiler intermediate code; the arithmetic instruction of the intermediate code comprises: ADDC add instructions and subs subtract instructions;

step 202, determining operands and operation codes of the arithmetic instructions of the LLVM compiler intermediate code;

in an embodiment of the invention, the operation code of the ADDC addition instruction is an ADDC operation code; the operation code of the SUBC subtraction instruction is an SUBC operation code;

step 203, determining the system digit of the MIPS platform;

MIPS platforms may include 32-bit systems and 64-bit systems.

Step 204, in an instruction set of the MIPS platform, determining an arithmetic instruction operation code of an intermediate code of the LLVM compiler and a target operation code corresponding to the system bit number;

in an embodiment of the present invention, the step 204 may include the following sub-steps:

substep S11, if the arithmetic instruction is an ADDC add instruction, the system bit number of the target platform is 64 bits, and the operand of the ADDC add instruction does not include an immediate number, determining an add opcode DADDu corresponding to the ADDC opcode;

sub-step S12, if the arithmetic instruction is a subs subtraction instruction, the system number of bits of the target platform is 64 bits, and the operand of the subs subtraction instruction does not include an immediate number, determining a subtraction opcode DSUBu corresponding to the subs opcode;

in sub-step S13, if the arithmetic instruction is an ADDC add instruction, the system bit number of the target platform is 64 bits, and the operand of the ADDC add instruction includes an immediate number, determining an add opcode DADDiu corresponding to the ADDC opcode;

sub-step S14, if the arithmetic instruction is a subs subtraction instruction, the number of system bits of the target platform is 64 bits, and an operand of the subs subtraction instruction includes an immediate number, determining a subtraction opcode DSUBiu corresponding to the subs opcode;

in substep S15, if the arithmetic instruction is an ADDC add instruction, the system bit number of the target platform is 32 bits, and the operand of the ADDC add instruction does not include an immediate number, determining an add opcode ADDu corresponding to the ADDC opcode;

sub-step S16, if the arithmetic instruction is a subs subtraction instruction, the system number of bits of the target platform is 32 bits, and the operand of the subs subtraction instruction does not include an immediate number, determining a subtraction opcode susu corresponding to the subs opcode;

in the substep S17, if the arithmetic instruction is an ADDC addition instruction, the system bit number of the target platform is 32 bits, and the operand of the ADDC addition instruction includes an immediate number, determining an addition opcode ADDiu corresponding to the ADDC opcode;

in sub-step S18, if the arithmetic instruction is a subs subtraction instruction, the number of system bits of the target platform is 32 bits, and the operand of the subs subtraction instruction includes an immediate number, a subtraction opcode subsu corresponding to the subs opcode is determined.

Step 205, generating an arithmetic instruction of the MIPS platform by using the operand and the target opcode.

In an embodiment of the present invention, the operands of the ADDC add instruction and the subs subtract instruction comprise: a first operand and a second operand;

the first operand is in particular the Left operand LHS (Left-handle Side) and the second operand is in particular the right operand RHS (right-handle Side).

The step 205 may comprise the following sub-steps:

substep S21, generating an add instruction corresponding to the ADDC add instruction on the 64-bit target platform using the first operand, the second operand, and the add opcode DADDu; or the like, or, alternatively,

if the system bit number of the MIPS platform is 64 bits and the operand of the ADDC addition instruction does not contain an immediate number, the first operand, the second operand and an addition operation code DADDu are adopted to generate the addition instruction corresponding to the ADDC addition instruction on the 64-bit MIPS platform.

Sub-step S22, generating a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform by using the first operand, the second operand, and the subtraction opcode DSUBu; or the like, or a combination thereof,

if the system bit number of the MIPS platform is 64 bits and the operand of the SUBC subtraction instruction does not contain an immediate number, the first operand, the second operand and a subtraction operation code DSUBu are adopted to generate the subtraction instruction corresponding to the SUBC subtraction instruction on the 64-bit MIPS platform.

Substep S23, generating an add instruction corresponding to the ADDC add instruction on the 64-bit target platform by using the first operand, the second operand, and the add opcode DADDiu; or the like, or, alternatively,

if the system bits of the MIPS platform are 64 bits and the operand of the ADDC addition instruction includes an immediate, an addition instruction corresponding to the ADDC addition instruction on the 64-bit MIPS platform is generated by using the first operand, the second operand, and the addition opcode DADDiu.

A substep S24, generating a subtraction instruction corresponding to the subs subtraction instruction on the 64-bit target platform by using the first operand, the second operand, and the subtraction operation code DSUBiu; or the like, or a combination thereof,

if the system bit number of the MIPS platform is 64 bits and the operand of the SUBC subtraction instruction comprises an immediate number, a subtraction instruction corresponding to the SUBC subtraction instruction on the 64-bit MIPS platform is generated by adopting the first operand, the second operand and a subtraction operation code DSUBiu.

Substep S25, generating an add instruction corresponding to the ADDC add instruction on the 32-bit destination platform using the first operand, the second operand, and the add opcode ADDu; or the like, or, alternatively,

if the number of system bits of the MIPS platform is 32 bits and the operands of the ADDC addition instruction do not include an immediate number, the first operand, the second operand and the addition operation code ADDu are adopted to generate the addition instruction corresponding to the ADDC addition instruction on the 32-bit MIPS platform.

A substep S26, generating a subtraction instruction corresponding to the SUBC subtraction instruction on the 32-bit target platform by using the first operand, the second operand, and the subtraction opcode SUBu; or the like, or, alternatively,

if the system bit number of the MIPS platform is 32 bits and the operand of the SUBC subtraction instruction does not contain an immediate number, the first operand, the second operand and a subtraction operation code SUBu are adopted to generate the subtraction instruction corresponding to the SUBC subtraction instruction on the 32-bit MIPS platform.

Substep S27, generating an add instruction corresponding to the ADDC add instruction on the 32-bit destination platform using the first operand, the second operand, and the add opcode ADDiu; or the like, or, alternatively,

if the number of system bits of the MIPS platform is 32 bits and the operand of the ADDC addition instruction includes an immediate number, the addition instruction corresponding to the ADDC addition instruction on the 32-bit MIPS platform is generated by using the first operand, the second operand, and the addition operation code ADDiu.

And a substep S28, generating a subtraction instruction corresponding to the SUBC subtraction instruction on the 32-bit target platform by using the first operand, the second operand, and the subtraction opcode SUBiu.

If the system bit number of the MIPS platform is 32 bits and the operand of the SUBC subtraction instruction comprises an immediate number, a subtraction instruction corresponding to the SUBC subtraction instruction on the 32-bit MIPS platform is generated by adopting the first operand, the second operand and a subtraction operation code SUBiu.

In the embodiment of the present invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the MIPS platform, for the 32-bit MIPS platform, the LLVM compiler may convert the arithmetic instruction of the intermediate code (ADDC/subsc instruction) into the arithmetic instruction on the 32-bit MIPS platform. For a 64-bit MIPS platform, the LLVM compiler may convert the intermediate code arithmetic instruction (ADDC/subsc instruction) into an arithmetic instruction on the 64-bit MIPS platform.

In order to enable a person skilled in the art to better understand the embodiments of the present invention, the following description illustrates the embodiments of the present invention by way of example:

the following shows the codes for converting SUBC instruction into DSUBu subtraction instruction of 64-bit MIPS platform in the embodiment of the present invention:

where GPR64 indicates that the operand type is 64 bits, $ LHS indicates the left operand, and $ RHS indicates the right operand.

The SUBC instruction includes: opcode SUBC, 64 bits of left operand LHS and 64 bits of right operand RHS.

The DSUBu subtraction instruction includes: opcode DSUBu, 64-bit left operand LHS and 64-bit right operand RHS.

The following shows the addition instruction code of DSUBu for converting ADDC instruction into 64-bit MIPS platform according to the embodiment of the present invention:

wherein the ADDC instruction includes: an opcode ADDC, a 64 bit left operand LHS and a 64 bit right operand RHS.

The DADDu instruction includes: the opcode ADDDu, a 64-bit left operand LHS, and a 64-bit right operand RHS.

The following is the code for converting the ADDC instruction into a DADDiu addition instruction of a 64-bit MIPS platform in an embodiment of the present invention:

where, $ imm denotes the immediate number.

The ADDC instruction includes: the opcode ADDC, a 64-bit left operand LHS, and a 64-bit immediate imm.

The DADDiu instruction includes: the opcode DADDiu, a 64-bit left operand LHS, and a 64-bit immediate imm.

Referring to fig. 3, a flowchart of steps of embodiment 3 of the instruction conversion method according to the present invention is shown, where the target platform is an MIPS (Microprocessor with interlocked pipeline stages) platform, and the method specifically includes the following steps:

step 301, acquiring an arithmetic instruction of an LLVM compiler intermediate code; the arithmetic instruction of the intermediate code comprises: ADDE add and subscribe subtract instructions;

step 302, determining operands and operation codes of the arithmetic instructions of the LLVM compiler intermediate code;

in the embodiment of the present invention, the operation code of the ADDE addition instruction is an ADDE operation code; the operation code of the SUBE subtraction instruction is a SUBE operation code;

step 303, determining the system digit of the MIPS platform;

MIPS platforms may include 32-bit systems and 64-bit systems.

Step 304, in the instruction set of the MIPS, an arithmetic instruction operation code of the LLVM compiler intermediate code and a target operation code corresponding to the system bit number are determined;

in an embodiment of the present invention, the step 304 may include the following sub-steps:

in sub-step S31, if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 64 bits, and the operand of the ADDE addition instruction does not include an immediate number, determining an addition opcode DADDu corresponding to the ADDE opcode;

sub-step S32, if the arithmetic instruction is a subscribe subtraction instruction, the system number of bits of the target platform is 64 bits, and the operand of the subscribe subtraction instruction does not include an immediate, determining a subtraction opcode DSUBu corresponding to the subscribe opcode;

in the substep S33, if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 64 bits, and the operand of the ADDE addition instruction includes an immediate number, determining an addition opcode DADDiu corresponding to the ADDE opcode;

sub-step S34, if the arithmetic instruction is a subscribe subtraction instruction, the system number of bits of the target platform is 64 bits, and the operand of the subscribe subtraction instruction includes an immediate, determining a subtraction opcode DSUBiu corresponding to the subscribe opcode;

in the substep S35, if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 32 bits, and the operand of the ADDE addition instruction does not include an immediate number, determining an addition opcode ADDu corresponding to the ADDE opcode;

sub-step S36, if the arithmetic instruction is a subscribe subtraction instruction, the system number of bits of the target platform is 32 bits, and the operand of the subscribe subtraction instruction does not include an immediate number, determining a subtraction opcode SUBu corresponding to the subscribe opcode;

in the substep S37, if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 32 bits, and the operand of the ADDE addition instruction includes an immediate number, determining an addition opcode ADDiu corresponding to the ADDE opcode;

in sub-step S38, if the arithmetic instruction is a SUBE subtraction instruction, the system bits of the target platform are 32 bits, and the operand of the SUBE subtraction instruction includes an immediate, the subtraction opcode subou corresponding to the SUBE opcode is determined.

Step 305, generating an arithmetic instruction of the MIPS by using the operand and the target opcode.

In an embodiment of the present invention, the operands of the ADDE addition instruction and the SUBE subtraction instruction include: a first operand, a second operand, an input carry value;

the first operand is specifically a Left operand LHS (Left-Hand Side), the second operand is specifically a right operand RHS (right-Hand Side), and the input Carry value is the value of the input Carry flag Carry.

In an embodiment of the present invention, the step 305 may include the following sub-steps:

sub-step S41, generating a DADDu addition instruction using the first operand, the second operand, and the addition opcode DADDu; or the like, or a combination thereof,

if the system bit number of the MIPS platform is 64 bits and the operand of the ADDE addition instruction does not contain an immediate number, generating a DADDu addition instruction by adopting a first operand, a second operand and an addition operation code DADDu;

substep S42, generating a DSUBu subtraction instruction using the first operand, the second operand, and the subtraction opcode DSUBu;

if the system bit number of the MIPS platform is 64 bits and the operand of the SUBE subtraction instruction does not contain an immediate number, generating a DSUBu subtraction instruction by adopting a first operand, a second operand and a subtraction operation code DSUBu;

a substep S43, generating a DADDiu addition instruction by using the first operand, the second operand, and the addition opcode DADDiu;

if the number of systematic bits of the MIPS platform is 64 bits and the operand of the ADDE add instruction includes an immediate, the first operand, the second operand, and the add opcode, DADDiu, are used to generate the DADDiu add instruction.

A substep S44, generating a DSUBiu subtraction instruction using the first operand, the second operand, and the subtraction opcode DSUBiu;

if the number of systematic bits of the MIPS platform is 64 bits and the operand of the subscribe subtraction instruction includes an immediate, the DSUBiu subtraction instruction is generated by using the first operand, the second operand, and the subtraction operation code DSUBiu.

Substep S45, generating an ADDu add instruction using the first operand, the second operand, and the add opcode ADDu;

if the number of systematic bits of the MIPS platform is 32 bits and the operand of the ADDE add instruction does not include an immediate, an ADDu add instruction is generated using the first operand, the second operand, and the add opcode ADDu.

Substep S46, generating a SUBu subtraction instruction by using the first operand, the second operand, and the subtraction opcode SUBu;

if the system bit number of the MIPS platform is 32 bits and the operand of the SUBE subtraction instruction does not contain an immediate number, the SUBu subtraction instruction is generated by adopting the first operand, the second operand and a subtraction operation code SUBu.

A substep S47, generating an ADDiu addition instruction by using the first operand, the second operand, and the addition opcode ADDiu;

if the number of system bits of the MIPS platform is 32 bits and the operand of the ADDE add instruction includes an immediate, the ADDiu add instruction is generated using the first operand, the second operand, and the add opcode ADDiu.

Substep S48, generating a SUBiu subtraction instruction by using the first operand, the second operand, and the subtraction opcode SUBiu;

if the number of systematic bits of the MIPS platform is 32 bits and the operand of the SUBE subtraction instruction includes an immediate number, a subu subtraction instruction is generated by using the first operand, the second operand, and a subtraction operation code subu.

A substep S49 of generating an output carry value calculation instruction using the input carry value, the first operand, and the second operand;

in an embodiment of the present invention, the sub-step S49 may include the following sub-steps:

in substep S491, a first output carry value calculation instruction is generated for the DADDu addition instruction; the first output carry value calculation instruction is used for executing the operation result of the DADDu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

in the embodiment of the invention, the output carry values of different instructions are calculated in different manners.

For an instruction that performs an add operation, its output carry value is equal to the input carry value, plus the carry value of the add operation.

For an instruction that performs a subtraction operation, whose output carry value is equal to the input carry value, the borrow value of the subtraction operation is subtracted.

In particular, the compare instruction SLTu may be used to determine the addend value. The SLTu command means to set 1 if the condition is satisfied and to set 0 otherwise.

The result of the DADDu addition instruction is the sum of the first operand and the second operand. The SLTu instruction carries a 1 if the operation result of the DADDu addition instruction is smaller than any of the first operand or the second operand, otherwise it is 0, by comparing the operation result of the DADDu addition instruction with any of the first operand or the second operand. When the sum is judged to be smaller than any addend, carry is carried to 1, otherwise, carry is not carried.

Substep S492, for said DSUBu subtraction instruction, generating a second output carry value calculation instruction; the second output carry value calculation instruction is used for comparing the first operand and the second operand and determining a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

for a DSUBu subtraction instruction, the SLTu instruction compares the values of the first operand and the second operand, borrows 1 if less than, otherwise borrows 0. The first operand is equivalent to the subtracted number, the second operand is equivalent to the subtracted number, namely, when the subtracted number is judged to be smaller than the subtracted number, the bit is borrowed by 1, otherwise, the bit is borrowed by 0.

Substep S493 of generating a third output carry value calculation instruction for the DADDiu addition instruction; the third output carry value calculation instruction is used for executing the operation result of the DADDiu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

the result of the DADDiu addition instruction is the sum of the first operand and the second operand. The SLTu instruction compares the operation result of the DADDiu addition instruction with any one of the first operand or the second operand, carries a bit 1 if the operation result of the DADDiu addition instruction is smaller than any one of the first operand or the second operand, and otherwise is 0. When the sum is judged to be smaller than any addend, carry is carried to 1, otherwise, carry is not carried.

Substep S494, for the DSUBiu subtraction instruction, generating a fourth output carry value calculation instruction; the fourth output carry value calculation instruction is for performing a comparison of the first operand and the second operand to determine a subtraction borrowing value; and subtracting the subtraction borrowing value from the input carry value to obtain the operation of outputting the carry value.

For a DSUBiu subtraction instruction, the SLTu instruction compares the values of the first operand and the second operand, borrows 1 if less than, otherwise borrows 0. The first operand is equivalent to the subtracted number, the second operand is equivalent to the subtracted number, namely, when the subtracted number is judged to be smaller than the subtracted number, the bit is borrowed by 1, otherwise, the bit is borrowed by 0.

Substep S495, for the ADDu add instruction, generating a fifth output carry value calculation instruction; the fifth output carry value calculation instruction is used for executing the operation result adopting the ADDu addition instruction, and comparing the operation result with the first operand and the second operand respectively to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

the result of the ADDu add instruction is the sum of the first operand and the second operand. The SLTu instruction compares the operation result of the ADDu addition instruction with any one of the first operand or the second operand, carries a bit 1 if the operation result of the ADDu addition instruction is smaller than any one of the first operand or the second operand, and otherwise is 0. When the sum is judged to be smaller than any addend, carry is carried to 1, otherwise, carry is not carried.

Substep S496, for the SUBu subtraction instruction, generating a sixth output carry value calculation instruction; the sixth output carry value calculation instruction is to perform a comparison of the first operand and the second operand to determine a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

for the SUBu subtraction instruction, the SLTu instruction compares the values of the first operand and the second operand, borrows 1 if less than, otherwise borrows 0. The first operand is equivalent to the subtracted number, the second operand is equivalent to the subtracted number, namely, when the subtracted number is judged to be smaller than the subtracted number, the bit is borrowed by 1, otherwise, the bit is borrowed by 0.

Substep S497 of generating a seventh output carry value calculation instruction for the ADDiu addition instruction; the seventh output carry value calculating instruction is used for executing the operation result of the ADDiu addition instruction, and the operation result is respectively compared with the first operand and the second operand to determine an addition carry value; adding the input carry value and the addition carry value to obtain an output carry value;

the result of the ADDiu add instruction is the sum of the first operand and the second operand. The SLTu instruction compares the operation result of the ADDiu addition instruction with any one of the first operand or the second operand, carries a bit 1 if the operation result of the ADDiu addition instruction is smaller than any one of the first operand or the second operand, and otherwise is 0. When the sum is judged to be smaller than any addend, carry is carried to 1, otherwise, carry is not carried.

Substep S498 of generating an eighth output carry value calculation instruction for the SUBiu subtraction instruction; the eighth output carry value calculation instruction is to perform a comparison of the first operand and the second operand to determine a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

for the SUBiu subtraction instruction, the SLTu instruction compares the values of the first operand and the second operand, borrows 1 if less than, otherwise borrows 0. The first operand is equivalent to the subtracted number, the second operand is equivalent to the subtracted number, namely, when the subtracted number is judged to be smaller than the subtracted number, the bit is borrowed by 1, otherwise, the bit is borrowed by 0.

A substep S499 of generating a specific output carry value calculation instruction; the specific output carry value calculation instruction is used for executing the operation of taking the input carry value as the output carry value if the second operand of the ADDE addition instruction or the SUBE subtraction instruction is 0.

If the second operand of the ADDE addition instruction or the SUBE subtraction instruction is 0, the input carry value is taken as the output carry value.

Substep S50, combining the DADDu add instruction and the output carry value calculation instruction as an add instruction corresponding to the ADDE add instruction on a 64-bit target platform; or the like, or, alternatively,

a substep S51, combining the DSUBu subtraction instruction and the output carry value calculation instruction, to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform; or the like, or, alternatively,

substep S52, combining the DADDiu addition instruction and the output carry value calculation instruction as an addition instruction corresponding to the ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

a substep S53, combining the DSUBiu subtraction instruction and the output carry value calculation instruction, to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on a 64-bit target platform; or the like, or, alternatively,

substep S54, combining the ADDu add instruction and the output carry value calculation instruction as an add instruction corresponding to the ADDE add instruction on the 32-bit target platform; or the like, or, alternatively,

a substep S55, combining the SUBu subtraction instruction and the output carry value calculation instruction, to use them as the subtraction instruction corresponding to the subbe subtraction instruction on the 32-bit target platform; or the like, or, alternatively,

substep S56, combining the ADDiu add instruction and the output carry value calculation instruction as an add instruction corresponding to the ADDE add instruction on the 32-bit target platform; or the like, or, alternatively,

and a substep S57, combining the subu subtraction instruction and the output carry value calculation instruction, to serve as a subtraction instruction corresponding to the SUBE subtraction instruction on the 32-bit target platform.

In the embodiment of the invention, when the LLVM compiler converts the arithmetic instruction of the intermediate code into the arithmetic instruction of the MIPS platform, for the 32-bit MIPS platform, the LLVM compiler can convert the arithmetic instruction (ADDE/SUBE instruction) of the intermediate code into the arithmetic instruction on the 32-bit MIPS platform. For a 64-bit MIPS platform, the LLVM compiler may convert the arithmetic instruction (ADDE/subscribe instruction) of the intermediate code into an arithmetic instruction on the 64-bit MIPS platform.

In an embodiment of the invention, the ADDC add instruction includes only two operands, outputting the added value of the left operand LHS and the right operand RHS. The ADDE addition instruction comprises three operands, and outputs the addition value of the left operand LHS and the right operand RHS and the carry value; the output carry value is equal to the input carry value plus the added carry value of the left operand LHS and the right operand RHS.

Therefore, the addition instruction added to the corresponding instruction of the MIPS platform is added with only one SLTu comparison instruction for indicating the carry value, compared with the addition instruction added to the corresponding instruction of the MIPS platform.

For example, the instruction to convert the ADDC add instruction to a 64-bit MIPS is: a DADDu add instruction;

instructions to convert the ADDE add instruction to a 64-bit MIPS include: a DADD add instruction, and a SLTu compare instruction to indicate a carry value.

the code for converting the ADDE instruction to an add instruction for the 32-bit or 64-bit MIPS platform in an embodiment of the present invention is shown below.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Referring to fig. 4, a block diagram of a structure of an embodiment of an instruction converting apparatus of the present invention is shown, which may specifically include the following modules:

an arithmetic instruction obtaining module 401, configured to obtain an arithmetic instruction of an LLVM compiler intermediate code;

an operation parameter determining module 402, configured to determine an operand and an operation code of an arithmetic instruction of the LLVM compiler intermediate code;

a system digit determining module 403, configured to determine a system digit of the target platform;

a target operation code determining module 404, configured to determine, in the instruction set of the target platform, a target operation code corresponding to the arithmetic instruction operation code of the LLVM compiler intermediate code and the system bit number;

an arithmetic instruction generating module 405, configured to generate an arithmetic instruction of the target platform by using the operand and the target opcode.

In an example of the embodiment of the present invention, the target platform is an MIPS platform, and the arithmetic instruction includes: ADDC add and subs subtract instructions; the operation code of the ADDC addition instruction is an ADDC operation code; the operation code of the SUBC subtraction instruction is an SUBC operation code;

the target opcode determination module 404 may include:

In an embodiment of the present invention, the operands of the ADDC add instruction and the subs subtract instruction comprise: a first operand and a second operand; the arithmetic instruction generation module 405 may include:

the first arithmetic instruction generation submodule is used for generating an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by adopting the first operand, the second operand and the addition operation code DADDu; or the like, or a combination thereof,

In another example of the embodiment of the present invention, the target platform is an MIPS platform, and the arithmetic instruction includes: ADDE add and subscribe subtract instructions; the operation code of the ADDE addition instruction is an ADDE operation code; the operation code of the SUBE subtraction instruction is a SUBE operation code;

the target opcode determination 404 may include:

In an embodiment of the present invention, operands of the ADDE add instruction and the SUBE subtract instruction include: a first operand, a second operand, an input carry value;

the arithmetic instruction generation module 405 may include:

In an embodiment of the present invention, the output carry value calculation instruction generation submodule may include:

In this embodiment of the present invention, the output carry value calculation instruction generation sub-module may further include:

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

acquiring an arithmetic instruction of an LLVM compiler intermediate code;

determining the system digit of a target platform;

Preferably, the processor when executing the program further realizes the following steps:

Preferably, the processor, when executing the program, may further implement the steps of:

if the arithmetic instruction is a SUBE subtraction instruction, the system digits of the target platform are 64 bits, and the operand of the SUBE subtraction instruction does not contain an immediate number, determining a subtraction operation code DSUBu corresponding to the SUBE operation code;

generating a DSUBu subtraction instruction by using the first operand, the second operand and the subtraction operation code DSUBu; or the like, or a combination thereof,

generating a DADDiu addition instruction by using the first operand, the second operand and the addition operation code DADDiu; or the like, or, alternatively,

combining the DADDu addition instruction and the output carry value calculation instruction to serve as an addition instruction corresponding to an ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

combining the DADDiu addition instruction and the output carry value calculation instruction to serve as an addition instruction corresponding to an ADDE addition instruction on a 64-bit target platform; or the like, or, alternatively,

The embodiment of the invention also discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is used for realizing the method of the embodiment of the invention when being executed by a processor.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the true scope of the embodiments of the present invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or terminal equipment comprising the element.

The above detailed description is provided for an instruction conversion method and an instruction conversion apparatus provided by the present invention, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. An instruction conversion method, comprising:

determining a system bit number of a target platform, wherein the system bit number comprises 32 bits and 64 bits;

2. The method of claim 1, wherein the target platform is a MIPS platform, and wherein the arithmetic instruction comprises: ADDC add instructions and subs subtract instructions; the operation code of the ADDC addition instruction is an ADDC operation code; the operation code of the SUBC subtraction instruction is an SUBC operation code;

3. The method of claim 2, wherein operands of the ADDC add instruction and the subsc subtract instruction comprise: a first operand and a second operand; the step of generating the arithmetic instruction of the target platform by adopting the operand and the target operation code comprises the following steps:

adopting the first operand, the second operand and the subtraction operation code DSUBu to generate a subtraction instruction corresponding to the SUBC subtraction instruction on a 64-bit target platform; or the like, or, alternatively,

generating an addition instruction corresponding to the ADDC addition instruction on a 64-bit target platform by adopting the first operand, the second operand and the addition operation code DADDiu; or the like, or, alternatively,

4. The method of claim 1, wherein the target platform is a MIPS platform, and wherein the arithmetic instruction comprises: ADDE add and subscribe subtract instructions; the operation code of the ADDE addition instruction is an ADDE operation code; the operation code of the SUBE subtraction instruction is a SUBE operation code;

the step of determining, in the instruction set of the target platform, the target opcode corresponding to the arithmetic instruction opcode of the LLVM compiler intermediate code and the system bit number comprises:

if the arithmetic instruction is an ADDE addition instruction, the system bit number of the target platform is 64 bits, and the operand of the ADDE addition instruction does not contain an immediate number, determining an addition operation code DADDu corresponding to the ADDE operation code;

5. The method of claim 4, wherein operands of the ADDE add instruction and the SUBE subtract instruction comprise: a first operand, a second operand, an input carry value;

generating a DADDu addition instruction by adopting the first operand, the second operand and the addition operation code DADDu; or the like, or a combination thereof,

combining the DADDiu addition instruction and the output carry value calculation instruction to serve as an addition instruction corresponding to an ADDE addition instruction on a 64-bit target platform; or the like, or a combination thereof,

6. The method of claim 5, wherein the step of generating an output carry calculation instruction using the input carry value, a first operand, and the second operand comprises:

7. The method of claim 5 or 6, wherein the step of generating an output carry value calculation instruction using the input carry value, the first operand, and the second operand further comprises:

8. An instruction converting apparatus, comprising:

the system bit number determining module is used for determining the system bit number of the target platform, wherein the system bit number comprises 32 bits and 64 bits;

a target operation code determining module, configured to determine, in an instruction set of the target platform, an arithmetic instruction operation code of the LLVM compiler intermediate code and a target operation code corresponding to the system bit number;

and the arithmetic instruction generating module is used for generating the arithmetic instruction of the target platform by adopting the operand and the target operation code.

9. The apparatus of claim 8, wherein the target platform is a MIPS platform, and wherein the arithmetic instructions comprise: ADDC add instructions and subs subtract instructions; the operation code of the ADDC addition instruction is an ADDC operation code; the operation code of the SUBC subtraction instruction is an SUBC operation code;

the target opcode determination module includes:

10. The apparatus of claim 9, wherein operands of the ADDC add instruction and the subsc subtract instruction comprise: a first operand and a second operand; the arithmetic instruction generation module comprises:

11. The apparatus of claim 8, wherein the target platform is a MIPS platform, and wherein the arithmetic instructions comprise: ADDE add and subscribe subtract instructions; the operation code of the ADDE addition instruction is an ADDE operation code; the operation code of the SUBE subtraction instruction is a SUBE operation code;

the target opcode determination includes:

12. The apparatus of claim 11, wherein operands of the ADDE add instruction and the subscribe subtract instruction comprise: a first operand, a second operand, an input carry value;

the arithmetic instruction generation module comprises:

13. The apparatus of claim 12, wherein the output carry value calculation instruction generation submodule comprises:

a second output carry value calculation unit for generating a second output carry value calculation instruction for the DSUBu subtraction instruction; the second output carry value calculation instruction is used for comparing the first operand with the second operand and determining a subtraction borrowing value; subtracting the subtraction borrowing value from the input carry value to obtain an output carry value;

a fourth output carry value calculation unit for generating a fourth output carry value calculation instruction for the DSUBiu subtraction instruction; the fourth output carry value calculation instruction is used for comparing the first operand with the second operand and determining a subtraction borrowing value; and subtracting the subtraction borrowing value from the input carry value to obtain the operation of outputting the carry value.

14. The apparatus of claim 12 or 13, wherein the output carry value calculation instruction generation submodule further comprises:

15. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the following steps when executing the program:

acquiring an arithmetic instruction of an LLVM compiler intermediate code;

16. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.