CN109491601A - Method for parallel processing, device and the readable storage medium storing program for executing of solid state hard disk data - Google Patents
Method for parallel processing, device and the readable storage medium storing program for executing of solid state hard disk data Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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Abstract
The invention discloses method for parallel processing, device and the computer readable storage mediums of a kind of solid state hard disk data, the method for parallel processing of the solid state hard disk data is the following steps are included: after the current slice choosing of destination channel has executed corresponding operation, be selected as starting point with the current slice, by hardware according to whether have in destination channel described in preset order cycle detection piece choosing be in idle condition；When having detected that piece choosing is in idle condition, is then selected from the piece being in idle condition and obtain the corresponding mapping address of next operation in corresponding linked list head；The corresponding opposite deviant in the chained list buffer area of next operation is obtained according to the mapping address, and next operation is obtained in the operation information of control buffer area according to the opposite deviant, and the piece choosing being in idle condition described in control executes next operation.The present invention has through linked list data structure, the technical effect of the optimal execution sequence operated.
Description
Technical field
The present invention relates to the method for parallel processing of technical field of data storage more particularly to solid state hard disk data, device and
Readable storage medium storing program for executing.
Background technique
In the prior art, in order to allow solid state hard disk (SSD) product to possess faster read or write speed, flash controller has more
A channel and many piece choosings achieve the effect that parallel work-flow non-volatile flash memory to control non-volatile flash memory (Flash).It is existing
Have in technology, parallel between control channel and piece choosing, need are carried out by the firmware (FW, Firmware) carried in flash controller
A large amount of software code is wanted to guarantee the concurrency between channel and piece choosing, but software code is easy to appear defect (Bug), and
Debug time is needed, and implementation procedure occupies the resource of central processing unit very much.
Summary of the invention
The main purpose of the present invention is to provide method for parallel processing, device and the readable storages of a kind of solid state hard disk data
Medium, it is intended to solve in the prior art by being easy to appear asking for defect parallel between firmware realization control channel and piece choosing
Topic.
To achieve the above object, the present invention provides a kind of method for parallel processing of solid state hard disk data, the solid state hard disk
Including flash controller and flash array, the flash controller has the multiple channels connecting with flash array, each channel
It is selected including multiple, and the flash controller includes control buffer area and chained list, the chained list includes chained list buffer area and more
A linked list head, the method for parallel processing of the solid state hard disk data the following steps are included:
After the current slice choosing of destination channel has executed corresponding operation, starting point is selected as with the current slice, according to default
Whether there is piece choosing to be in idle condition in destination channel described in sequence cycle detection；
When having detected that piece choosing is in idle condition, then selects in corresponding linked list head and obtain from the piece being in idle condition
It is next to operate corresponding mapping address；
The corresponding opposite deviant in the chained list buffer area of next operation is obtained according to the mapping address,
And next operation is obtained in the operation information of control buffer area according to the opposite deviant, and control described in the free time
The piece choosing of state executes next operation.
Preferably, described select from the piece being in idle condition obtains the corresponding mapping ground of next operation in corresponding linked list head
Before the step of location, further includes:
Judge that the piece being in idle condition selects whether corresponding linked list head is empty；
If so, skipping the piece being in idle condition choosing, continue to execute described according to described in preset order cycle detection
Whether piece choosing be in idle condition the step of is had in destination channel；
If it is not, then executing described select from the piece being in idle condition obtains that next operation is corresponding to reflect in corresponding linked list head
The step of penetrating address.
Preferably, described after the current slice choosing of destination channel has executed corresponding operation, it has been selected as with the current slice
Point, according to whether have in destination channel described in preset order cycle detection piece choosing be in idle condition the step of before, further includes:
The operation information to the flash array is written in opposite deviation post into the control buffer area.
Preferably, the operation information includes that channel information, piece select information, row address, column address, the data volume to be operated
And operational order.
Preferably, the operation of the flash array is believed in the opposite deviation post write-in into the control buffer area
After the step of breath, further includes:
Opposite deviant in the control buffer area is written in the idle node of the chained list buffer area.
Preferably, the chain is written in the corresponding opposite deviant of opposite deviation post by the control buffer area
After step in table cache area, further includes:
Scan the channel in the control buffer area and piece choosing；
The current final node position that the chained list buffer area is obtained in corresponding linked list head is selected from described；
By the idle node carry after the current final node position, using the idle node as working as
Preceding final node.
Preferably, it after the step of piece choosing being in idle condition described in the control executes next operation, also wraps
It includes:
Next operation is discharged in control buffer area, the occupied space of chained list buffer area and changes chained list relationship.
Preferably, described that starting point is selected as with the current slice, according to being in destination channel described in preset order cycle detection
No have piece choosing the step of being in idle condition to include:
Storage unit into the flash array of current slice choosing connection sends inquiry instruction；
Judge that current slice choosing is in a busy state or idle state according to the feedback command of the storage unit.
In addition, to achieve the above object, the present invention also provides a kind of parallel processing apparatus of solid state hard disk data, features
It is, the parallel processing apparatus of the solid state hard disk data includes: memory, processor and is stored on the memory and can
The concurrent processor of the solid state hard disk data run on the processor, the concurrent processor of the solid state hard disk data
The step of realizing the method for parallel processing of solid state hard disk data as described above when being executed by the processor.
In addition, to achieve the above object, the present invention also provides a kind of computer readable storage mediums, which is characterized in that institute
State the concurrent processor that solid state hard disk data are stored on computer readable storage medium, the solid state hard disk data it is parallel
The step of method for parallel processing of solid state hard disk data as described above is realized when processing routine is executed by processor.
The present invention according to preset order detection current slice choosing and remaining piece by selecting after piece choosing has executed once-through operation
State, when there is piece to be selected as idle state, next operation is found in linked list head, chained list buffer area and the control buffer area selected by piece
Operation information, by linked list data structure, operated it is optimal execute sequence, avoid passing through a large amount of codes pair of firmware
Operation information is ranked up, and avoids the occurrence of defect, reduces the debug time of programmer, while reducing the burden of firmware.
Detailed description of the invention
Fig. 1 is the terminal structure schematic diagram for the hardware running environment that the embodiment of the present invention is related to；
Fig. 2 is the block schematic illustration of solid state hard disk of the present invention；
Fig. 3 is the flow diagram of the method for parallel processing first embodiment of solid state hard disk data of the present invention；
Fig. 4 is the flow diagram of the method for parallel processing second embodiment of solid state hard disk data of the present invention；
Fig. 5 is the flow diagram of the method for parallel processing 3rd embodiment of solid state hard disk data of the present invention；
Fig. 6 is the flow diagram of the method for parallel processing fourth embodiment of solid state hard disk data of the present invention；
Fig. 7 is the flow diagram of the 5th embodiment of method for parallel processing of solid state hard disk data of the present invention；
Fig. 8 is the flow diagram of the method for parallel processing sixth embodiment of solid state hard disk data of the present invention；
Fig. 9 is the flow diagram of the 7th embodiment of method for parallel processing of solid state hard disk data of the present invention.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
The primary solutions of the embodiment of the present invention are:
After the current slice choosing of destination channel has executed corresponding operation, starting point is selected as with the current slice, according to default
Whether there is piece choosing to be in idle condition in destination channel described in sequence cycle detection；
When having detected that piece choosing is in idle condition, then selects in corresponding linked list head and obtain from the piece being in idle condition
It is next to operate corresponding mapping address；
The corresponding opposite deviant in the chained list buffer area of next operation is obtained according to the mapping address,
And next operation is obtained in the operation information of control buffer area according to the opposite deviant, and control described in the free time
The piece choosing of state executes next operation.
In the prior art, in order to allow solid state hard disk (SSD) product to possess faster read or write speed, flash controller has more
A channel and many piece choosings achieve the effect that parallel work-flow non-volatile flash memory to control non-volatile flash memory (Flash).It is existing
Have in technology, parallel between control channel and piece choosing, need are carried out by the firmware (FW, Firmware) carried in flash controller
A large amount of software code is wanted to guarantee the concurrency between channel and piece choosing, but software code is easy to appear defect (Bug), and
Debug time is needed, and implementation procedure occupies the resource of central processing unit very much.
The present invention according to preset order detection current slice choosing and remaining piece by selecting after piece choosing has executed once-through operation
State, when there is piece to be selected as idle state, next operation is found in linked list head, chained list buffer area and the control buffer area selected by piece
Operation information, by linked list data structure, operated it is optimal execute sequence, avoid passing through a large amount of codes pair of firmware
Operation information is ranked up, and avoids the occurrence of defect, reduces programmer's debug time, while reducing the burden of firmware.
As shown in Figure 1, Fig. 1 is the terminal structure schematic diagram for the hardware running environment that the embodiment of the present invention is related to.
The terminal of that embodiment of the invention can be PC, be also possible to smart phone, tablet computer, portable computer etc. with aobvious
Show the packaged type terminal device of function.
As shown in Figure 1, the terminal may include: processor 1001, such as CPU, network interface 1004, user interface
1003, memory 1005, communication bus 1002.Wherein, communication bus 1002 is for realizing the connection communication between these components.
User interface 1003 may include display screen (Display), input unit such as keyboard (Keyboard), optional user interface
1003 can also include standard wireline interface and wireless interface.Network interface 1004 optionally may include that the wired of standard connects
Mouth, wireless interface (such as WI-FI interface).Memory 1005 can be high speed RAM memory, be also possible to stable memory
(non-volatile memory), such as magnetic disk storage.Memory 1005 optionally can also be independently of aforementioned processor
1001 storage device.
It will be understood by those skilled in the art that the restriction of the not structure paired terminal of terminal structure shown in Fig. 1, can wrap
It includes than illustrating more or fewer components, perhaps combines certain components or different component layouts.
As shown in Figure 1, as may include that operating system, network are logical in a kind of memory 1005 of computer storage medium
Believe the concurrent processor of module, Subscriber Interface Module SIM and solid state hard disk data.
In terminal shown in Fig. 1, network interface 1004 is mainly used for connecting background server, carries out with background server
Data communication；User interface 1003 is mainly used for connecting client (user terminal), carries out data communication with client；And processor
1001 can be used for calling the concurrent processor of the solid state hard disk data stored in memory 1005, and execute following operation:
After the current slice choosing of destination channel has executed corresponding operation, starting point is selected as with the current slice, according to default
Whether there is piece choosing to be in idle condition in destination channel described in sequence cycle detection；
When having detected that piece choosing is in idle condition, then selects in corresponding linked list head and obtain from the piece being in idle condition
It is next to operate corresponding mapping address；
The corresponding opposite deviant in the chained list buffer area of next operation is obtained according to the mapping address,
And next operation is obtained in the operation information of control buffer area according to the opposite deviant, and control described in the free time
The piece choosing of state executes next operation.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
Judge that the piece being in idle condition selects whether corresponding linked list head is empty；
If so, skipping the piece being in idle condition choosing, continue to execute described according to described in preset order cycle detection
Whether piece choosing be in idle condition the step of is had in destination channel；
If it is not, then executing described select from the piece being in idle condition obtains that next operation is corresponding to reflect in corresponding linked list head
The step of penetrating address.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
The operation information to the flash array is written in opposite deviation post into the control buffer area.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
Opposite deviant in the control buffer area is written in the idle node of the chained list buffer area.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
Scan the channel in the control buffer area and piece choosing；
The current final node position that the chained list buffer area is obtained in corresponding linked list head is selected from described；
By the idle node carry after the current final node position, using the idle node as working as
Preceding final node.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
Next operation is discharged in control buffer area, the occupied space of chained list buffer area and changes chained list relationship.
Further, processor 1001 can call the parallel processing journey of the solid state hard disk data stored in memory 1005
Sequence also executes following operation:
Storage unit into the flash array of current slice choosing connection sends inquiry instruction；
Judge that current slice choosing is in a busy state or idle state according to the feedback command of the storage unit.
Referring to Fig. 2, the solid state hard disk 10 of the invention includes at least flash controller 11, flash array 12 and centre
Device (CPU) 13 is managed, the flash controller 11 has the multiple channels 111 connecting with flash array, and each channel 111 includes more
A piece selects 112, and the flash controller 11 includes control buffer area 113 and chained list 114, and the chained list 114 includes a chain
Table cache area (not shown) and multiple linked list head (not shown).
Wherein, the control buffer area 113 is for receiving firmware performed by central processing unit 13 (Firmware) code
The operation information to the flash array 12 being written to the control buffer area 113, and by the behaviour to the flash array 12
Make information temporary storage in the opposite deviation post 1131 in the control buffer area 113；
For the data field of chained list buffer area in the chained list 114 for storing opposite deviant, this is suitable with respect to deviant
In a pointer, which is directed toward the operation information in the position of the control buffer area 113, that is, opposite deviant is remembered
The operation information is recorded at which with respect in deviation post 1131, while on the pointer field of the chained list buffer area also stores and have
The chain table pointer of one node and next node address；Linked list head in the chained list 114 is then used to record opposite deviant and exists
Which position of the chained list buffer area, and the linked list head is corresponded with described choosing.
It is not interfere with each other between the multiple channel 111, for executing operation to the flash array 12 parallel, it should be pointed out that
, each channel 111 includes that several pieces select 112, and each channel 111 can only execute certain a piece of choosing within the same time
Operation under 112, after current slice selects 112 execution complete corresponding operation, current slice selects 112 to enter RB state (flash memory battle array
The busy state of column), which will continue certain RB duration, and only at the end of the continuity duration, which selects and 112 could weigh
Idle state newly is returned to, the piece is re-executed and selects 112 corresponding next operations.
When current slice select 112 enter RB state after, central processing unit 13 start detect current slice select 112 under a piece of choosing
Whether 112 be in idle condition, it may appear that two kinds of results: (1) it is a piece of under to select 112 as idle state, then obtain a piece of choosing under this
112 corresponding operations, and it is a piece of under this select the 112 execution corresponding operation, it is a piece of under this to select the complete corresponding behaviour of 112 execution
After work, RB state can be also immediately entered；(2) a piece of under to select 112 to be still within RB state due to executing operation before this, then
Whether the central processing unit is a piece of under will test again selects 112 to be in idle condition.It loops back and forth like this, realizes more in channel
The concurrency that a piece selects 112 execution to operate.
Refering to Fig. 3, the method for parallel processing first embodiment of solid state hard disk data of the present invention, the solid state hard disk data
Method for parallel processing the following steps are included:
Step S10 is selected as starting point after the current slice choosing of destination channel has executed corresponding operation with the current slice,
It is in idle condition according to whether there is piece to select in destination channel described in preset order cycle detection；
In the present embodiment, it is not interfere with each other between the multiple channel, for executing operation to the flash array parallel,
It should be pointed out that each channel includes the choosing of several pieces, each channel can only be executed within the same time under certain a piece of choosing
Corresponding operation, when current slice choosing has executed corresponding operation after, current slice select immediately enter RB state (flash array
Busy state), which will continue certain time length, and only at the end of the continuity duration, piece choosing can just come back to sky
Not busy state re-executes the piece and selects corresponding next operation.
After current slice choosing enters RB state, central processing unit starts to detect whether a piece of choosing under current slice choosing is in
Idle state, it may appear that it is a piece of under two kinds of results (1) to be selected as idle state, then obtain it is a piece of under this select corresponding operation, and
A piece of choosing executes the corresponding operation under this, after a piece of choosing has executed the corresponding operation under this, can also immediately enter RB shape
State；(2) a piece of choosing is still within RB state due to executing operation before this under, then the central processing unit will test again next
Whether piece choosing is in idle condition；It loops back and forth like this, realizes that multiple choosings execute the concurrency operated in channel.
In the present embodiment, according to whether having piece choosing in destination channel described in preset order cycle detection in idle shape
State, for example, the destination channel has a choosing of 3 pieces: piece select 1, piece select 2 and piece select 3, piece select 1 execute at first it is corresponding under the piece selects 1
Operation to flash array, after being finished, which selects 1 in RB state and continues the RB time, at this point, described of detection selects 1
Whether it is in idle condition, if it is to be in idle condition that piece, which selects 1, piece, which selects, 1 can continue to execute corresponding operation, if it is not, detection
Described is selected whether 2 be in idle condition, if it is to be in idle condition that piece, which selects 2, piece selects the corresponding operation of 2 execution；
After piece selects the complete corresponding operation of 2 execution, described of detection selects whether 2 be in idle condition, if piece selects 2 to be in the free time
State, then piece, which selects, 2 can continue to execute corresponding operation, if it is not, described of detection selects whether 3 be in idle condition, if piece selects and 3 is
It is in idle condition, then piece selects the corresponding operation of 3 execution；
After piece selects the complete corresponding operation of 3 execution, described of detection selects whether 3 be in idle condition, if piece selects 3 to be in the free time
State, then piece, which selects, 3 can continue to execute corresponding operation, if it is not, detecting described again selects whether 1 be in idle condition, if piece
Selecting 1 is to be in idle condition, then piece selects the corresponding operation of 1 execution；
That is, the preset order is that first detection lug selects 1, then detection lug selects 2, rear detection lug selects 3, then piece selects 1 again, such as
This cycle detection, if in the detection process, certain is a piece of to be selected as idle state, then piece choosing will execute corresponding operation；In addition, also
It is noted that a corresponding linked list head per a piece of choosing, when certain is a piece of is selected as idle state, if the piece selects corresponding linked list head
For sky, then it can not obtain the piece and select corresponding operation, piece choosing, which will be skipped, does not execute operation.
Step S20 then selects corresponding chained list from the piece being in idle condition when having detected that piece choosing is in idle condition
The corresponding mapping address of next operation is obtained in head；
Each is selected a corresponding linked list head, which has recorded the mapping address that piece selects corresponding next operation,
Specifically, which is directed toward a certain position in chained list buffer area, and a certain position storage has an opposite deviant, should
Opposite deviant has been directed toward the specific storage position of next operation in control buffer area.
Step S30 obtains the corresponding phase in the chained list buffer area of next operation according to the mapping address
Next operation is obtained in the operation information of control buffer area to deviant, and according to the opposite deviant, and controls institute
It states the piece choosing being in idle condition and executes next operation.
In the present embodiment, it is an address that the opposite deviant is practical, and what the address was directed toward is in control buffer area
A certain position, and a certain position storage is information that piece selects corresponding next operation, finds next operation information
Afterwards, the piece being in idle condition choosing executes next operation.
In conclusion the present invention by piece choosing has executed once-through operation after, according to preset order detection current slice select and
The state of remaining piece choosing, when there is piece to be selected as idle state, linked list head, chained list buffer area and the control buffer area selected by piece are looked for
To the operation information of next operation, by linked list data structure, operated it is optimal execute sequence, avoid passing through firmware
A large amount of codes are ranked up operation information, avoid the occurrence of defect, reduce the debug time of programmer, while reducing the negative of firmware
Load.
Preferably, referring to Fig. 4, as the method for parallel processing second embodiment of solid state hard disk data of the present invention, this second
Embodiment is based on embodiment as shown in Figure 3, before the step S20, further includes:
Step S40: judge that the piece being in idle condition selects whether corresponding linked list head is empty；
If so, skipping the piece being in idle condition choosing, step S10 is continued to execute；
Continue step S20 if it is not, then executing.
In the present embodiment, if the piece being in idle condition selects whether corresponding linked list head is sky, which selects nothing
Method gets the mapping address of opposite deviant, also can not just get corresponding opposite deviant and operation information, can not hold
Row operation, therefore the piece being in idle condition choosing need to be skipped.
Preferably, referring to Fig. 5, as the method for parallel processing 3rd embodiment of solid state hard disk data of the present invention, the third
Embodiment is based on embodiment as shown in Figure 3-4, before the step S10, further includes:
Step S50: the operation information to the flash array is written in the opposite deviation post into the control buffer area.
In the present embodiment, the operation to the flash array is written in the opposite deviation post into control buffer area
Information, so that the piece choosing being in idle condition can find next operation information.The operation information includes but is not limited to
Channel information, piece select information, row address, column address, the data volume and operational order to be operated；The operational order includes but not
It is limited to reading order, writing commands, erasing instruction etc..
Preferably, referring to Fig. 6, as the method for parallel processing fourth embodiment of solid state hard disk data of the present invention, the 4th
Embodiment is based on embodiment as in Figure 3-5, before the S10, after step S50, further includes:
Step S60: the opposite deviant in the control buffer area is written in the idle node of the chained list buffer area.
In the present embodiment, the idle of the chained list buffer area is written in the opposite deviant in the control buffer area to save
In point, to find the opposite deviant of the chained list buffer area, and root according to the mapping address in the linked list head of described choosing
Next operation is found according to the opposite deviant.
Preferably, referring to Fig. 7, as the 5th embodiment of method for parallel processing of solid state hard disk data of the present invention, the 5th
Embodiment is based on embodiment as seen in figures 3-6, after the step S60, further includes:
Step S70: channel and piece choosing in the scanning control buffer area；
Step S80: the current final node position that the chained list buffer area is obtained in corresponding linked list head is selected from described
It sets；
Step S90: by the idle node carry after the current final node position, by the idle section
Point is as current final node.
In the present embodiment, it is selected by the scanning channel controlled in buffer area and piece, is corresponded to from described choosing
Linked list head in obtain the current final node position of the chained list buffer area, by the idle node carry in described current
Final node position after, using the idle node as current final node, so as to described be selected in obtain it is next
When operation, mapping address is first obtained from linked list head, being stored in the chained list buffer area is found further according to mapping address and works as
The opposite deviant of preceding final node, and next operation is found according to the opposite deviant.
Preferably, referring to Fig. 8, as the method for parallel processing sixth embodiment of solid state hard disk data of the present invention, the 6th
Embodiment is based on embodiment as shown in fig. 3 to 7, after the step S30, further includes:
Step S100: release next operation is in control buffer area, the occupied space of chained list buffer area and changes chain
Table relationship.
In the present embodiment, after the operation is finished by piece choosing, the operation pair in the chained list buffer area is discharged
The node for being used to store the operation in node and control buffer area where the opposite deviant answered, convenient for the phase of subsequent operation
Storage again to deviant and operation information.It is writable state by marking above-mentioned node, for new operation information, phase
The control buffer area is re-write, in chained list buffer area to deviant, improves the control buffer area, chained list buffer area is deposited
Store up resource utilization.
Preferably, referring to Fig. 9, as the 7th embodiment of method for parallel processing of solid state hard disk data of the present invention, the 7th
Embodiment is based on embodiment as shown in figures 3-8；The step S10 includes:
S11: the storage unit into the flash array of current slice choosing connection sends inquiry instruction；
S12: judge that current slice choosing is in a busy state or idle state according to the feedback command of the storage unit.
In the present embodiment, when whether detection lug choosing is in idle condition, according to the preset order to the flash memory
Storage unit in array sequentially sends inquiry instruction, and the flash array, which receives the inquiry instruction, can return to a feedback letter
Breath can determine whether that current slice choosing is in a busy state or idle state according to the feedback information.
In addition, the embodiment of the present invention also proposes a kind of parallel processing apparatus of solid state hard disk data, the solid state hard disk number
According to parallel processing apparatus include: memory, processor and be stored on the memory and can run on the processor
Solid state hard disk data concurrent processor, when the concurrent processor of the solid state hard disk data is executed by the processor
The step of realizing the method for parallel processing of solid state hard disk data described in as above each embodiment.
In addition, the embodiment of the present invention also proposes a kind of computer readable storage medium, the computer readable storage medium
On be stored with the concurrent processors of solid state hard disk data, the concurrent processor of the solid state hard disk data is executed by processor
Shi Shixian as above the method for parallel processing of solid state hard disk data described in each embodiment the step of.
It should be noted that, in this document, the terms "include", "comprise" or its any other variant are intended to non-row
His property includes, so that the process, method, article or the system that include a series of elements not only include those elements, and
And further include other elements that are not explicitly listed, or further include for this process, method, article or system institute it is intrinsic
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including being somebody's turn to do
There is also other identical elements in the process, method of element, article or system.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
Through the above description of the embodiments, those skilled in the art can be understood that above-described embodiment side
Method can be realized by means of software and necessary general hardware platform, naturally it is also possible to by hardware, but in many cases
The former is more preferably embodiment.Based on this understanding, technical solution of the present invention substantially in other words does the prior art
The part contributed out can be embodied in the form of software products, which is stored in one as described above
In storage medium (such as ROM/RAM, magnetic disk, CD), including some instructions are used so that terminal device (it can be mobile phone,
Computer, server, air conditioner or network equipment etc.) execute method described in each embodiment of the present invention.
The above is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of method for parallel processing of solid state hard disk data, which is characterized in that the solid state hard disk include flash controller and
Flash array, the flash controller have the multiple channels connecting with flash array, and each channel includes multiple and selects, and institute
It includes chained list buffer area and multiple linked list heads, the solid-state that flash controller, which is stated, including control buffer area and chained list, the chained list
The method for parallel processing of hard disc data the following steps are included:
After the current slice choosing of destination channel has executed corresponding operation, starting point is selected as with the current slice, according to preset order
Whether there is piece choosing to be in idle condition in destination channel described in cycle detection；
When detected piece choosing be in idle condition when, then selected from the piece being in idle condition obtained in corresponding linked list head it is next
Operate corresponding mapping address；
The corresponding opposite deviant in the chained list buffer area of next operation, and root are obtained according to the mapping address
Next operation is obtained in the operation information of control buffer area according to the opposite deviant, and is in idle condition described in control
Piece choosing execute next operation.
2. the method for parallel processing of solid state hard disk data as described in claim 1, which is characterized in that described from idle shape
The piece of state selected before the step of obtaining the corresponding mapping address of next operation in corresponding linked list head, further includes:
Judge that the piece being in idle condition selects whether corresponding linked list head is empty；
If so, skipping the piece being in idle condition choosing, continue to execute described according to target described in preset order cycle detection
Whether piece choosing be in idle condition the step of is had in channel；
If it is not, then executing described select from the piece being in idle condition obtains the corresponding mapping ground of next operation in corresponding linked list head
The step of location.
3. the method for parallel processing of solid state hard disk data as described in claim 1, which is characterized in that described when destination channel
After current slice choosing has executed corresponding operation, starting point is selected as with the current slice, according to target described in preset order cycle detection
Before whether thering is piece to select the step of being in idle condition in channel, further includes:
The operation information to the flash array is written in opposite deviation post into the control buffer area.
4. the method for parallel processing of solid state hard disk data as claimed in claim 3, which is characterized in that the operation information includes
Channel information, piece select information, row address, column address, the data volume and operational order to be operated.
5. the method for parallel processing of solid state hard disk data as claimed in claim 3, which is characterized in that described slow to the control
After depositing the step of opposite deviation post write-in in area is to the operation information of the flash array, further includes:
Opposite deviant in the control buffer area is written in the idle node of the chained list buffer area.
6. the method for parallel processing of solid state hard disk data as claimed in claim 5, which is characterized in that described that the control is slow
The opposite deviant in area is deposited to be written after the step in the idle node of the chained list buffer area, further includes:
Scan the channel in the control buffer area and piece choosing；
The current final node position that the chained list buffer area is obtained in corresponding linked list head is selected from described；
By the idle node carry after the current final node position, using the idle node as current
Final node.
7. the method for parallel processing of solid state hard disk data as described in claim 1, which is characterized in that be in described in the control
After the step of piece choosing of idle state executes next operation, further includes:
Next operation is discharged in control buffer area, the occupied space of chained list buffer area and changes chained list relationship.
8. the method for parallel processing of solid state hard disk data as described in claim 1, which is characterized in that described with the current slice
Be selected as starting point, according to whether have in destination channel described in preset order cycle detection piece choosing be in idle condition the step of include:
Storage unit into the flash array of current slice choosing connection sends inquiry instruction；
Judge that current slice choosing is in a busy state or idle state according to the feedback command of the storage unit.
9. a kind of parallel processing apparatus of solid state hard disk data, which is characterized in that the parallel processing of the solid state hard disk data fills
It sets and includes: memory, processor and be stored in the solid state hard disk data that can be run on the memory and on the processor
Concurrent processor, realize when the concurrent processor of the solid state hard disk data is executed by the processor such as claim
Described in any one of 1 to 8 the step of the method for parallel processing of solid state hard disk data.
10. a kind of computer readable storage medium, which is characterized in that it is hard to be stored with solid-state on the computer readable storage medium
It realizes when the concurrent processor of the concurrent processor of disk data, the solid state hard disk data is executed by processor as right is wanted
Described in asking any one of 1 to 8 the step of the method for parallel processing of solid state hard disk data.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110099325A1 (en) * | 2009-10-27 | 2011-04-28 | Samsung Electronics Co., Ltd. | User device and mapping data management method thereof |
| CN102567257A (en) * | 2011-12-26 | 2012-07-11 | 华中科技大学 | Method for controlling data reading and writing of multi-channel solid-state disc |
| CN102768645A (en) * | 2012-06-14 | 2012-11-07 | 国家超级计算深圳中心(深圳云计算中心) | Solid state disk (SSD) prefetching method for mixed caching and SSD |
| CN103777905A (en) * | 2014-02-14 | 2014-05-07 | 华中科技大学 | Software-defined fusion storage method for solid-state disc |
| CN104166634A (en) * | 2014-08-12 | 2014-11-26 | 华中科技大学 | Management method of mapping table caches in solid-state disk system |
| US20150074328A1 (en) * | 2012-05-04 | 2015-03-12 | Lsi Corporation | Dynamic map pre-fetching for improved sequential reads of a solid-state media |
| CN105892955A (en) * | 2016-04-29 | 2016-08-24 | 华为技术有限公司 | Method and equipment for managing storage system |
| CN106484334A (en) * | 2016-10-20 | 2017-03-08 | 郑州云海信息技术有限公司 | A kind of release pre-reads the method and device of resource |
| CN108122588A (en) * | 2016-11-30 | 2018-06-05 | 三星电子株式会社 | Non-volatile memory devices and the storage device for including it |
-
2018
- 2018-10-26 CN CN201811266831.8A patent/CN109491601B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110099325A1 (en) * | 2009-10-27 | 2011-04-28 | Samsung Electronics Co., Ltd. | User device and mapping data management method thereof |
| CN102567257A (en) * | 2011-12-26 | 2012-07-11 | 华中科技大学 | Method for controlling data reading and writing of multi-channel solid-state disc |
| US20150074328A1 (en) * | 2012-05-04 | 2015-03-12 | Lsi Corporation | Dynamic map pre-fetching for improved sequential reads of a solid-state media |
| CN102768645A (en) * | 2012-06-14 | 2012-11-07 | 国家超级计算深圳中心(深圳云计算中心) | Solid state disk (SSD) prefetching method for mixed caching and SSD |
| CN103777905A (en) * | 2014-02-14 | 2014-05-07 | 华中科技大学 | Software-defined fusion storage method for solid-state disc |
| CN104166634A (en) * | 2014-08-12 | 2014-11-26 | 华中科技大学 | Management method of mapping table caches in solid-state disk system |
| CN105892955A (en) * | 2016-04-29 | 2016-08-24 | 华为技术有限公司 | Method and equipment for managing storage system |
| CN106484334A (en) * | 2016-10-20 | 2017-03-08 | 郑州云海信息技术有限公司 | A kind of release pre-reads the method and device of resource |
| CN108122588A (en) * | 2016-11-30 | 2018-06-05 | 三星电子株式会社 | Non-volatile memory devices and the storage device for including it |
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