CN109462562B - Digital pre-distortion processing method applied to multi-mode RRU - Google Patents
Digital pre-distortion processing method applied to multi-mode RRU Download PDFInfo
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Abstract
The invention discloses a digital pre-distortion processing method applied to multi-mode RRU (remote radio unit). firstly, a DPD (digital pre-distortion) processing module calculates time delay according to captured forward downlink signals and feedback signals and aligns the forward downlink signals and the feedback signals; then, matrix modeling is carried out on the aligned forward downlink signals and feedback signals by using a memory polynomial model, and predistortion coefficients are calculated; and finally, applying the predistortion coefficient to the forward downlink signal, and outputting the predistorted downlink signal to the power amplifier, thereby improving the linearity of the power amplifier and the demodulation performance of the multimode signal. The invention has the beneficial effects that: compared with the prior art, the DPD processing module adopts a multi-mode digital pre-distortion algorithm, can process single-mode broadband signals, single-mode narrow-band signals and multi-mode broadband signals.
Description
Technical Field
The invention relates to the field of multi-mode RRU, in particular to a digital predistortion processing method applied to the multi-mode RRU.
Background
A radio Remote unit rru (radio Remote unit) is a novel distributed network coverage mode, which converts a baseband optical signal into a radio frequency signal at a Remote end for amplification and transmission. Under the condition that multi-mode signals coexist, the multi-mode RRU can simultaneously transmit wireless signals of multiple modes.
In a single-mode RRU, a DPD (Digital Pre-Distortion) technique is often used to perform predistortion processing on an output signal, so that the influence of signal Distortion is reduced while the signal transmission power is increased, and thus the operating efficiency of a power amplifier is increased while the transmission quality of the signal is ensured. In multi-mode RRU, DPD processing is also required for the multi-mode signals.
At present, the DPD algorithm is mainly used for the non-linear processing of single-mode signals, and even if the DPD processing of multi-mode signals is carried out, the multi-mode signals are separated into the single-mode signals for processing; in addition, in view of the wideband characteristics of DPD, DPD is more suitable for processing multicarrier signals, and the effect is not satisfactory when DPD processing is performed on narrowband signals such as GSM. However, when the multi-mode RRU operates, there is a case where only one narrowband signal is transmitted, for example, in the multi-mode RRU of GSM + LTE, there is a case where only a GSM signal is used, and in this case, the DPD is required to be capable of processing the nonlinear calibration of the narrowband signal. Therefore, the prior art does not have a real RRU of multi-mode digital predistortion algorithm.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a digital predistortion processing method applied to multi-mode RRU.
The object of the present invention is achieved by the following technical means. A digital predistortion processing method applied to multi-mode RRU, DPD processing module carry on the calculation of time delay according to forward downstream signal and feedback signal caught at first, carry on the alignment treatment to forward downstream signal and feedback signal; then, matrix modeling is carried out on the aligned forward downlink signals and feedback signals by using a memory polynomial model, and predistortion coefficients are calculated; and finally, applying the predistortion coefficient to the forward downlink signal, and outputting the predistorted downlink signal to the power amplifier, thereby improving the linearity of the power amplifier and the demodulation performance of the multimode signal.
Preferably, at the initial power-on stage, an initial default coefficient stored in the DPD processing module transmits an initial signal of the peak canceling module to the downlink DAC without any change, and the DAC converts a digital signal output by the DPD processing module into an analog signal and transmits the analog signal to the power amplifier for output; the feedback link collects the signal according to the output of the power amplifier, performs analog-to-digital conversion through the ADC and sends the signal to the DPD processing module.
Furthermore, the DPD processing module comprises a DPD data path module, a predistortion coefficient calculation module, a signal capturing RAM module, a time delay calculation module and a DPD control module; the method comprises the following specific steps:
(1) the signal capturing RAM module captures the output signal of the DPD data path module and the feedback signal output by the ADC into the signal capturing RAM module for storage according to the control signal given by the DPD control module;
(2) the time delay calculation module captures signal data in the RAM module according to the signal, calculates a correlation peak so as to calculate the time delay difference of the forward signal and the feedback signal, and records the time delay difference in a vector for judging whether the calculated time delay difference is stable and effective; if the peak value of the correlation peak or the time delay difference does not meet the requirement, the step (1) is carried out again;
(3) the predistortion coefficient calculation module captures signals of the RAM according to the time delay data and the signals provided by the time delay calculation module, aligns forward downlink signals and feedback signals, and then calculates the predistortion coefficient by using a least square method according to a memory polynomial model;
(4) and the DPD data path module applies the predistortion coefficient to the baseband multimode signal, transmits the digital signal to the DAC to be converted into an analog signal, and transmits the analog signal to the power amplifier to amplify the signal.
Preferably, the specific algorithm of the delay calculating module is as follows:
(1) calculating a complex correlation algorithm by using z (n) ═ x (n) × (y) (n), wherein x is a convolution symbol, x (n) and y (n) are complex sequences, x (n) sequences are collected forward downlink signals, y (n) collected feedback signals, and n represents the collected number;
(2) performing complex correlation algorithm calculation by moving the y (n) sequence, setting the moving window value to be A, namely stopping calculation when the y (n) sequence moves to the y (A);
(3) and recording the calculated A numbers in an array, and determining the position of a peak value by calculating the square of a modulus of a sequence z (n) and searching for a maximum value, wherein the position value is the delay difference.
Preferably, the pre-distortion coefficients are calculated as follows:
(1) aligning the collected forward downlink signals x (n) and feedback signals y (n);
(2) carrying out matrix modeling according to the following formula model;
q represents the memory depth of the simplified model, and K represents the order of nonlinearity;
the following matrix is established:
(3) correspondingly putting y (n) into the last column in the matrix A to obtain A':
(4) performing coefficient estimation by using a least square algorithm in the polynomial, and performing QR decomposition on the A' matrix to complete calculation of the least square method;
(5) after QR decomposition, i.e., a' ═ q × r, the predistortion coefficient a (k, q) can be obtained by performing iterative processing on r.
The invention has the beneficial effects that: compared with the prior art, the DPD processing module adopts a multi-mode digital pre-distortion algorithm, can process single-mode broadband signals, single-mode narrow-band signals and multi-mode broadband signals.
Drawings
Fig. 1 is a schematic diagram of an RRU structure employing multi-mode digital predistortion.
Fig. 2 is a diagram of the multi-mode DPD algorithm of the present invention.
Fig. 3 is a schematic diagram of a correlation algorithm of a delay calculation module.
Fig. 4 is a schematic diagram of a preferred model of the predistortion algorithm.
Detailed Description
The invention will be described in detail below with reference to the following drawings:
as shown in fig. 1, the multi-mode digital predistortion RRU includes a serial-to-parallel conversion interface, a CPRI decoding module, a digital up-conversion module, a peak-canceling module, a DPD processing module, a DAC (digital-to-analog conversion module), an ADC (analog-to-digital conversion module), a downlink of a power amplifier, and a feedback link.
The serial-parallel conversion interface is connected with an external photoelectric conversion module and can receive a CPRI protocol code stream transmitted from an optical fiber; the photoelectric conversion module realizes the interconversion of optical signals and electric signals, for downlink signals, signals with a certain wavelength transmitted from an optical fiber are converted into differential electric signals after passing through the optical module, and serial-parallel conversion interfaces convert serial signals represented by the differential electric signals into parallel digital signals and output the parallel digital signals to a subsequent CPRI decoding module.
The CPRI decoding module decodes the received CPRI protocol signal to obtain an IQ digital signal and a system control signal. Wherein, the IQ digital signal is a baseband multimode digital signal to be transmitted.
The digital up-conversion module performs up-conversion processing on the baseband multimode digital signal output by the CPRI decoding module, so that the code stream rate of the baseband multimode digital signal reaches the processing rate required by the peak eliminating module, and the processing rate of the peak eliminating module is consistent with the data code stream rate of the feedback link.
The peak eliminating module receives the baseband multimode digital signal output by the digital up-conversion module and carries out peak eliminating processing on the baseband multimode digital signal, so that the peak-to-average ratio of the baseband multimode digital signal is reduced, and the subsequent DPD processing and the improvement of the average output power of the power amplifier are facilitated.
The DPD processing module performs digital pre-distortion processing on the multi-mode signal; firstly, a DPD processing module calculates time delay according to a captured forward downlink signal and a captured feedback signal, and aligns the forward downlink signal and the feedback signal; then, matrix modeling is carried out on the aligned forward downlink signals and feedback signals by using a memory polynomial model, and predistortion coefficients are calculated; and finally, applying the predistortion coefficient to the forward downlink signal, and outputting the predistorted downlink signal to the power amplifier, thereby improving the linearity of the power amplifier and the demodulation performance of the multimode signal. The DAC converts the multi-mode digital signals into analog signals and transmits the analog signals to a power amplifier for amplification; and the ADC converts the analog signals received on the feedback link into digital signals and sends the digital signals to the DPD processing module.
The working principle of the RRU is specifically described below by taking GSM and LTE multimode signals within 1805M to 1830M bandwidth as an example.
The serial-parallel conversion interface converts the differential electric signal output by the external photoelectric conversion module into a parallel digital signal, recovers the clock of the previous stage of equipment according to the serial data code stream, and keeps the clock synchronization with the previous stage of equipment. The CPRI decoding module decodes 30.72M baseband IQ signals and system control signals from the parallel digital signals, and since the processing rate of the peak-canceling module is 122.88M, the digital up-conversion module is required to interpolate the 30.72M baseband IQ signals by 4 times to 122.88MHz, that is, the processing rate of the peak-canceling module. Because of the 4 times relation, the method of two half-band interpolation filters can be adopted, and the order of the filter can be reduced while the functions and indexes are met, so that the use of multiplier resources and the signal delay are reduced.
The peak eliminating module eliminates the peak of the baseband multimode signal which is interpolated to 122.88M, and the peak-to-average ratio is set to be 8. Theoretically, the smaller the peak-to-average ratio is, the larger the effective power is, but when the peak cancellation processing is performed on the signal, the EVM of the signal is deteriorated, and the demodulation of the signal is affected. In order to take account of the effective output power of the power amplifier and the EVM index, the peak-to-average ratio is set to 8 in the implementation process of the scheme.
At the initial power-on stage, an initial default coefficient stored in the DPD processing module transmits an initial signal of the peak eliminating module to a downlink DAC (digital-to-analog converter) without change, and a digital signal output by the DPD processing module is converted into an analog signal through the DAC and is transmitted to a power amplifier for output; the feedback link collects the signal according to the output of the power amplifier, performs analog-to-digital conversion through the ADC and sends the signal to the DPD processing module. And then the DPD processing module performs time delay calculation and alignment processing according to the cached forward digital signal and the feedback signal, performs matrix modeling through a memory polynomial model, calculates a predistortion coefficient by using a least square method, and performs digital predistortion processing on the baseband multimode signal according to the predistortion coefficient.
Fig. 2 is a preferred embodiment of the multi-mode DPD algorithm, where the DPD processing module includes the DPD data path module, the predistortion coefficient calculation module, the signal capturing RAM module, the delay calculation module, and the DPD control module; the method comprises the following specific steps:
(1) and the signal capturing RAM module captures the output signal of the DPD data path module and the feedback signal output by the ADC into the signal capturing RAM module for storage according to the control signal given by the DPD control module, and the signal capturing RAM module is used for subsequent work such as time delay calculation, data alignment, predistortion coefficient calculation and the like.
(2) The time delay calculation module captures signal data in the RAM module according to the signal, calculates a correlation peak through a correlation algorithm, thereby calculating the time delay difference of the forward signal and the feedback signal, and records the time delay difference in a vector for judging whether the calculated time delay difference is stable and effective; if the peak value of the correlation peak or the time delay difference does not meet the requirement, the step (1) is carried out again;
(3) the predistortion coefficient calculation module captures signals of the RAM according to the time delay data and the signals provided by the time delay calculation module, aligns forward downlink signals and feedback signals, and then calculates the predistortion coefficient by using a least square method according to a memory polynomial model;
(4) and the DPD data path module applies the predistortion coefficient to the baseband multimode signal, transmits the digital signal to the DAC to be converted into an analog signal, and transmits the analog signal to the power amplifier to amplify the signal.
Fig. 3 is a schematic diagram of a correlation algorithm of a delay calculation module, and the specific algorithm is as follows:
(1) calculating a complex correlation algorithm by using z (n) ═ x (n) × (y) (n), wherein x is a convolution symbol, x (n) and y (n) are complex sequences, x (n) sequences are collected forward downlink signals, y (n) collected feedback signals, and n represents the collected number;
(2) and performing complex correlation algorithm calculation by moving the y (n) sequence, wherein the time delay of the forward downlink signal and the feedback signal is not very large, and the difference between the x (n) sequence and the y (n) sequence is generally within 100. Therefore, a moving window value of a is set to 100, i.e., when the y (n) sequence moves to y (100), the calculation is terminated.
(3) And recording the calculated 100 numbers in an array, and determining the position of a peak value by calculating the square of a modulus of a z (n) sequence and searching for a maximum value, wherein the position value is the delay difference.
The following examples illustrate specific implementations.
(1) And the DPD control module sends out acquisition signals, and the signal capture RAM captures forward downlink signals x (n) and feedback y (n) which are 4096 signals respectively.
(2) The time delay calculation module firstly calculates
Here, x (n) real denotes the real part of x (n), i.e., the I signal; x (n) imag denotes the imaginary part of y (n), i.e. the Q signal, and the same.
Record z (1) in the z (n) array.
(3) And translating the pointer to the y (n) sequence to the position of y (2), namely, the y (n) sequence starts from y (2).
Record z (2) in the z (n) sequence.
(4) And repeating the step (3) until the pointer pointing to the y (n) sequence is translated to the position of y (100), namely the y (n) sequence starts from y (100).
Record z (100) in the z (n) sequence.
(5) Finally, calculating the square of the modulus of z (n)
|z(n)|2＝z(n).real2+z(n).imag2
(6) Finding | z (n) laces2The maximum value of (a) is the peak value of the correlation algorithm, and the subscript value corresponding to the value is the delay value. Such as | z (50) | ceiling2At maximum, 50 is the delay value, and an alignment operation is performed, i.e., x (1) is aligned with y (50), x (2) is aligned with y (51), and so on.
FIG. 4 is a preferred model of the predistortion algorithm, and the Volterra series can describe a nonlinear dynamical system more accurately. A Volterra series model is used here as the predistorter model. The complete model in its discrete form is described as:
q represents the memory depth of the model.
Because the complete model is complex, a simplified Volterra series model is adopted during implementation. The specific description is as follows:
wherein Q represents the memory depth of the simplified model, K represents the order of nonlinearity, and the complexity of the model is increased correspondingly with the increase of K and Q.
The algorithm calculation process is described in detail below:
(1) aligning the collected forward downlink signals x (n) and feedback signals y (n);
(2) carrying out matrix modeling according to the simplified model, and establishing the following matrix:
correspondingly putting y (n) into the last column in the matrix A to obtain A':
(3) in the polynomial, the coefficients are estimated by a number of methods, here using a least squares algorithm. To avoid the problem of least squares instability, the calculation of the least squares method is done by performing QR decomposition on the above a' matrix.
(4) After QR decomposition, i.e., a' ═ q × r, the coefficients a (k, q) can be obtained by performing iterative processing on r.
(5) And multiplying the data z (n) entering the predistortion function module by the following coefficient to obtain the data after the predistortion treatment, and further outputting the data to the power amplifier.
(6) And outputting the mixed-mode signal subjected to the pre-distortion treatment to a power amplifier, so that a signal subjected to nonlinear calibration can be obtained.
It should be understood that equivalent substitutions and changes to the technical solution and the inventive concept of the present invention should be made by those skilled in the art to the protection scope of the appended claims.
Claims (3)
1. A digital predistortion processing method applied to multi-mode RRU is characterized in that: the method comprises the following steps: firstly, a DPD processing module calculates time delay according to a captured forward downlink signal and a captured feedback signal, and aligns the forward downlink signal and the feedback signal; then, matrix modeling is carried out on the aligned forward downlink signals and feedback signals by using a memory polynomial model, and predistortion coefficients are calculated; finally, the predistortion coefficient is acted on the forward downlink signal, and the predistorted downlink signal is output to the power amplifier, so that the linearity of the power amplifier and the demodulation performance of the multimode signal are improved;
the DPD processing module comprises a DPD data path module, a predistortion coefficient calculation module, a signal capturing RAM module, a time delay calculation module and a DPD control module; the method comprises the following specific steps:
(1) the signal capturing RAM module captures the output signal of the DPD data path module and the feedback signal output by the ADC into the signal capturing RAM module for storage according to the control signal given by the DPD control module;
(2) the time delay calculation module captures signal data in the RAM module according to the signal, calculates a correlation peak so as to calculate the time delay difference of the forward signal and the feedback signal, and records the time delay difference in a vector for judging whether the calculated time delay difference is stable and effective; if the peak value of the correlation peak or the time delay difference does not meet the requirement, the step (1) is carried out again;
(3) the predistortion coefficient calculation module captures signals in the RAM module according to the time delay data and the signals provided by the time delay calculation module, aligns forward downlink signals and feedback signals, and then calculates the predistortion coefficient by using a least square method according to a memory polynomial model;
(4) the DPD data path module acts the predistortion coefficient on the baseband multimode signal, transmits the digital signal to the DAC to be converted into an analog signal, and transmits the analog signal to the power amplifier to amplify the signal;
the specific algorithm of the time delay calculation module is as follows:
(1) calculating a complex correlation algorithm by using z (n) ═ x (n) × (y) (n), wherein x is a convolution symbol, x (n) and y (n) are complex sequences, x (n) sequences are collected forward downlink signals, y (n) collected feedback signals, and n represents the collected number;
(2) performing complex correlation algorithm calculation by moving the y (n) sequence, setting the moving window value to be A, namely stopping the calculation when the y (n) sequence is moved to y (A), wherein the value of A is 100;
(3) and recording the calculated A numbers in an array, and determining the position of a peak value by calculating the square of a modulus of a sequence z (n) and searching for a maximum value, wherein the position value is the delay difference.
2. The digital predistortion processing method applied to multi-mode RRU of claim 1, wherein: at the initial power-on stage, an initial default coefficient stored in the DPD processing module transmits an initial signal of the peak eliminating module to a downlink DAC (digital-to-analog converter) without change, and a digital signal output by the DPD processing module is converted into an analog signal through the DAC and is transmitted to a power amplifier for output; the feedback link collects the signal according to the output of the power amplifier, performs analog-to-digital conversion through the ADC and sends the signal to the DPD processing module.
3. The digital predistortion processing method applied to multi-mode RRU of claim 1, wherein: the predistortion coefficient is calculated as follows:
(1) aligning the collected forward downlink signals x (n) and feedback signals y (n);
(2) carrying out matrix modeling according to the following formula model;
q represents the memory depth of the simplified model, and K represents the order of nonlinearity;
the following matrix is established:
(3) correspondingly putting y (n) into the last column in the matrix A to obtain A':
(4) performing coefficient estimation in the polynomial by using a least square algorithm, and performing QR decomposition on the A' matrix to complete calculation of the least square method;
(5) after QR decomposition, i.e., a ═ q × r, the predistortion coefficient a (k, q) can be obtained by performing iterative processing on r.
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| CN110572341B (en) * | 2019-09-19 | 2021-10-08 | 三维通信股份有限公司 | Digital predistortion technology DPD processing method and device |
| CN113709074A (en) * | 2020-05-21 | 2021-11-26 | 中兴通讯股份有限公司 | Baseband signal processing method, baseband processing unit and base station |
| CN112838995B (en) * | 2020-12-31 | 2023-02-03 | 北京新岸线移动多媒体技术有限公司 | Broadband digital predistortion method and digital predistorter |
| CN112953870A (en) * | 2021-01-28 | 2021-06-11 | 展讯半导体(南京)有限公司 | Digital pre-distortion processing method, device and system and computer equipment |
| CN113517865B (en) * | 2021-04-20 | 2022-11-22 | 重庆邮电大学 | Power amplifier model based on memory polynomial and hardware implementation method thereof |
| CN114900244B (en) * | 2022-05-13 | 2023-07-04 | 中国电子科技集团公司第三十研究所 | Signal distortion control system based on open loop digital predistortion |
| CN117714247B (en) * | 2024-02-05 | 2024-06-18 | 极芯通讯技术(安吉)有限公司 | Time delay alignment method and device |
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