CN109462441B - Multi-rate compatible non-standard DPSK receiving device based on 90-degree optical bridge - Google Patents

Multi-rate compatible non-standard DPSK receiving device based on 90-degree optical bridge Download PDF

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CN109462441B
CN109462441B CN201910034447.3A CN201910034447A CN109462441B CN 109462441 B CN109462441 B CN 109462441B CN 201910034447 A CN201910034447 A CN 201910034447A CN 109462441 B CN109462441 B CN 109462441B
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CN109462441A (en
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陈卫标
岳朝磊
孙建锋
侯霞
张晓曦
朱韧
刘磊
朱福南
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Shanghai Institute of Optics and Fine Mechanics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H04B10/612—Coherent receivers for optical signals modulated with a format different from binary or higher-order PSK [X-PSK], e.g. QAM, DPSK, FSK, MSK, ASK
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H04B10/616—Details of the electronic signal processing in coherent optical receivers

Abstract

A 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device, comprising: erbium-doped fiber amplifier (EDFA), 1: 1, an optical fiber beam splitter, an optical fiber phase shifter, an arm length matching optical fiber, a 90-degree optical bridge, a balance detector, a programmable limiting amplifier, a baseband receiving chip, a programmable logic gate array (FPGA), a digital-to-analog converter, an electronic mixer, an analog-to-digital converter and an optical fiber phase shifter driving amplification circuit. The invention has simple design, can realize the compatible reception of a plurality of communication rates and can ensure the optimal receiving performance of each communication rate. Multiple communication rates share optics and electronics, simplifying system design and significantly reducing system cost and system weight.

Description

Multi-rate compatible non-standard DPSK receiving device based on 90-degree optical bridge
Technical Field
The invention relates to free space coherent communication and optical fiber coherent communication, in particular to a multi-rate compatible non-standard DPSK (Differential Phase-Shift Keying) receiving device based on a 90-degree optical bridge.
Background
The laser coherent communication has the advantages of high sensitivity, large communication bandwidth, dense wavelength division multiplexing and the like, is a technical hotspot of optical fiber communication, and is gradually replacing laser intensity modulation communication on backbone networks. Meanwhile, satellite laser communication is also developing vigorously, and is a key implementation technology of the first generation of satellite communication. The laser coherent communication has the advantages of high communication speed, long communication distance, high security and the like, and is about to become a mainstream technology for realizing high-speed optical fiber communication and satellite laser communication. The demodulation method of coherent laser communication comprises the following steps: homodyne coherent demodulation, homodyne DPSK coherent demodulation and inner difference digital coherent demodulation. Compared with a homodyne coherent demodulation mode and an interpolation digital coherent demodulation mode, the homodyne DPSK demodulation mode has the advantages of lower implementation complexity and power consumption, lower requirement on communication wavelength and attractive communication mode. In a satellite optical communication scenario, it is desirable that one receiving end can simultaneously accommodate multiple communication rates. The traditional implementation mode mostly changes the modulation format or corresponds to one set of receiver for each rate, which results in the complexity of the receiver system and the proportional increase of the weight and the power consumption.
In the prior art [1] chinese patent CN200710143877.6, "DPSK optical modulation signal receiving apparatus and method" use a 180-degree bridge and a balanced receiver to demodulate DPSK signals, and the optimal point of error control is the maximum value of error signals, which is not favorable for improving control bandwidth. In the prior art [2] chinese patent 200910163008.9, "a device and method for locking demodulator phase in DPSK receiver," also adopts 180-degree bridge and temperature compensation method to implement phase control of demodulator, but the temperature control mode is slow in response and is not suitable for the scenario with fast phase change. In the prior art [3] european patent EP1164761a2 "DPSK system with variable data rates" selects a mode of sharing an optical path to realize multi-rate DPSK demodulation, an electronic part is a mode of a multiple-pass filter, and in the aspect of sharing an interference arm, an arm length difference is selected as an optical path corresponding to a highest communication rate bit period, and communication rates are downward compatible. In the prior art [4] CN106716873A 'lossless multi-rate optical transmission and reception' the effective communication rate is changed by changing the coding mode of an error correcting code, but the actual transmission and reception symbol rate is not changed, and the transmission code rate of a transmitting end is required to be fixed. In the prior art, the 'DPSK modulation-demodulation method' of CN101213775B and the optical communication equipment and the system using the method realize the compatibility of a plurality of rates by the time division multiplexing and wavelength division multiplexing methods, the communication rate can only be 2 times, 4 times, 8 times and 16 times of the lowest rate, and the structure is more complex.
A simple and reliable multi-rate compatible coherent communication demodulation device is researched, and the device has important significance for reducing the complexity of a communication system, reducing the power consumption and the load weight of the system and realizing the miniaturization of satellite laser communication loads.
Disclosure of Invention
The invention provides a multi-rate compatible non-standard DPSK receiving device based on a 90-degree optical bridge aiming at free space laser coherent communication and optical fiber coherent communication, which can be compatible with a plurality of communication rates and improve the receiving performance at each communication rate.
The technical solution of the invention is as follows:
a 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device, comprising: the device comprises an EDFA, an optical fiber beam splitter, an arm length matching optical fiber, an optical fiber phase shifter, a 90-degree optical bridge, an I-path balance detector, a Q-path balance detector, an electronic mixer, an analog-to-digital converter, an FPGA, a digital-to-analog converter, an optical fiber phase shifter driving circuit, a programmable limiting amplifier and a baseband signal receiving chip;
the output port of the EDFA is connected with the input port of the optical fiber beam splitter, the first output port of the optical fiber beam splitter is connected with the input port of the arm length matching optical fiber, the output port of the arm length matching optical fiber is connected with the first input port of the 90-degree optical bridge, the second output port of the optical fiber beam splitter is connected with the input port of the optical fiber phase shifter, the output port of the optical fiber phase shifter is connected with the second input port of the 90-degree optical bridge, the I-path output port of the 90-degree optical bridge is connected with the input port of the I-path balance detector, the Q-path output port of the bridge is connected with the input port of the Q-path balance detector, and the first output port of the I-path balance detector is connected with the first input port of the electronic mixer, the output port of the Q-path balance detector is connected with the second input port of the electronic mixer, the output port of the electronic mixer is connected with the input port of the analog-to-digital converter, the output pin of the analog-to-digital converter is connected with the first input pin of the FPGA, the first output pin of the FPGA is connected with the input pin of the digital-to-analog converter, the output port of the digital-to-analog converter is connected with the input port of the optical fiber phase shifter driving circuit, the output port of the optical fiber phase shifter driving circuit is connected with the driving input port of the optical fiber phase shifter, the second output port of the I-path balance detector is connected with the first input port of the programmable limiting amplifier, and the output port of the programmable limiting amplifier is connected with the input port of the baseband signal receiving chip, and the output pin of the baseband signal receiving chip is connected with the second input pin of the FPGA, and the second output pin of the FPGA is connected with the programming control pin of the programmable limiting amplifier.
The working principle and the signal output analysis of the invention are as follows:
the lowest communication code rate is set as: b isbThen the system communication rate can be compatible with Bb、2*Bb、3*Bb、4*Bb、5*BbAnd the like. The delay part requires that: the optical path of the time delay arm is smaller than that of the phase shift arm by Tb*C。Tb＝1/BbAnd C is the speed of light.
The electric field of the signal light entering the entrance of the receiving device may be expressed as:
Figure GDA0003156201040000041
PSfor received signal light power, w is the signal light angular frequency, m (t)0) Is t0The modulation code at the moment takes a value of 0 or 1,
Figure GDA0003156201040000042
is the signal light initial phase.
the electric field reaching the bridge portal 1 through the delay at time t can be expressed as:
Figure GDA0003156201040000043
the electric field reaching the bridge entrance 2 through the phase shifter at time t can be expressed as:
Figure GDA0003156201040000044
Figure GDA0003156201040000045
the phase difference of one arm of the delayer accumulated by time delay, signal light frequency change and optical fiber optical path change,
Figure GDA0003156201040000046
is the phase introduced by the fiber phase shifter when the control signal is added.
The 4 paths of output port optical electric field signals of the 90-degree bridge are as follows:
Figure GDA0003156201040000047
Figure GDA0003156201040000048
the corresponding current signals are:
Figure GDA0003156201040000049
Figure GDA00031562010400000410
Figure GDA0003156201040000051
Figure GDA0003156201040000052
Figure GDA0003156201040000053
Figure GDA0003156201040000054
Figure GDA0003156201040000055
Figure GDA0003156201040000056
Figure GDA0003156201040000057
for DPSK signals, m (T) is 0 or 1, then [ m (T + T)b)-m(t)]Pi is 0 or ± pi. The signal output by the multiplier can be rewritten as:
Figure GDA0003156201040000058
the feedback control program of the FPGA can ensure that:
Figure GDA0003156201040000059
at this time, the signal of the I path becomes:
Figure GDA00031562010400000510
or
Figure GDA00031562010400000511
Figure GDA00031562010400000512
Therefore, during the phase locking period, the I-path signal is equivalent to m (T) and m (T + T)b) Exclusive or exclusive or operation.
For communication rate of BbSignals m (T) and m (T + T)b) Are adjacent two bit signals.
Figure GDA00031562010400000513
For a communication rate of 2 × BbSignals m (T) and m (T + T)b) Are signals spaced 1 bit apart.
Figure GDA00031562010400000514
For a communication rate of 3 × BbSignals m (T) and m (T + T)b) Are 2 bit signals apart.
Figure GDA00031562010400000515
For a communication rate of 4 × BbSignals m (T) and m (T + T)b) Are 3 bit signals apart.
Figure GDA00031562010400000516
For the transmitting end, corresponding differential encoding needs to be performed,
communication rate of 1 × BbOf (2) a signal
Figure GDA0003156201040000061
Communication rate of 2 × BbOf (2) a signal
Figure GDA0003156201040000062
Communication rate of 3 xBbOf (2) a signal
Figure GDA0003156201040000063
Communication rate of 4 xBbOf (2) a signal
Figure GDA0003156201040000064
From the rule of the XOR operation, ck＝ak。
In conclusion: in phase locking
Figure GDA0003156201040000065
When c isk＝akThe amplitude-limited output signal is the communication code which needs to be transmitted by the transmitting end. In phase locking
Figure GDA0003156201040000066
When c isk＝～ak(-represents a binary negation operation). The phase lock is very stable and ensures that no 0, pi inversion occurs.
Tb 2Tb 3Tb 4Tb 5Tb 6Tb
b1 b2 b3 b4 b5 b6
… b1 b2 b3 b4 b5
… a1 a2 a3 a4 a5
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12
… … b1 b2 b3 b4 b5 b6 b7 b8 b9 b10
… … a1 a2 a3 a4 a5 a6 a7 a8 a9 a10
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18
… … … b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
… … … a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
When the speed is switched, the FPGA can control the input bandwidth of the amplitude limiting chip, the optimal receiving bandwidth corresponding to the speed is selected, and the optimal receiving performance under each speed is ensured.
Compared with the prior art, the invention has the advantages that:
1. the optical and electronic devices are shared at different communication rates, and the system is simple, low in power consumption, light in weight and small in size.
2. For different communication rates, the bandwidth of the limiting amplifier can be controlled through the FPGA, so that the optimal receiving performance of each communication rate can be ensured.
3. The mode that the FPGA is adopted to control the optical fiber phase shifter to realize phase control can be used for simultaneously monitoring the phase-locked state in real time, the phase-locked state can be automatically detected and locked again after being lost, and the reliability of phase locking is ensured.
4. The digital control algorithm and the coherent receiving signal are completed by the same FPGA chip, the circuit design is simple, the power consumption is low, and complex heat treatment analysis is not needed.
Drawings
Fig. 1 is a block diagram of a multi-rate compatible non-standard DPSK receiving device based on a 90-degree optical bridge according to the present invention.
Detailed Description
The present invention will be further described with reference to the following examples and drawings, but the scope of the present invention should not be limited thereto.
Fig. 1 is a block diagram of a multi-rate compatible non-standard DPSK receiving device based on a 90-degree optical bridge according to the present invention. As can be seen from the figure, the multi-rate compatible non-standard DPSK receiving apparatus based on a 90-degree optical bridge of the present invention includes: the device comprises an EDFA1, an optical fiber beam splitter 2, an arm length matching optical fiber 3, an optical fiber phase shifter 4, a 90-degree optical bridge 5, an I-path balance detector 6, a Q-path balance detector 7, an electronic mixer 8, an analog-to-digital converter 9, an FPGA10, a digital-to-analog converter 11, an optical fiber phase shifter driving circuit 12, a programmable limiting amplifier 13 and a baseband signal receiving chip 14;
an output port of the EDFA1 is connected to an input port of the optical fiber splitter 2, a first output port of the optical fiber splitter 2 is connected to an input port of the arm-length matching optical fiber 3, an output port of the arm-length matching optical fiber 3 is connected to a first input port of the 90-degree optical bridge 5, a second output port of the optical fiber splitter 2 is connected to an input port of the optical fiber phase shifter 4, an output port of the optical fiber phase shifter 4 is connected to a second input port of the 90-degree optical bridge 5, an I-path output port of the 90-degree optical bridge 5 is connected to an input port of the I-path balance detector 6, a Q-path output port of the bridge is connected to an input port of the Q-path balance detector 7, a first output port of the I-path balance detector 6 is connected to a first input port of the electronic mixer 8, an output port of the Q-path balance detector 7 is connected to a second input port of the electronic mixer 8, an output port of the electronic mixer 8 is connected to an input port of the analog-to-digital converter 9, an output pin of the analog-to-digital converter 9 is connected to a first input pin of the FPGA10, a first output pin of the FPGA10 is connected to an input pin of the digital-to-analog converter 11, an output port of the digital-to-analog converter 11 is connected to an input port of the optical fiber phase shifter driving circuit 12, an output port of the optical fiber phase shifter driving circuit 12 is connected to a driving input port of the optical fiber phase shifter 4, a second output port of the I-path balance detector 6 is connected to a first input port of the programmable limiting amplifier 13, and an output port of the programmable limiting amplifier 13 is connected to an input port of the baseband signal receiving chip 14, an output pin of the baseband signal receiving chip 14 is connected to a second input pin of the FPGA10, and a second output pin of the FPGA10 is connected to a programming control pin of the programmable limiting amplifier 13.

Claims (8)

1. A multi-rate compatible non-standard DPSK receiving device based on a 90-degree optical bridge is characterized by comprising the following components: the device comprises an EDFA (1), an optical fiber beam splitter (2), an arm length matching optical fiber (3), an optical fiber phase shifter (4), a 90-degree optical bridge (5), an I-path balance detector (6), a Q-path balance detector (7), an electronic mixer (8), an analog-to-digital converter (9), an FPGA (10), a digital-to-analog converter (11), an optical fiber phase shifter driving circuit (12), a programmable limiting amplifier (13) and a baseband signal receiving chip (14);
an output port of the EDFA (1) is connected with an input port of the optical fiber beam splitter (2), a first output port of the optical fiber beam splitter (2) is connected with an input port of the arm length matching optical fiber (3), an output port of the arm length matching optical fiber (3) is connected with a first input port of the 90-degree optical bridge (5), a second output port of the optical fiber beam splitter (2) is connected with an input port of the optical fiber phase shifter (4), an output port of the optical fiber phase shifter (4) is connected with a second input port of the 90-degree optical bridge (5), an I-path output port of the 90-degree optical bridge (5) is connected with an input port of the I-path balance detector (6), and a Q-path output port of the 90-degree optical bridge (5) is connected with an input port of the Q-path balance detector (7), a first output port of the I-path balance detector (6) is connected with a first input port of the electronic mixer (8), an output port of the Q-path balance detector (7) is connected with a second input port of the electronic mixer (8), an output port of the electronic mixer (8) is connected with an input port of the analog-to-digital converter (9), an output pin of the analog-to-digital converter (9) is connected with a first input pin of the FPGA (10), a first output pin of the FPGA (10) is connected with an input pin of the digital-to-analog converter (11), an output port of the digital-to-analog converter (11) is connected with an input port of the optical fiber phase shifter driving circuit (12), an output port of the optical fiber phase shifter driving circuit (12) is connected with a driving input port of the optical fiber phase shifter (4), the second output port of the I-path balance detector (6) is connected with the first input port of the programmable limiting amplifier (13), the output port of the programmable limiting amplifier (13) is connected with the input port of the baseband signal receiving chip (14), the output pin of the baseband signal receiving chip (14) is connected with the second input pin of the FPGA (10), and the second output pin of the FPGA (10) is connected with the programming control pin of the programmable limiting amplifier (13).
2. The 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device according to claim 1, wherein the arm length matching fiber (3) can be shared by a plurality of communication rates without gating.
3. The multi-rate compatible non-standard DPSK receiving device based on a 90-degree optical bridge according to claim 1, wherein the two path optical path difference between the arm length matching fiber (3) and the fiber phase shifter (4) is as follows: lowest communication rate BbThe single communication bit time multiplied by the speed of light.
4. The 90-degree-based optical bridge multi-rate compatible non-standard DPSK receiving device according to any one of claims 1 to 3, wherein when the communication rate is n times the lowest communication rate, the differential coding requirement of the corresponding transmitting end is as follows:
Figure FDA0003147925030000021
when k < ═ n, bk0, wherein akFor the k-th communication code to be transmitted, bkFor the k-th communication code after differential encoding, bk+nThe communication codes are k + n communication codes after differential coding, wherein n is a multiple of an actual communication rate and a lowest communication rate set by a system.
5. The 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device according to any one of claims 1-3, wherein the input bandwidth of the programmable limiting amplifier (13) is controlled by the FPGA (10) to ensure optimal reception at each communication rate.
6. The 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device according to any one of claims 1 to 3, wherein the piezoelectric fiber phase shifter (4) is controlled by the FPGA (10) to achieve phase locking.
7. A 90-degree optical bridge based multi-rate compatible non-standard DPSK receiver as claimed in any of claims 1-3, wherein the phase-lock error standard deviation is controlled within 4 degrees.
8. The 90-degree optical bridge based multi-rate compatible non-standard DPSK receiving device according to any one of claims 1-3, wherein a phase-locked error signal is obtained by mixing the 90-degree bridge and a quadrature IQ two-path signal, and the phase-locked error signal is proportional to the phase error.
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