CN109460210A - Ordering system and data processing method - Google Patents
Ordering system and data processing method Download PDFInfo
- Publication number
- CN109460210A CN109460210A CN201811231441.7A CN201811231441A CN109460210A CN 109460210 A CN109460210 A CN 109460210A CN 201811231441 A CN201811231441 A CN 201811231441A CN 109460210 A CN109460210 A CN 109460210A
- Authority
- CN
- China
- Prior art keywords
- data
- register
- processing unit
- comparator
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
- G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
Abstract
The embodiment of the present invention provides a kind of ordering system and data processing method, which is used for the K target data of the K before filtering out ranking in the input data that data volume is N, which includes sequentially connected K processing unit；Any one processing unit includes: register, for storing the target data of current location；Comparator, for comparing input data, the target data of register storage according to preset condition to obtain comparison result；No. three selectors, including selecting output end, three road input terminals, two selection ends, the three roads input terminal is respectively used to receive input data, the target data of current location, the target data of previous processing unit storage, this two selection ends be respectively used to receive the comparison result of comparator, in previous processing unit comparator comparison result, which is used for register export selected results.In use, K comparator is compared simultaneously, K register stores K target data respectively.
Description
Technical field
The present invention relates to data processing fields, in particular to a kind of ordering system and data processing method.
Background technique
With the rise of artificial intelligence, the technologies such as image recognition in real life using more and more extensive.In image
In the image processing tasks such as classification, recognition of face, needs to be ranked up final result, obtain TOP_K.
In practical applications, it generally requires to be ranked up to obtain TOP_K to mass data (N number of) (to be the big of N from data volume
In scale data, the element of K before ranking is found), and with the increase of K and N, algorithm complexity can increase therewith.At present
The optimal time complexity of TOP_K algorithm based on CPU (Central Processing Unit, central processing unit) is N*O
(log2(K)) a large amount of storage resources can, be occupied.
Summary of the invention
To overcome the technical problems existing in the prior art, the embodiment of the present invention is designed to provide a kind of ordering system
And data processing method.
In a first aspect, the embodiment of the present invention provides a kind of ordering system, for screening from the input data that data volume is N
Out before ranking K K target data, the system comprises sequentially connected K processing units；
Any one processing unit includes:
Register, for storing the target data of current location；
Comparator, for comparing the target data of input data, register storage according to preset condition, to be compared
Relatively result；
No. three selectors, including three road input terminals, two selection ends and a selection output end, three roads input terminal difference
For receiving the target data of the input data, the current location, the target data of previous processing unit storage, this two
A selection end is respectively used to receive the comparison knot of comparator described in the comparison result of the comparator, previous processing unit
Fruit, the selection output end are used for the register export selected results；
In use, the K comparators are compared simultaneously in the K processing unit, the K register difference
For storing the K target datas.
Second aspect, the embodiment of the present invention provide a kind of data processing method, for from the input data that data volume is N
Filter out the K target data of K before ranking, which comprises
When receiving trigger signal, using K comparator respectively to the K stored in present input data, K register
A data are compared, and obtain K comparison result；
The data in the K registers are updated parallel according to the K comparison result, obtain the K targets
Data.
Compared with prior art, the ordering system and data processing method of the embodiment of the present invention can be used in data volume being N
Large-scale data in filter out the data of K before ranking and can be carried out simultaneously by K processing unit in the ordering system
Data processing.Wherein, K register in K processing unit is respectively used to the target data of K before storage ranking, due to K ratio
It is existed simultaneously in K processing unit compared with device, and input data can be received simultaneously, therefore may be implemented defeated simultaneously for one
Enter data repeatedly to be compared, it is disposable to complete to update the data of multiple registers.It, can in entire data handling procedure
To realize the parallel processing of data, K register and K comparator need to be only occupied.At using above-mentioned ordering system and data
When reason method realizes TOP_K algorithm, it can be avoided in the prior art since the hardware configuration of CPU limits bring serial process disadvantage
End, can make space complexity N, and time complexity will not increase substantially, i.e., situation decline low in time complexity
Low spatial complexity.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, special embodiment below, and appended by cooperation
Attached drawing is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the schematic diagram of ordering system provided in an embodiment of the present invention.
Fig. 2 is the schematic diagram of wherein coagulation unit provided in an embodiment of the present invention.
Fig. 3 is the structural schematic diagram of No. three provided in an embodiment of the present invention selector.
Fig. 4 is the flow chart of data processing method provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
In the prior art, it is limited to the hardware configuration limitation (the especially quantity limitation of processor) of CPU, causes to be based on
The TOP_K algorithm that CPU is realized is serial process, often can only be complicated in view of the time at present for the optimization of TOP_K algorithm
It spends (sort algorithm is optimized), multiple operation is done using a CPU on hardware, although the dominant frequency of CPU is high, but
It is to be difficult to take into account using time complexity, the space complexity of the CPU algorithm realized.For example, for quick sorting algorithm,
Its algorithm complexity is unstable, and time complexity, space complexity are O (Nlog2N), even if accomplishing to be optimized to optimal cases,
Time complexity, space complexity still occupy height.And for other sort algorithms, such as bubble sort, selected and sorted, insertion
It sorts for scheduling algorithm, although can reduce space complexity, time complexity has but reached O (N2).Therefore, applicant
The solution of the present invention is proposed after study, to reduce space complexity under the premise of ensureing time complexity, so that the time
Complexity, space complexity are N, even if introducing pipelining to improve running frequency, time complexity is also 1*N, 2*N
Deng time complexity will not rise to (Nlog2N) even O (N2), the optimization to TOP_K algorithm is accomplished with this, reduces storage money
The occupancy in source.
It should be noted that heretofore described " upper one ", " next ", " previous ", " the latter " refer to patrol
Collect connection relationship.
First embodiment
Referring to Fig. 1, being the schematic diagram of ordering system provided in an embodiment of the present invention.The ordering system is used for from data volume
To filter out the K target data of K before ranking in the input data of N to get to TOP_K.The system comprises sequentially connected K
A processing unit, any one processing unit include register, comparator, No. three selectors (respectively correspond REG in Fig. 1,
COMP,MUX).Wherein, the COMP_DATA in Fig. 1 indicates input data, and [31:0] indicates the type of input data, and A is default
Value.It should be noted that K processing unit in the present invention can be understood as multiple processing units of same rank, it is each to handle
There are connection relationships between unit.
Structure about any one processing unit can further regard to Fig. 2, and REG, COMP, MUX in Fig. 2 are respectively indicated
Register, comparator, No. three selectors, COMP_DATA indicate input data, and " n " indicates that current location handles unit, " n-1 "
Indicate previous processing unit, " n+1 " indicates the latter processing unit.
Register in any one processing unit is used to store the target data of current location.K in K processing unit
Register (REG1, REG2 ... REGK) can be respectively used to K target data (top1, top 2 ... top K) of storage.Wherein,
The K target data can be the minimum data of K before ranking in the large-scale data that data volume is N, be also possible to K before ranking
Maximum data.
Wherein, the data stored in each register can be sent into No. three selectors of current location, can also be with
It send into the comparator of current location, can also send into the latter processing unit Zhong No. tri- selector.
In the present embodiment, comparator in any one processing unit is used to compare according to preset condition input data, described
The target data of register storage, to obtain comparison result.Wherein, there are two data sources for each comparator, i.e., currently
The data stored in the register of input data and current location, after being compared according to preset condition, obtained comparison knot
Fruit can be sent into No. three selectors of the latter processing unit, provide foundation with the data processing for the latter processing unit.
Wherein, the possibility situation of the preset condition has: the first, present input data is more than or equal to current location
Register in store data when, otherwise comparison result 1 is 0；Second, present input data is less than or equal to and works as
When the data stored in the register of front position, otherwise comparison result 1 is 0.In actual use, to meet not
The data of same type can realize using different comparators, and support to numerous types of data may be implemented and opened up with this
Exhibition.For example, the data that the input data in Fig. 1 is 32, then respective comparator should be the comparator that can compare 32 data.
In the present embodiment, any one processing unit Zhong No. tri- selector includes three road input terminals, two selection ends and one
A selection output end.The three roads input terminal is respectively used to receive the input data, target data of the current location, previous
The target data of a processing unit storage, this two selection ends are respectively used to receive the comparison result of the comparator, previous
The comparison result of comparator described in processing unit, the selection output end are used for the register export selected results.
Wherein, each No. three selector can act as the effect of data selection and transmitting, for example, when receiving triggering
When signal, No. three selectors can select the value at end according to two, select a circuit-switched data in three data of Cong Sanlu input terminal
It is stored in corresponding register, data selection is realized with this and updates.
By above structure, every level-one processing unit is all connect with adjacent processing unit, for example, three tunnels of current location
Selector is connect with the register in previous processing unit, is also connect with the comparator in previous processing unit, similarly, when
The register and comparator of front position are also connect with the latter processing unit Zhong No. tri- selector.
When in use, for above-mentioned K processing unit, K comparator can be compared simultaneously, K register difference
For storing the K target datas.When needing to obtain K final target data, it is only necessary to obtain and be stored in K register
Data.
The beneficial effect is that can disposably pass through multiple registers, multiple comparators realize screening, i.e., parallel place
Reason can be shown compared with the existing technology for the serial process means of middle CPU when handling the large-scale data that data volume is N
It writes and improves treatment effeciency, realize the optimization to TOP_K.
Especially when above-mentioned ordering system is configured to FPGA, (Field Programmable Gate Array, scene can
Program gate array) in when, the pipeline design based on FPGA, the TOP_K that can satisfy large-scale data is calculated, and the time is complicated
Degree is N, and storage resource occupancy is low, there is higher treatment effeciency.
Therefore, above-mentioned ordering system can be applied to FPGA, due to that can have thousands of register and processing in FPGA
Device can be realized building for above-mentioned ordering system.
If realizing the way of TOP_K using single cpu, algorithm complexity is difficult to stablize or can only stress the time
Complexity or space complexity can only be laid particular emphasis on, if the circuit or system built using other discrete devices, it is difficult to protect
Hinder device between coupling with it is synchronous, in order to realize the coupling between device, a large amount of communication resource must be occupied, if such as
Be using multiple CPU perhaps multiple processors can occupy building multiple processing units between CPU or between processor it is big
The coupling between the communication resource (communication resource includes storage resource) Lai Shixian device is measured, also will increase other costs.Therefore,
The TOP_K (above-mentioned ordering system is applied in FPGA) realized based on FPGA has more preferably application value.
On the other hand, when doing signal processing, image procossing, actual run time cannot only consider that the time is complicated
Degree, the actual run time of CPU are as follows: the clock cycle of the time complexity * CPU of CPU, the actual run time of FPGA are as follows:
The clock cycle of the time complexity * FPGA of FPGA, the actual run time ratio of the two are as follows:
(clock cycle of the time complexity * CPU of CPU)/(clock cycle of the time complexity * FPGA of FPGA).It will
Above-mentioned ordering system, which is configured in FPGA, can significantly improve this ratio, realize the optimization to TOP_K with this.
In the present embodiment, the register of any one processing unit is configured as storage extreme value.
In one embodiment, which can be the maximum that register can indicate, correspondingly, comparator is matched
It is set to, exports 1 when the input data is greater than or equal to the target data of current location, otherwise export 0.
In another embodiment, which can be the minimum that register can indicate, correspondingly, comparator quilt
It is configured to, exports 1 when the input data is less than or equal to the target data of current location, otherwise export 0.
Wherein, the selection of extreme value should according to actual needs depending on, if for example, needing to filter out the minimum of K before ranking
Data, extreme value can be maximum, if needing to filter out the maximum data of K before ranking, extreme value can be minimum.
It will obtain saying for the minimum data of K before ranking by from data volume for screening in the large-scale data of N below
It is bright.It should be noted that in other instances, what those skilled in the art can disclose according to design of the invention and the present invention
Technological means screening from the large-scale data that data volume is N obtains the maximum data of K before ranking.
In order to realize data screening purpose, any one processing unit Zhong No. tri- selector can be according to knot shown in Fig. 3
Structure is configured.
In Fig. 3, two selection ends of No. three selectors be respectively first choice end, second selection end, No. three selectors
Three road input terminals are respectively first input end, the second input terminal, third input terminal.
In any one processing unit:
The output end of the comparator at the second selection end and current location connects, and first choice end and previous processing are single
Comparator connection in member.Wherein, for first processing unit, the comparison result of corresponding previous processing unit is default
Value obtains before ranking for the minimum data of K for screening, which can be 0, that is, allows first processing unit corresponding
The comparison result perseverance of the comparator of previous processing unit is 0 (i.e. " A " in Fig. 1 can be 0).
In any one processing unit: the connection of the output end of first input end and the register of current location, the second input
End is connect with the register in previous processing unit, and third input terminal is for receiving present input data.Wherein, at first
In processing unit, the second input terminal of No. three selectors is for receiving input data.
The specific structure of above-mentioned ordering system can summarize are as follows: in a processing unit in office, the first of No. three selectors
The connection of the output end of input terminal and register；Second input terminal of No. three selector is for connecting previous processing unit；
The third road input terminal of No. three selectors is for obtaining input data；The first choice end of No. three selectors is previous for connecting
Processing unit；No. three selector second selection end connect with the comparator, the output end of No. three selector and
The input terminal of the register connects；Wherein, for the register for storing target data, which can be as current
The data source of Liang Ge No. tri- selector in position and the latter processing unit.
Illustrate the principle of 4 minimum data before acquiring ranking in N number of data with a complete example below.In system
Including 4 REG registers, 4 No. three selector MUX, 4 comparator COMP.
In 4 REG registers, REG1, REG2, REG3, REG4 are respectively used to store the smallest 4 data.
4 comparators are such configuration: present input data COMP_DATA, which is greater than or equal in REG register, to be stored
Data when, otherwise it is 0 that the output result of comparator, which is 1,.
The input data of whole system is COMP_DATA (having N number of), after N number of COMP_DATA data end of input, 4
The smallest 4 data, i.e. top1, top2, top3, top4 will be saved in REG register, be sequentially output available TOP_4, and
Time complexity is N, it is only necessary to occupy 4 registers and 4 comparators.
It is as follows to implement principle:
Firstly, being initialized to 4 REG registers, so that the data stored in 4 REG registers are register institute
The maximal number that can be indicated.Then as the trigger signal of clock cycle to receive input data COMP_DATA.
When receiving first input data COMP_DATA, first input data COMP_DATA can be simultaneously with 4
The data stored in a REG register are compared, and obtain 4 comparators exports the comparison knot as a result, i.e. comparator output
Fruit.
It will illustrate data updating process below with a kind of concrete mode.
When output result is respectively 0,0,0,0, indicate to store in than 4 REG registers of input data COMP_DATA
Data it is all small, at this time by the data stored in 4 registers a transmitting respectively backward, and by input data COMP_
DATA is stored in REG1, it may be assumed that
REG1=COMP_DATA, REG2=REG1, REG3=REG2, REG4=REG3.
When exporting result and being respectively 1,0,0,0, indicate that input data COMP_DATA ratio is wherein deposited in 3 registers
The data of storage are small, and it is constant to retain the data stored in REG1 at this time, and successively backward by the data stored in other 3 registers
One transmitting, and input data COMP_DATA is stored in REG2, it may be assumed that
REG1=REG1, REG2=COMP_DATA, REG3=REG2, REG4=REG3.
Similarly, when output result is respectively 1,1,0,0, the movement of execution is:
REG1=REG1, REG2=REG2, REG3=COMP_DATA, REG4=REG3.
And so on, when output result is respectively 1,1,1,1, the movement of execution is:
REG1=REG1, REG2=REG2, REG3=REG3, REG4=REG4.
In order to realize above-mentioned principle, Fig. 3 is referred to for the design of No. three selectors.The first choice end of No. three selectors
It is received be input data COMP_DATA and previous register REG_n-1 storage data between comparison result, second
Selecting end received is input data COMP_DATA compared between the data that the register REG_n of current location is stored
As a result.
When the comparison result at first choice end, the second selection end is respectively 0,0, the selection output end of No. three selectors
Export the data that REG_out is REG_n-1 storage.
When the comparison result at first choice end, the second selection end is respectively 1,0, the selection output end of No. three selectors
Output REG_out is present input data COMP_DATA.
When the comparison result at first choice end, the second selection end is respectively 1,1, the selection output end of No. three selectors
Export the data that REG_out is REG_n storage.
In this example, it is located at the first order (i.e. first tri- Lu Xuan of processing unit Zhong corresponding to No. three selectors of REG1
Select device), the comparison result that its first choice end is arranged is always 0, such as can make the fixed access low level in the first choice end,
The second input terminal of No. three selector is also set up when receiving trigger signal, receives present input data always.Due to 4
Register is set as maximum under initial situation, is theoretically not in the comparison result at first choice end, the second selection end
The case where respectively 0,1.
Certainly, above-mentioned update mode can also be using other update conditions, be with the maximum data for seeking before ranking 4
, initialization storage is minimum in register, it is entered data to when first interim, it is assumed that comparison condition is: when
When input data is less than or equal to target data, otherwise it is 0 that the comparison result of output, which is 1, then the update condition of data can be with
It is: when the comparison result of two adjacent processing units is 0,1, the target data stored in respective memory is carried out more
Newly, it is updated to the input data.
And according to comparison condition be: when input data be greater than or equal to target data when, the comparison result of output is
1, it is otherwise 0, then update condition may is that when the comparison result of two adjacent processing units is 10, to respective stored
The target data stored in device is updated, and is updated to the input data.
Under both update conditions, when comparison result 00,11 of two processing units, two kinds of update conditions corresponding two
Kind update mode can be opposite.
It should be noted that when receiving next input data, needing to complete to go through when next input data arrives
The update of history data, then with the data in updated register to be compared.If by the ordering system build in
This point may be implemented in FPGA, if because the system built using multiple CPU is in addition to needing to occupy the communication resource (communication money
Source includes storage resource) outside, due also to the dominant frequency of CPU obtained after adding assembly line, such as add 15 assembly lines,
So executing can just obtain after an instruction needs 15 clock cycle as a result, and realizing that TOP_K can be to avoid this based on FPGA
A little problems help operation to accelerate.
This example merely illustrates a kind of concrete condition of 4 minimum data before acquiring ranking in N number of data, certainly, this
The extreme value of register can be arranged in field technical staff according to actual needs, and the preset condition of respective comparator is assisted (to compare
Condition) and the selection regular (update condition) of No. three selectors can obtain result similar with this example.Therefore, extreme value is set
It sets, the setting of the selection rule of the preset condition of comparator, No. three selectors should not individually be interpreted as limitation of the present invention.
If desired the data for obtaining K before ranking, can expand to obtain with the TOP_K in examples detailed above, in actual use, if
Need support the input data of different types of data, it is only necessary to can realize to numerous types of data using different comparators
Support, such as the preset condition of comparator can be changed.
In conclusion the screening to the large-scale data that data volume is N may be implemented by above-mentioned ordering system, to obtain
The K target data of K before ranking.Above-mentioned ordering system can be based on FPGA to build, the TOP_K algorithm energy realized with this
Time complexity and space complexity are enough taken into account, compared with the TOP_K algorithm that CPU is realized, actual run time can be shortened, had
More preferably application value, significantly reduce resources occupation rate, expansibility with higher.
Second embodiment
Referring to Fig. 4, being the flow chart of data processing method provided in an embodiment of the present invention.This method is used for from data volume
For K target data for filtering out K before ranking in the input data of N.This method can be applied to described in first embodiment
Include sequentially connected K processing unit in the system in ordering system, includes register in every level-one processing unit, compares
Device, No. three selectors.The method includes the steps S101- step S102.Detailed process shown in Fig. 4 will be carried out below detailed
It illustrates.
Step S101, when receiving trigger signal, using K comparator respectively to present input data, K register
K data of middle storage are compared, and obtain K comparison result.
Wherein, which can be the rising edge or failing edge of clock cycle, in one embodiment, the touching
The clock that signalling can have internal system included generates trigger signal, can there is the oscillation of peripheral hardware in another embodiment
Device or trigger are to generate trigger signal.
When receiving trigger signal, input data can receive, further realize the input data and multiple deposits
The synchronous of multiple data in device is compared, and obtains multiple comparison results rapidly.
Step S102 updates the data in the K registers parallel according to the K comparison result, obtains K
The target data.
Wherein it is possible to the data in register are updated parallel according to principle described in first embodiment, with
The data finally stored into K register, these data are exactly the data of K before ranking needed for user.
By the above method, the data processing (parallel processing) of multiple comparators can be disposably carried out, in an example
In, the above method can be applied in FPGA, processing means (single-processor or single comparison compared to existing CPU
Device, serial process), operational efficiency can be significantly improved, after successively receiving N number of input data, so that it may complete all data
Comparison, without carrying out other classification to input data and being ranked up again, by upper after having received N number of input data
Method is stated, enables to that space complexity N can be made, and time complexity will not increase substantially, i.e., in time complexity
Space complexity is reduced in the case where low.
In the present embodiment, in order to further illustrate the preset condition of comparator, any comparator can be allowed to export
Comparison result is 1 or 0, and correspondingly, above-mentioned steps S102 includes: corresponding described to post the part comparator that comparison result is 0
Data in storage are moved step by step, to obtain K target data.About specifically move mode can refer to first step by step
The process of TOP_4 is obtained in embodiment, details are not described herein.It should be noted that can between K processing unit in the present invention
To be interpreted as the processing unit of same rank, " step by step " is intended merely to the convenient transmitting to illustrate data of description, is receiving one
When secondary trigger signal, the data that can disposably complete multiple registers update.
The data that can be realized in multiple registers in this way update, it is possible to reduce for the place of input data
Number is managed, that is, is not required to divide again between N number of input data, or swap between N number of input data.
In view of in the particularity being compared for the first time, therefore, when being compared for the first time, the K deposits can be allowed
K primary data, the extreme value that the primary data can indicate for the register are stored in device.
If needing to screen the minimum data of K before ranking, which can be maximum, and this is arranged to any comparator
The preset condition (comparison condition) of sample: for any comparator, when the present input data is greater than or equal to present bit
When the data stored in the register set, otherwise it is 0 that the comparison result of the comparator output, which is 1,.For such feelings
Condition, when the data stored in multiple registers are updated parallel, above-mentioned steps S102 includes: to judge that this K is relatively tied
Fruit whether all 0, if so, the primary data in K registers is moved step by step, and by the current input number
According in register described in the deposit first order.About specifically move mode can be with reference to obtaining TOP_4 in first embodiment step by step
Process, details are not described herein.
If needing to screen the maximum data of K before ranking, which can be minimum, and this is arranged to any comparator
The preset condition (comparison condition) of sample: for any comparator, when the present input data is less than or equal to present bit
When the data stored in the register set, otherwise it is 0 that the comparison result of the comparator output, which is 1,.For such feelings
Condition, when the data stored in multiple registers are updated parallel, above-mentioned steps S102 includes: to judge that this K is relatively tied
Fruit whether all 0, if so, the primary data in K registers is moved step by step, and by the current input number
According in register described in the deposit first order.
It is of course also possible to other update conditions are arranged, K comparison result it is all 1 when, by the K registers
In primary data moved step by step, and the present input data is stored in described in the first order in register.
In the present embodiment, above-mentioned steps S102 can be realized by such mode: by the comparison knot of current location
Fruit, previous processing unit comparison result respectively as No. three selectors two selection factors, and by the current input
Data, current location the register in data, the data in register described in previous processing unit respectively as
Three road input elements of No. three selector.For example, can by the output end of two neighboring comparator respectively with No. three selectors
Two selection ends connection, then by the output end of two neighboring register respectively with the two of them input terminal of No. three selectors connect
It connects, another input terminal of No. three selector is for receiving input data.
According still further to the first preset rules using in the input element of three road wherein all the way input element as three Lu Xuan
Select device output as a result, and by the output result deposit current location the register in, with realize data update.
Wherein, it is only necessary to the alternative condition of No. three selectors can be changed by changing the first preset rules, but belong to from
Present input data, the data of the register storage of current location, the data of register storage in previous processing unit this
In three, filters out a data and the data of the register of current location are updated.
In an example, the first preset rules that each No. three selector is met are as follows:
If the value of two selection factors is 00, the output result of No. three selector is to post described in previous processing unit
The data of storage storage, wherein the data in register described in the corresponding previous processing unit of first order No. three selector
For the present input data.
If the value of two selection factors is 10, the output result of No. three selector is the present input data.
If the value of two selection factors is 11, the output result of No. three selector is in the register of current location
Data.
Wherein, the value of two selection factors is determined by two comparators connecting with No. three selector.Corresponding to first
The fixed situation of the value of one of selection factor of grade No. three selectors, such as the first choice end of first order No. three selector
The case where being configured as the comparison result received is preset value 0, and the primary data of register is configured as maximum, reason
It the phenomenon that by the value for being above not in two selection factors being 01, but is not limited thereto.
Because first preset rules can also do such variation: if the value of two selection factors is 11, three Lu Xuan
The output result for selecting device is the data of the storage of register described in previous processing unit；If the value of two selection factors is 01,
The output result of No. three selector is the present input data；If the value of two selection factors is 00, No. three selector
Output result be current location the register in data.
But since those skilled in the art are when carrying out practical operation, it may be made to first order No. three selector
He is arranged, or other comparison conditions are arranged to comparator, and therefore, the first preset rules that No. three selectors are met may be used also
To there is other variations.
Can rationally derive other embodiments by above-mentioned data processing method, for example, can change register,
The quantity of comparator to obtain the target data of different number, can also change the extreme value of register, the comparison condition of comparator,
The first preset rules etc. that No. three selectors are met, but these changes should all be included in the protection scope of the present invention.
The other details of the data processing method described in the present embodiment, can be with further reference in first embodiment
Associated description, details are not described herein.
By above-mentioned data processing method realize TOP_K algorithm when, algorithm can be optimized, it is contemplated that hardware because
Element can make that space complexity N can be made, and time complexity will not increase substantially, i.e., feelings low in time complexity
Condition declines low spatial complexity.
3rd embodiment
The present embodiment provides a kind of fpga chip, configured with ordering system described in previous embodiment in the chip, lead to
Crossing the chip may be implemented TOP_K algorithm, can be with reference to the associated description in previous embodiment, herein about specific implementation principle
It repeats no more.
By above-mentioned ordering system, data processing method, fpga chip, multiple data can be disposably handled, i.e., parallel
Processing reduces space complexity under the premise of meeting time complexity, reduces the occupancy to temporary resource, is needing to handle
There is good application value in the fields such as image procossing, the identification of large-scale data.
Each functional module in each embodiment of the present invention can integrate one independent part of formation together, can also
To be modules individualism, an independent part can also be integrated to form with two or more modules.The function
If in the form of software function module realize and when sold or used as an independent product, can store in a computer
In read/write memory medium.Based on this understanding, technical solution of the present invention substantially makes tribute to the prior art in other words
The part offered or the part of the technical solution can be embodied in the form of software products, computer software product storage
In one storage medium, including some instructions are used so that computer equipment (can be personal computer, server,
Or network equipment etc.) perform all or part of the steps of the method described in the various embodiments of the present invention.And storage medium above-mentioned
It include: the various media that can store program code such as USB flash disk, mobile hard disk, memory.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of ordering system, which is characterized in that the K mesh for the K before filtering out ranking in the input data that data volume is N
Data are marked, the system comprises sequentially connected K processing units；
Any one processing unit includes:
Register, for storing the target data of current location；
Comparator, for comparing the target data of input data, register storage according to preset condition, to obtain comparing knot
Fruit；
No. three selectors, including three road input terminals, two selection ends and a selection output end, the three roads input terminal are respectively used to
Receive the input data, the target data of the current location, the target data of previous processing unit storage, this two choosings
End is selected to be respectively used to receive the comparison result of comparator described in the comparison result of the comparator, previous processing unit, it should
Output end is selected to be used for the register export selected results；
In use, the K comparators are compared simultaneously in the K processing unit, the K registers are respectively used to
Store the K target datas.
2. ordering system as described in claim 1, which is characterized in that be applied to FPGA；
The register of any one processing unit is configured as storage extreme value, the pole which can indicate for the register
Big value；
The comparator is configured as, and exports 1 when the input data is greater than or equal to the target data of current location,
Otherwise 0 is exported.
3. ordering system as described in claim 1, which is characterized in that be applied to FPGA；
The register of any one processing unit is configured as storage extreme value, the pole which can indicate for the register
Small value；
The comparator is configured as, and exports 1 when the input data is less than or equal to the target data of current location,
Otherwise 0 is exported.
4. ordering system as claimed in claim 2 or claim 3, which is characterized in that distinguish at two selection ends of No. three selector
For first choice end, the second selection end, three road input terminals of No. three selector are respectively first input end, the second input
End, third input terminal；
In any one processing unit:
The output end of the comparator at the second selection end and current location connects, the first choice end and previous place
Manage the comparator connection in unit；
The connection of the output end of the first input end and the register of current location, second input terminal and previous place
The register connection in unit is managed, the third input terminal is for receiving the input data；
Wherein, for first processing unit, the comparison result of corresponding previous processing unit is preset value, and described second is defeated
Enter end for receiving input data.
5. a kind of data processing method, which is characterized in that the K for the K before filtering out ranking in the input data that data volume is N
A target data, which comprises
When receiving trigger signal, using K comparator respectively to the K number stored in present input data, K register
According to being compared, K comparison result is obtained；
The data in the K registers are updated parallel according to the K comparison result, obtain the K target datas.
6. data processing method as claimed in claim 5, which is characterized in that the comparison result of any comparator output is
1 or 0, it is described that the data in the K registers are updated parallel according to the K comparison result, obtain the K targets
Data, comprising:
The data in the corresponding register of part comparator for being 0 by comparison result are moved step by step, to obtain K mesh
Mark data.
7. data processing method as claimed in claim 6, which is characterized in that it is applied to FPGA, when being compared for the first time, K
K primary data of storage in a register, the maximum that the primary data can indicate for the register, described
The step of data in the K registers are updated parallel, obtain the K target datas according to the K comparison result,
Include:
The K comparison result whether all 0 is judged, if so, the primary data in the K registers is moved step by step
It is dynamic, and the present input data is stored in register described in the first order；Wherein, for any comparator, when described
When present input data is greater than or equal to the data stored in the register of current location, the comparison of the comparator output
As a result it is 1, is otherwise 0.
8. data processing method as claimed in claim 6, which is characterized in that it is applied to FPGA, when being compared for the first time, K
K primary data of storage in a register, the minimum that the primary data can indicate for the register, described
The step of data in the K registers are updated parallel, obtain the K target datas according to the K comparison result,
Include:
The K comparison result whether all 0 is judged, if so, the primary data in the K registers is moved step by step
It is dynamic, and the present input data is stored in register described in the first order；Wherein, for any comparator, when described
When present input data is less than or equal to the data stored in the register of current location, the comparison of the comparator output
As a result it is 1, is otherwise 0.
9. such as the described in any item data processing methods of claim 5-8, which is characterized in that described according to the K comparison result
Data in the K registers are updated parallel, obtain the K target datas, comprising:
Using the comparison result of current location, previous processing unit comparison result as two of No. three selectors selections
Factor, and by the present input data, current location the register in data, post described in previous processing unit
The three road input elements of data in storage respectively as No. three selector；
According to the first preset rules using in the input element of three road wherein all the way input element as No. three selector
Output as a result, and by the output result deposit current location the register in, with realize data update.
10. data processing method as claimed in claim 9, which is characterized in that each No. three selector is met described
First preset rules include:
If the value of two selection factors is 00, the output result of No. three selector is register described in previous processing unit
The data of storage, wherein the data in register described in the corresponding previous processing unit of first order No. three selector are institute
State present input data；
If the value of two selection factors is 10, the output result of No. three selector is the present input data；
If the value of two selection factors is 11, the output result of No. three selector is the number in the register of current location
According to；
Alternatively, first preset rules include:
If the value of two selection factors is 11, the output result of No. three selector is register described in previous processing unit
The data of storage；
If the value of two selection factors is 01, the output result of No. three selector is the present input data；
If the value of two selection factors is 00, the output result of No. three selector is the number in the register of current location
According to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811231441.7A CN109460210B (en) | 2018-10-22 | 2018-10-22 | Sorting system and data processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811231441.7A CN109460210B (en) | 2018-10-22 | 2018-10-22 | Sorting system and data processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109460210A true CN109460210A (en) | 2019-03-12 |
| CN109460210B CN109460210B (en) | 2020-11-03 |
Family
ID=65608061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811231441.7A Active CN109460210B (en) | 2018-10-22 | 2018-10-22 | Sorting system and data processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109460210B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825343A (en) * | 2019-11-05 | 2020-02-21 | 中电科仪器仪表有限公司 | Rapid data screening method and system |
| CN117687957A (en) * | 2024-02-04 | 2024-03-12 | 中国人民解放军海军航空大学 | Top-k information processing engine based on FPGA and ordering method thereof |
| CN117687957B (en) * | 2024-02-04 | 2024-04-23 | 中国人民解放军海军航空大学 | Top-k information processing engine based on FPGA and ordering method thereof |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57137939A (en) * | 1981-02-18 | 1982-08-25 | Univ Kyoto | Parallel counting and sorting method and its circuit |
| DE68926131D1 (en) * | 1988-05-26 | 1996-05-09 | Mitsubishi Electric Corp | Control data generator for sort processor |
| US7124268B2 (en) * | 2002-10-31 | 2006-10-17 | Mosaid Technologies, Inc. | Sorting method and apparatus using a CAM |
| CN1987771A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Hardware circuit for realizing data sequencing and method |
| CN101114215A (en) * | 2006-07-28 | 2008-01-30 | 中兴通讯股份有限公司 | Circuit for realizing data ordering and method thereof |
| WO2008054963A2 (en) * | 2006-10-31 | 2008-05-08 | Motorola, Inc. | Hardware sorter |
| CN101192847A (en) * | 2007-08-13 | 2008-06-04 | 中兴通讯股份有限公司 | A peak search and sorting device and peak sorting method |
| CN101261576A (en) * | 2008-04-03 | 2008-09-10 | 启攀微电子（上海）有限公司 | Hardware circuit for accomplishing paralleling data ordering and method |
| CN101470553A (en) * | 2007-12-27 | 2009-07-01 | 比亚迪股份有限公司 | Data preprocessing ranking circuit and method of touch screen controller |
| CN104317549A (en) * | 2014-10-15 | 2015-01-28 | 中国航天科技集团公司第九研究院第七七一研究所 | Cascade structure circuit and method for realizing data sorting |
| CN103019646B (en) * | 2013-01-09 | 2015-09-30 | 西安电子科技大学 | Sorting in parallel circuit and sorting in parallel method |
| CN105512179A (en) * | 2015-11-25 | 2016-04-20 | 中国科学院计算技术研究所 | Data sorting device, method and data processing chip achieved by hardware |
| CN106294414A (en) * | 2015-05-25 | 2017-01-04 | 腾讯科技（深圳）有限公司 | Data reordering method and device |
-
2018
- 2018-10-22 CN CN201811231441.7A patent/CN109460210B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57137939A (en) * | 1981-02-18 | 1982-08-25 | Univ Kyoto | Parallel counting and sorting method and its circuit |
| DE68926131D1 (en) * | 1988-05-26 | 1996-05-09 | Mitsubishi Electric Corp | Control data generator for sort processor |
| US7124268B2 (en) * | 2002-10-31 | 2006-10-17 | Mosaid Technologies, Inc. | Sorting method and apparatus using a CAM |
| CN1987771A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Hardware circuit for realizing data sequencing and method |
| CN101114215A (en) * | 2006-07-28 | 2008-01-30 | 中兴通讯股份有限公司 | Circuit for realizing data ordering and method thereof |
| WO2008054963A2 (en) * | 2006-10-31 | 2008-05-08 | Motorola, Inc. | Hardware sorter |
| CN101192847A (en) * | 2007-08-13 | 2008-06-04 | 中兴通讯股份有限公司 | A peak search and sorting device and peak sorting method |
| CN101470553A (en) * | 2007-12-27 | 2009-07-01 | 比亚迪股份有限公司 | Data preprocessing ranking circuit and method of touch screen controller |
| CN101261576A (en) * | 2008-04-03 | 2008-09-10 | 启攀微电子（上海）有限公司 | Hardware circuit for accomplishing paralleling data ordering and method |
| CN103019646B (en) * | 2013-01-09 | 2015-09-30 | 西安电子科技大学 | Sorting in parallel circuit and sorting in parallel method |
| CN104317549A (en) * | 2014-10-15 | 2015-01-28 | 中国航天科技集团公司第九研究院第七七一研究所 | Cascade structure circuit and method for realizing data sorting |
| CN106294414A (en) * | 2015-05-25 | 2017-01-04 | 腾讯科技（深圳）有限公司 | Data reordering method and device |
| CN105512179A (en) * | 2015-11-25 | 2016-04-20 | 中国科学院计算技术研究所 | Data sorting device, method and data processing chip achieved by hardware |
Non-Patent Citations (3)
| Title |
|---|
| YASUURA H 等: "The parallel enumeration sorting scheme for VLSI", 《IEEE TRANS ON COMPUTERS》 * |
| 胡二猛 等: "基于FPGA的硬件排序系统设计", 《微电子技术》 * |
| 魏凤歧 等: "一种BCA结构形式的硬件排序电路模型", 《内蒙古大学学报（自然科学版）》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825343A (en) * | 2019-11-05 | 2020-02-21 | 中电科仪器仪表有限公司 | Rapid data screening method and system |
| CN110825343B (en) * | 2019-11-05 | 2021-12-03 | 中电科思仪科技股份有限公司 | Rapid data screening method and system |
| CN117687957A (en) * | 2024-02-04 | 2024-03-12 | 中国人民解放军海军航空大学 | Top-k information processing engine based on FPGA and ordering method thereof |
| CN117687957B (en) * | 2024-02-04 | 2024-04-23 | 中国人民解放军海军航空大学 | Top-k information processing engine based on FPGA and ordering method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109460210B (en) | 2020-11-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Meng et al. | A hybrid artificial bee colony algorithm for a flexible job shop scheduling problem with overlapping in operations | |
| Zhou | Network landscape from a Brownian particle’s perspective | |
| US5852740A (en) | Polymorphic network methods and apparatus | |
| Fatih Tasgetiren et al. | Particle swarm optimization and differential evolution for the single machine total weighted tardiness problem | |
| EP3037991A1 (en) | Systems and user interfaces for dynamic and interactive investigation of bad actor behavior based on automatic clustering of related data in various data structures | |
| Dou et al. | Optimisation for multi-part flow-line configuration of reconfigurable manufacturing system using GA | |
| Safro et al. | Multilevel algorithms for linear ordering problems | |
| CN108764319A (en) | A kind of sample classification method and apparatus | |
| CN109978261A (en) | Determine method, apparatus, readable medium and the electronic equipment of load forecasting model | |
| CN109582452A (en) | A kind of container dispatching method, dispatching device and electronic equipment | |
| CN110334159A (en) | Information query method and device based on relation map | |
| CN109241392A (en) | Recognition methods, device, system and the storage medium of target word | |
| US6549931B1 (en) | Distributing workload between resources used to access data | |
| CN110442480A (en) | A kind of mirror image data method for cleaning, apparatus and system | |
| CN109409746A (en) | A kind of production scheduling method and device | |
| CN109460210A (en) | Ordering system and data processing method | |
| CN108537291A (en) | A kind of sample classification method and apparatus | |
| CN111813517A (en) | Task queue allocation method and device, computer equipment and medium | |
| CN109359760B (en) | Logistics path optimization method and device and server | |
| CN106503271A (en) | The intelligent shop site selection system of subspace Skyline inquiry under mobile Internet and cloud computing environment | |
| CN113657812A (en) | Method and system for intelligent decision-making of store operation based on big data and algorithm | |
| Xiao et al. | ORHRC: Optimized recommendations of heterogeneous resource configurations in cloud-fog orchestrated computing environments | |
| CN110096501A (en) | Data search method, device, medium and electronic equipment based on label | |
| CN115630514B (en) | Unmanned aerial vehicle cluster collaborative task distribution method and device | |
| CN109885651A (en) | A kind of question pushing method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 401122 5 stories, Block 106, West Jinkai Avenue, Yubei District, Chongqing Applicant after: Chongqing Zhongke Yuncong Technology Co., Ltd. Address before: 400 000 5 stories of Block 106, West Jinkai Avenue, Yubei District, Chongqing Applicant before: CHONGQING ZHONGKE YUNCONG TECHNOLOGY CO., LTD. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |