CN109450608A - A kind of synchronous method of improved sign synchronization loop - Google Patents
A kind of synchronous method of improved sign synchronization loop Download PDFInfo
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- CN109450608A CN109450608A CN201811365510.3A CN201811365510A CN109450608A CN 109450608 A CN109450608 A CN 109450608A CN 201811365510 A CN201811365510 A CN 201811365510A CN 109450608 A CN109450608 A CN 109450608A
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- data
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- phase
- sign synchronization
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
Abstract
The invention discloses a kind of synchronous method of improved sign synchronization loop, the components such as low-pass filter and the DDS in traditional lead-lag sign synchronization method are replaced with frequency counter, more brief and practical, by the counting period for constantly adjusting frequency counter, symbol sampler moment clock is in the center of input signal, i.e. eye figure opened near the maximum moment.
Description
Technical field
The present invention relates to a kind of synchronous method of improved sign synchronization loop.
Background technique
In digital communication systems, receiving end needs to export demodulation to recover data-signal from reception signal
Signal is periodically sampled with character rate, is accurately sampled, is adjudicated, thus receiving end must have one with
The digital baseband signal symbol rate synchronous clock signal received, to obtain accurate sampling instant.Therefore, sign synchronization is just
The basis of true sampled data.Extracted symbol synchronization information is the commutator pulse that frequency is equal to bit rate, phase then basis
The waveform of signal determines when judgement.
Receiver will not only make the clock restored consistent with the clock frequency of the digital signal received, but also be also predefined
It is sampled at maximum signal to noise ratio in each mark space, this is related with the phase of recovered clock, the institute in mark space
The sampling of choosing is instantaneously known as timing phase.In practical engineering applications, since there are clock drifts between send-receive clock, for this purpose,
Receiving end, which recovers clock, must adjust in real time its clock frequency and timing phase to compensate frequency drift, to ensure to demodulation
Output signal samples instantaneous maximization.
There are many method for realizing sign synchronization, and most common method has insertion pilot tone system and direct method.Being inserted into pilot tone system needs
Valuable band resource is occupied, is generally of little use.Direct method is the extraction bit synchronization information from digital signal streams, is divided into filtering
Method, phase locking technique and lead-lag type Synchronos method, wherein what is be most widely used is lead-lag type Synchronos method.
Referring to Fig. 1, traditional lead-lag type Synchronos method is accorded with using the characteristics of signal pulse waveform symmetry
Number synchronous.The I (advanced) or the signal after the demodulation of Q (lag) branch that y (t) indicates demodulation output, it is assumed that opened most on the way
It is sampled, i.e., is sampled in the best time when big, obtained sampled value is y (τ0+nTS), τ0It is best timing phase.If
Δ is the deviation value of off-target sampling time, deviation value be △ two sampling times sample value be it is equal, one
To sample in advance, with y (τ0+nTSΔ) it indicates；Another is lag sampling, with y (τ0+nTS+ Δ) it indicates, then the two is absolute
It is worth approximately equal, synchronization can be realized；When not synchronous, sampling phase τ ≠ τ0, respectively by the two full-wave rectification, and subtract each other, obtain
It arrives
y2(t)=| y (τ0+nTS-Δ)|-|y(τ0+nTS-Δ)|(1)
Again by y2(t) pass through low-pass filtering, be equivalent to y2(t) y is averagely obtained3(t), then by y3(t) DDS is given
(Direct Digital Synthesizer, Direct Digital Synthesizer), controls the frequency of DDS.If DDS generate when
Clock is best timing phase, then filtering output is 0；If advanced, negative value is exported；If lag, exports positive value, constantly adjusted with this
Save the frequency of DDS.y4It (t) is the real-time sampling clock exported.
Need to use the components such as low-pass filter, DDS in traditional lead-lag sign synchronization method.For Practical Project
Design, the data for demodulating output are apparently not continuous analog signal, and selectable sampled point is by counting in a symbol period
It is determined according to sample frequency.By the parameter of QPSK demodulation model it is found that I, Q roadbed band signal rate after demodulation are 6MHz, sampling
Rate is 48MHz, and the sample rate after demodulation is 8 times of data rate, that is to say, that selectable within a baseband signal period
Sampled point only has 8.Therefore DDS generation is that the frequency clock signal of continuous variable obviously has little significance in Fig. 1.Therefore, exist
It in the theoretical basis of lead-lag sign synchronization method, makes improvements, it is real to design a kind of more succinct sign synchronization ring
Existing structure.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies of existing technologies, a kind of side of synchronization of improved sign synchronization loop is provided
Method, more brief and practical, by constantly adjusting the counting period of frequency counter, symbol sampler moment clock is in input letter
Number center, i.e. eye figure opens near the maximum moment.
Realizing the technical solution of above-mentioned purpose is: a kind of synchronous method of improved sign synchronization loop, described improved
In sign synchronization loop use frequency counter, the synchronous method the following steps are included:
S1 before sampling first takes absolute value to output data, realizes full-wave rectification；
S2, when sign synchronization, the data of advanced branch and lag branch sampling are equal, and the frequency division counter is arranged at this time
The counting period of device is 8, and the driving clock of the frequency counter is data sampling clock 48MHz, after frequency dividing the clock cycle be
6MHz；
S3 indicates sampled value in the decline phase of eye figure peak value, sampling when advanced branch data is greater than lag branch data
Clock phase lags behind data clock phase, then one clock cycle of counting cycle time that the frequency counter is arranged is 7,
Next sampling instant is set to mention previous sampling clock cycle；
S4 indicated upper drop phase of the sampled value in eye figure peak value, sampling clock when advanced branch data is less than lag data
Phase is ahead of data clock phase, then one clock cycle of counting period increase that the frequency counter is arranged is 9, under making
One sampling instant mentions previous sampling clock cycle；
S5, step S2, S3 and S4 circulation repeatedly, when loop-locking, the symbol sampler moment be in always eye figure open it is maximum
Near moment.
The synchronous method of improved sign synchronization loop of the invention, traditional lead-lag is replaced with frequency counter
The components such as low-pass filter and DDS in sign synchronization method, more brief and practical, by the meter for constantly adjusting frequency counter
One number time, symbol sampler moment clock are in the center of input signal, i.e. eye figure opened near the maximum moment.
Detailed description of the invention
Fig. 1 is the schematic diagram of traditional lead-lag type Synchronos method；
Fig. 2 is the schematic diagram of the synchronous method of improved sign synchronization loop of the invention；
Fig. 3 is the time stimulatiom figure of the synchronous method of improved sign synchronization loop of the invention.
Specific embodiment
It is right with reference to the accompanying drawing in order to make those skilled in the art be better understood when technical solution of the present invention
Its specific embodiment is described in detail:
Referring to Fig. 2, highly preferred embodiment of the present invention, a kind of synchronous method of improved sign synchronization loop is improved
In sign synchronization loop use frequency counter, the synchronous method the following steps are included:
S1 before sampling first takes absolute value to output data, realizes full-wave rectification；
S2, when sign synchronization, the data of advanced branch and lag branch sampling are equal, and frequency counter is arranged at this time
Counting the period is 8, and the driving clock of frequency counter is data sampling clock 48MHz, and the clock cycle is 6MHz after frequency dividing；
S3 indicates sampled value in the decline phase of eye figure peak value, sampling when advanced branch data is greater than lag branch data
Clock phase lags behind data clock phase, then one clock cycle of counting cycle time that frequency counter is arranged is 7, under making
One sampling instant mentions previous sampling clock cycle；
S4 indicated upper drop phase of the sampled value in eye figure peak value, sampling clock when advanced branch data is less than lag data
Phase is ahead of data clock phase, then one clock cycle of counting period increase that frequency counter is arranged is 9, makes next
Sampling instant mentions previous sampling clock cycle；
S5, step S2, S3 and S4 circulation repeatedly, when loop-locking, the symbol sampler moment be in always eye figure open it is maximum
Near moment.
The basic thought of the synchronous method of improved sign synchronization loop of the invention is still according to data after demodulating waveform
Symmetry, sample lead-lag structure to adjust the phase of sign synchronization clock.The difference is that replacing passing with frequency counter
The components such as low-pass filter and DDS in the lead-lag sign synchronization method of system, y (t) indicate demodulation output advanced branch or
Signal after lagging branch demodulation, it is assumed that sampled when opening maximum on the way, i.e., sampled, obtained in the best time
Sampled value is y (τ0+nTS), τ0It is best timing phase.It is △ in deviation value if Δ is the deviation value of off-target sampling time
The sampling of two sampling times value be it is equal, one is advanced sampling, with y (τ0+nTSΔ) it indicates；Another is lag
Sampling, with y (τ0+nTS+ Δ) it indicates, then the absolute value of the two is approximately equal, and synchronization can be realized；When not synchronous, phase is sampled
Position τ ≠ τ0, respectively by the two full-wave rectification, and subtract each other, obtain
y2(t)=| y (τ0+nTS-Δ)|-|y(τ0+nTS-Δ)|
Again by y2(t) it is sent to frequency counter, controls the counting period of frequency counter, when the real-time sampling of output
Clock.
Figure Fig. 3 is please referred to, from the simulation waveform using the synchronous method of improved sign synchronization loop of the invention
It can be seen that the rising edge of original state sampling clock clkout is aligned with the hopping edge of symbol pcm symbol, it need to be same by symbol
Ring is walked by the midpoint of the rising edge alignment pcm of clkout, by constantly adjusting the counting period of counter, symbol sampler moment
Clock clkout is in the center of input signal pcm, i.e. eye figure opened near the maximum moment.
In conclusion the synchronous method of improved sign synchronization loop of the invention, is replaced traditional with frequency counter
The components, more brief and practical such as low-pass filter and DDS in lead-lag sign synchronization method, by constantly adjusting frequency dividing
The counting period of counter, symbol sampler moment clock are in the center of input signal, i.e. eye figure opened near the maximum moment.
Those of ordinary skill in the art it should be appreciated that more than embodiment be intended merely to illustrate the present invention,
And be not used as limitation of the invention, as long as the change in spirit of the invention, to embodiment described above
Change, modification will all be fallen within the scope of claims of the present invention.
Claims (1)
1. a kind of synchronous method of improved sign synchronization loop, frequency division counter is used in the improved sign synchronization loop
Device, which is characterized in that the synchronous method the following steps are included:
S1 before sampling first takes absolute value to output data, realizes full-wave rectification；
S2, when sign synchronization, the data of advanced branch and lag branch sampling are equal, and the frequency counter is arranged at this time
Counting the period is 8, and the driving clock of the frequency counter is data sampling clock 48MHz, and the clock cycle is 6MHz after frequency dividing；
S3 indicates decline phase of the sampled value in eye figure peak value, sampling clock when advanced branch data is greater than lag branch data
Phase lags behind data clock phase, then one clock cycle of counting cycle time that the frequency counter is arranged is 7, under making
One sampling instant mentions previous sampling clock cycle；
S4 indicated upper drop phase of the sampled value in eye figure peak value, sampling clock phase when advanced branch data is less than lag data
It is ahead of data clock phase, then one clock cycle of counting period increase that the frequency counter is arranged is 9, is made next
Sampling instant mentions previous sampling clock cycle；
S5, step S2, repeatedly, when loop-locking, the symbol sampler moment is in eye figure always and opens the maximum moment S3 and S4 circulation
Near.
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| CN201811365510.3A CN109450608A (en) | 2018-11-16 | 2018-11-16 | A kind of synchronous method of improved sign synchronization loop |
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| CN201811365510.3A CN109450608A (en) | 2018-11-16 | 2018-11-16 | A kind of synchronous method of improved sign synchronization loop |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
| CN102185688A (en) * | 2011-04-29 | 2011-09-14 | 重庆金美通信有限责任公司 | Multi-symbol detecting and symbol synchronizing method based on CPM (critical path method) modulation |
| CN104639158A (en) * | 2014-12-30 | 2015-05-20 | 广东大普通信技术有限公司 | Method for regulating synchronous double phase-locked loops |
| CN105717523A (en) * | 2016-01-28 | 2016-06-29 | 中国电子科技集团公司第十研究所 | Range finding loop of spread spectrum measurement and control receiver |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulating system based on FPGA |
-
2018
- 2018-11-16 CN CN201811365510.3A patent/CN109450608A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
| CN102185688A (en) * | 2011-04-29 | 2011-09-14 | 重庆金美通信有限责任公司 | Multi-symbol detecting and symbol synchronizing method based on CPM (critical path method) modulation |
| CN104639158A (en) * | 2014-12-30 | 2015-05-20 | 广东大普通信技术有限公司 | Method for regulating synchronous double phase-locked loops |
| CN105717523A (en) * | 2016-01-28 | 2016-06-29 | 中国电子科技集团公司第十研究所 | Range finding loop of spread spectrum measurement and control receiver |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulating system based on FPGA |
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