CN109450469B - FPGA-based noise power calculation method - Google Patents

FPGA-based noise power calculation method Download PDF

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CN109450469B
CN109450469B CN201811633921.6A CN201811633921A CN109450469B CN 109450469 B CN109450469 B CN 109450469B CN 201811633921 A CN201811633921 A CN 201811633921A CN 109450469 B CN109450469 B CN 109450469B
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noise
receiver
uncertainty
intermediate frequency
power
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CN109450469A (en
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段飞
赵立军
魏连成
宋青娥
梁胜利
张庆龙
薛龙
袁国平
刘丹
李明太
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CLP Kesiyi Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/001—Measuring real or reactive component; Measuring apparent energy
    • G01R21/003—Measuring reactive component
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset

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Abstract

The invention discloses a noise power calculation method based on FPGA, belonging to the field of electronic test instruments, and the method provided by the invention removes the influence of DC offset on the sensitivity of a receiver and improves the sensitivity of the receiver; by adopting the method of averaging sampling points based on the intermediate frequency bandwidth of the receiver, the noise power uncertainty of the same level is obtained under different intermediate frequency bandwidths, and the uncertainty difference caused by different intermediate frequency bandwidths is made up, so that the design of the receiver is more reasonable.

Description

FPGA-based noise power calculation method
Technical Field
The invention belongs to the field of electronic test instruments, and particularly relates to a noise power calculation method based on an FPGA (field programmable gate array).
Background
The definition of the noise figure in IEEE refers to the ratio of the input signal-to-noise ratio and the output signal-to-noise ratio through the tested piece at the ambient temperature of 290K. The noise in the electronics is mainly thermal noise, so the noise power in the receiver varies with temperature. The dc offset caused by the electronics in the receiver is also affected by temperature and dc bias voltage variations. The noise power is related to the if the gain of the receiver with different if-band widths is not processed separately when the noise power is found, the uncertainty and dynamic range of the noise test will be affected.
The current instruments for measuring the noise coefficient in the market are mainly noise selection pieces of a noise coefficient analyzer and a frequency spectrum analyzer. The noise test requires a high sensitivity of the noise receiver, and the dc offset tends to affect the noise floor of the noise receiver. As the temperature and dc bias voltages drift, the amplifiers and other electronics in the receiver drift, which changes over time and can affect the noise test if not removed in real time. In other types of receivers, after ADC sampling is digitized, the dc offset of the signal is removed by averaging in the FPGA, but the averaging is not generally performed in real time, but rather a set of numbers are called out in advance and applied to the receiver. This conventional approach is suitable for situations where sensitivity requirements are not too high, or where signals are sampled rather than noise. In addition, the FPGA can provide real-time calculation, so that the real-time removal of the direct current offset is ensured. The traditional noise receiver does not perform special processing on the noise power caused by different bandwidths in the receiver, so that some loss of measurement uncertainty is caused.
The vector network analyzer is used as a testing instrument for testing S parameters and related parameters of microwave millimeter wave devices and systems, plays a very important role in the fields of modern integrated circuit research and development, radar and other system development and the like, and has a higher testing accuracy compared with a noise coefficient analyzer due to a noise coefficient measuring function under the vector network analyzer. The method is characterized in that due to the specific port calibration function of the vector network analyzer, the influence caused by the matching error is considered for the gain measurement of the DUT, and the gain measured by using the vector network analyzer is very accurate and can be just applied to noise measurement. Because the noise coefficient of the noise receiver selection of the vector network analyzer is very low, after ADC sampling, the numerical value obtained after FPGA multiple averaging can correctly reflect noise power data, and then the data can be sent to a host program of the vector network analyzer for next operation.
Noise is present in any electronic device and can cause significant interference to signals to be generated, transmitted and received by a user. In order to characterize the noise characteristics of electronic devices, engineers have introduced the concept of noise figure. With the rapid development of microwave communication, radar, navigation and other technologies, the requirement for low-noise devices is more and more urgent, which makes the testing and metering of noise coefficients extremely important. Amplifiers and other electronic devices often have dc offsets that vary with temperature and with drift in dc bias voltage. Two methods for removing dc offset in a test instrument are described below, one is a vector network analyzer and the other is a noise figure analyzer. In addition, the influence of the average number of times of each scanning point in the noise figure analyzer on the noise power calculation is described.
The method for removing the direct current offset in the vector network analyzer is to obtain a group of offsets in advance and then apply the offsets to actual tests. The receiver ADC of the vector network analyzer samples signals, is not noise, has not high sensitivity requirement, and can meet the requirement. When the circuit board is debugged, a group of N points are sampled, and the voltage value of each point is V1，V2…VNObtaining the vector mean value VbAs shown in the following formula (3):
Vb＝(V1+V2+…+VN)/N (3)
obtain the vector average value VbThen, at the time of testing, the measured voltage V is measuredmMinus VbTo obtain a true voltage value Vr，VrI.e. for subsequent calculations.
Vr＝Vm-Vb(22)
The receiver sensitivity requirement of the noise coefficient analyzer is higher than that of the vector network analyzer, so the offset V is removedbThe method of (c) is also different. However, like the vector network analyzer, the methods of formula (3) and formula (22) are still used, except that formula (3) is implemented in an FPGA. Each sampling obtains a V in real timebThen obtaining the real voltage value V through the formula (22)r. Adopting FPGA to sample in real time to obtain DC offset, making the obtained value closer to ambient temperature and DC offset, and sampling the obtained VrThe value is more real, and higher receiver sensitivity can be obtained. However, since this method is applied only when the dc offset is obtained in the FPGA and then the sampling average is performed, this offset is not a true offset, and there is still a certain deviation, so the receiver sensitivity is also affected to a certain extent.
The method for solving the noise coefficient by the noise coefficient analyzer is a Y factor method, and the noise power is required to be solved when the noise coefficient is solved. In the actual test, the noise power is obtained by sampling the noise voltage by the ADC and then obtaining the noise voltage. Since noise is a random quantity, theoretically an average of a myriad of points is required to obtain the true value of the noise power. Noise testing is the noise power obtained by averaging over a limited set of quantities, and so inevitably introduces uncertainty due to the randomness of the noise. The larger the number of averages per scan point, the smaller the uncertainty, but the longer the time required for the measurement.
Assuming that the noise is gaussian distributed, averaging N times will reduce the test uncertainty to one-square N, as shown in table 2 below.
TABLE 2 uncertainty versus number of averages
Figure GDA0002392087930000021
The average number of times N to be taken is determined from table 1 above, and it is generally necessary to take 10000 times or more depending on the requirement of noise figure uncertainty.
The noise power obtained at the frequency bandwidth is different in different receivers, and the relationship between the noise power and the bandwidth is as follows:
Pn(dB)＝10*log(KTB) (11)；
noisy receivers often have different intermediate frequency bandwidth choices, which can result in loss of uncertainty and dynamic range if the gain is not specially processed.
Existing test instrument pair signalOr the noise power is obtained by averaging in advance or averaging in the FPGA to obtain the DC offset VbAnd then, performing power acquisition by using an offset removal method. V found by such a methodbAnd actual VbThere is a difference that the effect of dc offset cannot be completely removed, so sensitivity to the receiver is a loss. It would be possible to improve the sensitivity of the receiver if there were a way to remove the dc offset in real time.
The existing noise coefficient analyzer does not perform special processing on different noise powers caused by different bandwidths in different receivers, so that measurement uncertainty and loss of a dynamic range are caused. According to the relationship between the noise power and the bandwidth and the relationship between the average times and the uncertainty, different average times are adopted for each scanning point under different bandwidths, so that the measurement under various intermediate frequency bandwidths can reach the same uncertainty level.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the noise power calculation method based on the FPGA, which is reasonable in design, overcomes the defects of the prior art and has a good effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a noise power calculation method based on FPGA adopts a method for removing DC offset in real time to remove the influence of the DC offset on the sensitivity of a receiver and improve the sensitivity of the receiver; by adopting a method for averaging the number of sampling points based on the intermediate frequency bandwidth of the receiver, the noise power uncertainty of the same level is obtained under different intermediate frequency bandwidths, the uncertainty difference caused by different intermediate frequency bandwidths is made up, the sensitivity level and the noise test uncertainty level of the noise receiver are improved, and a foundation is laid for the test of a noise coefficient measurement option of a vector network analyzer; the method specifically comprises the following steps:
step 1: determining the number N of sampling points required by each scanning point under the minimum intermediate frequency bandwidth;
by Gaussian distribution of noiseUncertainty P of noise power caused by clothJThe relation with the number N of sampling points is as follows:
Figure GDA0002392087930000031
the conversion to dB value is:
Figure GDA0002392087930000032
the size of N can be determined according to the required uncertainty;
step 2: the noise power obtained by different intermediate frequency bandwidths is different, and the relationship between the noise power and the bandwidth is as follows:
Pn(dB)＝10*log(KTB)
the uncertainty of the noise power caused by the receiver noise floor is related to the bandwidth as shown in equation (2):
Figure GDA0002392087930000033
wherein, PfIs the noise floor power of the receiver;
K—1.38×10-23J/K is Boltzmann constant;
b, medium frequency bandwidth;
t-equivalent input noise temperature of the noise receiver;
according to the formula (1) and the formula (2), the influence of the intermediate frequency bandwidth B and the number N of sampling points on the uncertainty is known to be approximate, and the relationship between the intermediate frequency bandwidth and the number of sampling points contained in each scanning point is determined by keeping B x N at a fixed value;
and step 3: acquiring the intermediate frequency bandwidth to be set through a vector network analyzer, determining the number of sampling points of a scanning point, and starting scanning;
and 4, step 4: in FPGA, the vector average value V of the number N of sampling points is circularly calculated according to formula (3)b；
Vb＝(V1+V2+…+VN)/N (3)；
And 5: in the FPGA, the sum of the squares of the sampled values, i.e., the total power P, is calculated according to equation (4)s；
Ps＝V1 2+V2 2+…+VN 2(4)；
Step 6: calculating a total power P of the removed offset valuesZ；
PZ＝(V1-Vb)2+(V2-Vb)2+…+(VN-Vb)2(5)；
Expanding equation (5) to the right yields:
PZ＝V1 2+V2 2+…+VN 2-2Vb(V1+V2+…+VN)+N*Vb 2(6)；
simplifying equation (6) yields:
PZ＝V1 2+V2 2+…+VN 2-N*Vb 2(7)；
substituting equation (4) into equation (7) yields:
Pz＝Ps-N*Vb 2(8)；
and 7: calculating the average power P of the removed offset valuea；
Multiplying both sides of equation (8) by N simultaneously yields:
NPz＝NPs-(NVb)2(9)；
by calculating P according to equation (10)a：
Pa＝NPZ/(N2) (10)；
And 8: calculating the finished average power PaThen, uploading the data to a vector network analyzer, and judging whether a screen is scanned or not;
if: if the judgment result is that one screen is not scanned, executing the step 3;
or the judgment result is that the screen is scanned completely, and then the operation is finished.
The invention has the following beneficial technical effects:
the method of the invention removes the influence of DC offset on the sensitivity of the receiver, and improves the sensitivity of the receiver; by adopting the method of averaging the number of sampling points based on the intermediate frequency bandwidth of the receiver, the noise power uncertainty of the same level is obtained under different intermediate frequency bandwidths, the uncertainty difference caused by different intermediate frequency bandwidths is made up, the design of the receiver is more reasonable, the sensitivity level and the noise test uncertainty level of the noise receiver can be improved by using the method, and a foundation is laid for the accurate test of the noise coefficient measurement option of the vector network analyzer.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the invention provides a noise power calculation method based on FPGA, which can remove the influence of DC offset on the sensitivity of a receiver in real time, and obtain the noise power uncertainty of the same level under different intermediate frequency bandwidths through the difference of the average times of the noise power; the method can improve the sensitivity level of the noise receiver and the uncertainty level of the noise test, and lays a foundation for the accurate test of the noise coefficient measurement option of the vector network analyzer.
First, a method for removing dc offset in real time will be described. As the temperature and dc bias voltage drift, the amplifiers and other electronics in the receiver have a dc offset. The receiver uses an analog-to-digital converter (ADC) chip to sample, so that the DC offset is reflected to the ADC along with the change of time, and if the DC offset cannot be removed in real time, the noise test is influenced.
The invention adopts a method for removing the direct current offset in real time, and the vector average and the average power are calculated for N sampling points when each scanning point is obtained, so that the influence of the direct current offset is removed in real time. Each scanning point is obtained after the voltage value of N sampling points is subjected to average processing, and after all the sampling points of the scanning point are collected, the average value after direct current is removed can be calculated by adopting a mathematical formula.
Let total power be PsTotal power P of the removed offset valuezThe average power of the removed offset value is PaThe number of sampling points is N, and the sampling point value is V1，V2…VNVector mean V of sample pointsbAnd (3) obtaining the data after sampling is finished according to the formula (1).
PaThe calculation and derivation process of (a) is as follows:
step 1: determining the number N of sampling points required by each scanning point under various intermediate frequency bandwidths;
uncertainty P of noise power caused by gaussian distribution of noiseJAnd the number N of sampling points is as follows:
Figure GDA0002392087930000051
the conversion to dB value should be:
Figure GDA0002392087930000052
it can be seen that if N is 10000, the uncertainty is 0.043 dB;
according to the required uncertainty, a certain margin is given, the size of N is determined, and in general, N is a value larger than 10000;
step 2: the noise power obtained by different intermediate frequency bandwidths is different in magnitude, and has the following relation:
Pn(dB)＝10*log(KTB)
let the bottom noise power of the receiver be PfThen the relationship between the uncertainty of noise power and bandwidth caused by the receiver bottom noise is:
Figure GDA0002392087930000061
K—1.38×10-23J/K is Boltzmann constant；
B, medium frequency bandwidth;
t-equivalent input noise temperature of the noise receiver;
observing the formula (1) and the formula (2), the influence of the bandwidth B and the number N of sampling points on the uncertainty is approximate. B x N may be kept at a fixed value to determine the relationship between the intermediate frequency bandwidth and the number of sample points contained in each scan point. For example, the average number of times N at each intermediate frequency bandwidth can be determined from table 1 below.
TABLE 1 relationship between bandwidth and number of samples
Medium frequency bandwidth Number of sampling points
800KHz 24N
2MHz 12N
4MHz 6N
8MHz 3N
24MHz N
And step 3: acquiring the intermediate frequency bandwidth to be set from a vector network analyzer, determining the number of sampling points of a scanning point, and starting scanning;
and 4, step 4: in FPGA, the vector average of the number N of sampling points is circularly calculated according to formula (3)Value Vb；
Vb＝(V1+V2+…+VN)/N (3)；
And 5: in the FPGA, the sum of the squares of the sampled values, i.e., the total power P, is calculated according to equation (4)s；
Ps＝V1 2+V2 2+…+VN 2(4)；
Step 6: calculating a total power P of the removed offset valuesZ；
PZ＝(V1-Vb)2+(V2-Vb)2+…+(VN-Vb)2(5)；
Expanding equation (5) to the right yields:
PZ＝V1 2+V2 2+…+VN 2+2Vb(V1+V2+…+VN)+N*Vb 2(6)；
simplifying equation (6) yields:
PZ＝V1 2+V2 2+…+VN 2-N*Vb 2(7)；
substituting equation (4) into equation (7) yields:
PZ＝Ps-N*Vb 2(8)；
and 7: calculating the average power P of the removed offset valuea；
Multiplying both sides of equation (8) by N simultaneously yields:
NPZ＝NPs-(NVb)2(9)；
by calculating P according to equation (10)a：
Pa＝NPZ/(N2) (10)；
And 8: calculating the finished average power PaAnd then uploading the data to a vector network analyzer, and returning to the step 3 to scan the next point until the scanning is finished.
Through the steps, after N sampling point cycles are carried out, the average power P for removing the deviation value can be obtained in real timea. The method ensures that the removed direct current offset value is more accurate, and improves the sensitivity of the receiver.
In the implemented noise receiver, a total of 5 intermediate frequency bandwidths are set. The medium frequency bandwidths are respectively 800KHz, 2MHz, 4MHz, 8MHz and 24 MHz. As can be seen from equation (11), the larger the bandwidth, the larger the obtained power, and the smaller the obtained power uncertainty with respect to the noise floor. If the average sampling times of each scanning point is the same as the gain of a receiver channel, the signal-to-noise ratio difference of the medium frequency bandwidths is 0dB, 4dB, 7dB, 10dB and 15dB (0 dB is set at 800 KHz). The number of sampling points and the bandwidth are correspondingly set, so that the influence of the medium-frequency bandwidth can be corrected. The number N of sampling points of each scanning point can be any number greater than 10000, and for the convenience of FPGA calculation, 2 is preferably selectednThe second power of the sample point.
The key points of the invention are as follows:
(1) a power calculation method for removing direct current offset in real time based on FPGA is adopted: by the method, the influence of the direct current offset on the acquisition of the noise power can be removed in real time, the sensitivity of the receiver is improved, and the scanning time is saved.
(2) A sampling point averaging method based on the intermediate frequency bandwidth of a receiver is adopted: by the method, the uncertainty of the noise power under different intermediate frequency bandwidths can be more uniform.
The protection points of the invention are as follows:
(1) FPGA-based power calculation method for removing DC offset in real time
The invention provides a noise power calculation method based on an FPGA (field programmable gate array), which can remove the influence of direct current offset on the sensitivity of a receiver in real time. The calculation method is derived through a formula, direct current offset does not need to be solved in advance, the direct current offset is solved in real time, sampling and averaging time is not delayed, and meanwhile the sensitivity of the receiver is improved.
(2) Averaging method based on intermediate frequency bandwidth of receiver
The noise power and the intermediate frequency bandwidth are correlated and the difference in signal-to-noise ratio and uncertainty caused by the intermediate frequency bandwidth can be known by the ratio between the different intermediate frequency bandwidths. Because the number of sampling points used in the noise power calculation of each scanning point is related to the uncertainty, the uncertainty difference caused by different intermediate frequency bandwidths can be made up through the number of sampling points.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.

Claims (1)

1. A noise power calculation method based on FPGA is characterized in that: the method for removing the direct current offset in real time is adopted to remove the influence of the direct current offset on the sensitivity of the receiver and improve the sensitivity of the receiver; by adopting a method for averaging the number of sampling points based on the intermediate frequency bandwidth of the receiver, the noise power uncertainty of the same level is obtained under different intermediate frequency bandwidths, the uncertainty difference caused by different intermediate frequency bandwidths is made up, the sensitivity level and the noise test uncertainty level of the noise receiver are improved, and a foundation is laid for the test of a noise coefficient measurement option of a vector network analyzer; the method specifically comprises the following steps:
step 1: determining the number N of sampling points required by each scanning point under the minimum intermediate frequency bandwidth;
uncertainty P of noise power caused by gaussian distribution of noiseJThe relation with the number N of sampling points is as follows:
Figure FDA0002392087920000011
the conversion to dB value is:
Figure FDA0002392087920000012
the size of N can be determined according to the required uncertainty;
step 2: the noise power obtained by different intermediate frequency bandwidths is different, and the relationship between the noise power and the bandwidth is as follows:
Pn(dB)＝10*log(KTB)
Pn(dB) represents the noise power;
the uncertainty of the noise power caused by the receiver noise floor is related to the bandwidth as shown in equation (2):
Figure FDA0002392087920000013
wherein, PfIs the noise floor power of the receiver;
K—1.38×10-23J/K is Boltzmann constant;
b, medium frequency bandwidth;
t-equivalent input noise temperature of the noise receiver;
PJ(dB) represents the uncertainty of the noise power;
according to the formula (1) and the formula (2), the influence of the intermediate frequency bandwidth B and the number N of sampling points on the uncertainty is known to be approximate, and the relationship between the intermediate frequency bandwidth and the number of sampling points contained in each scanning point is determined by keeping B x N at a fixed value;
and step 3: acquiring the intermediate frequency bandwidth to be set through a vector network analyzer, determining the number of sampling points of a scanning point, and starting scanning;
and 4, step 4: in FPGA, the vector average value V of the number N of sampling points is circularly calculated according to formula (3)b；
Vb＝(V1+V2+…+VN)/N (3)；
V1The sampling voltage value of the 1 st sampling point is represented; v2A sampling voltage value representing a 2 nd sampling point; vNA sampling voltage value representing an Nth sampling point;
and 5: in the FPGA, the sum of the squares of the sampled values, i.e., the total power P, is calculated according to equation (4)s；
Ps＝V1 2+V2 2+…+VN 2(4)；
Step 6: calculating a total power P of the removed offset valuesZ；
PZ＝(V1-Vb)2+(V2-Vb)2+…+(VN-Vb)2(5)；
Expanding equation (5) to the right yields:
PZ＝V1 2+V2 2+…+VN 2-2Vb(V1+V2+…+VN)+N*Vb 2(6)；
simplifying equation (6) yields:
PZ＝V1 2+V2 2+…+VN 2-N*Vb 2(7)；
substituting equation (4) into equation (7) yields:
PZ＝Ps-N*Vb 2(8)；
and 7: calculating the average power P of the removed offset valuea；
Multiplying both sides of equation (8) by N simultaneously yields:
NPz＝NPs-(NVb)2(9)；
by calculating P according to equation (10)a：
Pa＝NPZ/(N2) (10)；
And 8: calculating the finished average power PaThen, uploading the data to a vector network analyzer, and judging whether a screen is scanned or not; if: if the judgment result is that one screen is not scanned, executing the step 3;
or the judgment result is that the screen is scanned completely, and then the operation is finished.
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