CN109450045B - Multi-battery management protection chip and multi-battery management protection system - Google Patents
Multi-battery management protection chip and multi-battery management protection system Download PDFInfo
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- CN109450045B CN109450045B CN201811568699.6A CN201811568699A CN109450045B CN 109450045 B CN109450045 B CN 109450045B CN 201811568699 A CN201811568699 A CN 201811568699A CN 109450045 B CN109450045 B CN 109450045B
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- 238000001514 detection method Methods 0.000 claims abstract description 21
- 238000007599 discharging Methods 0.000 claims abstract description 10
- 229910052744 lithium Inorganic materials 0.000 claims description 8
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 229910001386 lithium phosphate Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
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- H02J7/0026—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
A multi-cell management protection chip and a multi-cell management protection system, the multi-cell management protection chip comprising: the device comprises a grounding pin, a charging drive output enabling end, a charging drive output pin, a discharging drive output pin and a register; further comprises: the adapter identification unit comprises a control input end, a detection end and a state output end; the control input end is connected with the charging drive output enabling end; the detection end is connected with the charging drive output pin; the state output end is connected with the register. The multi-cell management protection chip can provide detection and protection.
Description
Technical Field
The invention relates to the field of electricity, in particular to a multi-battery management protection chip and a multi-battery management protection system.
Background
In some electric devices, such as electric (self) vehicles, sweeping robots, balance cars, etc., it is often necessary to use multiple batteries.
In the early days, when a plurality of batteries are protected, a single battery protection chip is used on each battery. The protection technology is high in cost and unfavorable for linkage protection among multiple lithium batteries.
In a multi-lithium battery protection system, when the system detects that the battery is over-voltage or over-current is generated, the charging path needs to be disconnected, and the charging path can be opened again after the adapter is removed; when the system detects that the battery is under-voltage, the discharging path needs to be disconnected, and the discharging path can be opened again after the adapter is connected.
A multi-battery management protection chip 10 has been developed which is combined with a protection system consisting of a charging adapter and a multi-battery, as shown in fig. 1.
The internal circuit structure and most pins of the multi-cell management protection chip 10 are omitted in fig. 1. Therein, the multi-cell management protection chip 10 is shown to include a ground pin VSS, a charge driving output pin CHG, a discharge driving output pin DSG, and a register (not shown).
The protection system further comprises an NMOS tube Q1, an NMOS tube Q2, a PMOS tube Q3 and a resistor R1. The drain electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2. One end of the resistor R1 is connected with the grid electrode of the NMOS tube Q2, and the other end of the resistor R is connected with the source electrode of the NMOS tube Q2. The ground pin VSS is connected to the source of the NMOS transistor Q1. The discharge driving output pin DSG is connected to the gate of the NMOS transistor Q1. The charge driving output pin CHG is connected to the gate of the NMOS transistor Q2 (please consider that the PMOS transistor Q3 is not present, and the charge driving output pin CHG is directly connected to the gate of the NMOS transistor Q2).
The source of the NMOS transistor Q2 serves as a charging negative electrode access terminal. The negative electrode of the battery pack BT (a plurality of batteries shown in fig. 1) is connected to the ground pin VSS, and the ground pin VSS is connected to the negative electrode of the charging adapter after passing through the NMOS transistor Q1 and the NMOS transistor Q2, where the source electrode of the NMOS transistor Q2 is connected to the charging negative electrode terminal P-, i.e. the source electrode of the NMOS transistor Q2 is connected to the negative electrode of the charging adapter. The positive pole of the battery BT is connected to the charging positive pole p+, i.e. the positive pole for connecting to the charging adapter.
In the above protection system, when the system generates an overvoltage or a charging overcurrent of the battery BT, it is necessary to cut off the charging path to secure the safety of the battery and the system.
However, as shown in fig. 1, in the conventional protection system, when the charging path is disconnected, the positive charging terminal p+ is connected to the positive terminal of the multiple batteries BT, the voltage connected to the negative terminal P "of the charging adapter is a negative voltage with respect to the voltage of the negative terminal of the battery pack, and the negative terminal P" of the charging adapter is looped to the ground pin VSS of the multiple battery management protection chip 10 through the resistor R1 and the charging control pin CHG, resulting in a voltage difference (VGS) between the gate and source of the NMOS transistor Q2, so that the charging path cannot be completely turned off.
It should be noted that, in fig. 1, the diodes in the MOS transistors are corresponding parasitic diodes, and due to the parasitic diode of the NMOS transistor Q1 and the positive and negative directions of the parasitic diode, it is determined that the charging path cannot be normally turned off by turning off the NMOS transistor Q1, but the charging path needs to be turned off by the NMOS transistor Q2.
In order to ensure that the charging path is completely turned off, a PMOS transistor Q3 with a grounded gate VSS is added in fig. 1, that is, in fact, the charging driving output pin CHG is not directly connected to the gate of the NMOS transistor Q2, but the charging driving output pin CHG is connected to the source of the PMOS transistor Q3, the gate of the PMOS transistor Q3 is grounded (i.e., connected to the corresponding ground pin VSS), and the drain of the PMOS transistor Q3 is connected to the gate of the NMOS transistor Q2. That is, the charging drive output pin CHG is connected to the gate of the NMOS transistor Q2 through the PMOS transistor Q3.
The drain electrode of the PMOS transistor Q3 is a negative voltage with respect to the ground pin VSS, when the PMOS transistor Q3 is in the off state, there is no current loop from P-to the ground pin VSS, and the gate-source voltage of the charge control NMOS transistor Q2 is equal to zero, so that the charge path can be completely turned off.
When the system is in a normal state and the charging path needs to be opened, the multi-cell management protection chip 10 controls the CHG pin output to be high level, the PMOS transistor Q3 is in a conducting state, the NMOS transistor Q2 is restarted, and the charging path is restarted.
However, in the protection system shown in fig. 1, due to the PMOS transistor Q3, the negative voltage of the negative terminal P-of the charging adapter is completely isolated from the battery management protection chip 10, so that the battery management protection chip 10 cannot recognize the state of the adapter. In this case, the microprocessor is usually required to determine the state of the adapter by means of other detection circuits. That is, in the system of fig. 1, the charge control drive and the adapter detection also need to be implemented separately, and additional peripheral devices are required.
Disclosure of Invention
The invention solves the problem of providing a multi-battery management protection chip and a multi-battery management protection system, so as to save a peripheral detection circuit outside the chip and improve the reliability of the corresponding multi-battery management protection system.
In order to solve the above problems, the present invention provides a multi-cell management protection chip, comprising: the device comprises a grounding pin, a charging drive output enabling end, a charging drive output pin, a discharging drive output pin and a register; further comprises: the adapter identification unit comprises a control input end, a detection end and a state output end; the control input end is connected with the charging drive output enabling end; the detection end is connected with the charging drive output pin; the state output end is connected with the register.
Optionally, the adapter identification unit further comprises a high voltage power supply input, a low voltage power supply input, and a bias voltage input.
Optionally, the adapter identification unit further includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first constant current power supply, and a hysteresis comparison unit; the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are all enhancement type MOS tubes; the grid electrode of the first PMOS tube is used as the control input end; the source electrode of the first PMOS tube is connected with the input end of the high-voltage power supply; the drain electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the source electrode of the second PMSO tube; the drain electrode of the second PMSO pipe is used as the detection end; the positive electrode end of the first constant current power supply is connected with the input end of the low-voltage power supply; the negative electrode end of the first constant current power supply is connected with the source electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the input end of the low-voltage power supply; the drain electrode of the second NMOS tube is connected with the source electrode of the second PMSO tube; the input end of the hysteresis comparison unit is connected with the negative end of the first constant current power supply; the output end of the hysteresis comparison unit is used as the state output end.
Optionally, a voltage clamping unit is connected between the gate and the source of the second PMSO pipe.
Optionally, the voltage clamping unit includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a second constant current power supply; the third PMOS tube, the fourth PMOS tube and the third NMOS tube are all enhanced; the source electrode of the third PMOS tube is connected with the source electrode of the second PMOS tube; the drain electrode of the third PMOS tube is connected with the grid electrode and the source electrode of the fourth PMOS tube; the drain electrode of the fourth PMOS tube is connected with the grid electrode and connected with the grid electrode of the second PMOS tube; the drain electrode of the third NMOS tube is connected with the grid electrode of the second PMOS tube; the grid electrode of the third NMOS tube is connected with the bias voltage input end; the positive electrode end of the second constant current power supply is connected with the source electrode of the third NMOS tube; and the negative electrode of the second constant current power supply is grounded.
Optionally, the voltage clamping unit comprises a first diode, a second diode, a third NMOS tube and a second constant current power supply; the third NMOS tube is of an enhanced type; the anode of the first diode is connected with the source electrode of the second PMOS tube; the cathode of the first diode is connected with the anode of the second diode; the cathode of the second diode is connected with the grid electrode of the second PMOS tube; the drain electrode of the third NMOS tube is connected with the grid electrode of the second PMOS tube; the grid electrode of the third NMOS tube is connected with the bias voltage input end; the positive electrode end of the second constant current power supply is connected with the source electrode of the third NMOS tube; and the negative electrode of the second constant current power supply is grounded.
Optionally, the hysteresis comparison unit is a schmitt trigger.
In order to solve the above problems, the present invention provides a multi-cell management protection system, including the aforementioned multi-cell management protection chip, and further including a fourth NMOS transistor, a fifth NMOS transistor, a resistor, and a battery pack, where the battery pack includes a plurality of cells connected in series; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube; one end of the resistor is connected with the grid electrode of the fifth NMOS tube, and the other end of the resistor is connected with the source electrode of the fifth NMOS tube; the grounding pin of the multi-cell management protection chip is connected with the source electrode of the fourth NMOS tube and the cathode of the battery pack; the discharging driving output pins of the multiple battery management protection chips are connected with the grid electrode of the fourth NMOS tube; the charging drive output pin of the battery management protection chip is connected with the grid electrode of the fifth NMOS tube; the source electrode of the fifth NMOS tube is connected with a charging negative electrode terminal; the positive electrode of the battery pack is connected with the charging positive electrode terminal.
Optionally, the multiple battery management protection chips are as described above, the product of the first constant current power supply and the resistor is smaller than the turn-on voltage of the first NMOS, and the product of the first constant current power supply and the resistor is smaller than the turn-on voltage of the second NMOS.
Optionally, the battery is a lithium battery or a lithium polymer battery.
In one aspect of the technical scheme of the invention, the adapter identification unit is integrated in the chip, so that even if an abnormality occurs in a corresponding multi-battery management protection system with the chip, the charging path is opened when an error instruction is sent, and the multi-battery management protection chip can detect that the adapter is not removed and can not open the charging path, thereby improving the reliability of the multi-battery management protection system. Meanwhile, as no additional PMOS tube devices are required to be arranged in the peripheral circuit, the multi-cell management protection chip can save a peripheral detection circuit outside the chip, and the reliability of the corresponding multi-cell management protection system is improved.
Drawings
FIG. 1 is a circuit diagram of a prior art multi-cell battery management protection system;
Fig. 2 is a circuit diagram of a multi-cell management protection system in an embodiment of the present invention.
Detailed Description
When the charge protection system detects battery overvoltage, if the corresponding battery pack is continuously charged, the system is subject to reliability risk. Therefore, the charging path must be disconnected and only after the adapter is removed can the charging path be re-opened.
With conventional charge protection systems, it is necessary to add peripheral devices and detection circuitry. When the peripheral device is used, attention is paid to factors such as the voltage withstand value of the peripheral device, and if the voltage withstand of the peripheral device is insufficient, the charging path cannot be completely closed, so that the safety of the system is affected.
Therefore, the invention provides a novel multi-battery management protection chip and a multi-battery management protection system, which are used for solving the defects in the prior art.
The present invention will be described in detail with reference to the accompanying drawings for more clear illustration.
Referring to fig. 2, an embodiment of the present invention provides a multi-cell management protection chip 20, and simultaneously provides a multi-cell management protection system with the multi-cell management protection chip 20.
The multi-cell management protection chip 20 includes: ground pin VSS, charge drive output enable terminal EN, charge drive output pin CHG, discharge drive output pin DSG, and registers.
The multi-cell management protection chip 20 further includes: the adapter identifying unit 21, the adapter identifying unit 21 includes a control input terminal (not labeled), a detection terminal (not labeled), and a status output terminal (not labeled). Wherein, the control input end is connected with the charging driving output enabling end EN. The detection end is connected with a charging driving output pin CHG. The state output end is connected with the register.
The state output end is connected with the register, and then the corresponding microprocessor judges the state of the adapter by reading (actively reading) the numerical value of the register in the multi-cell management protection chip. For example, in one case, when a status output stores a "0" into a corresponding register, an adapter removal is indicated (instructed); when the status output stores a "1" into the corresponding register, then the adapter access is indicated (instructed). In this embodiment, the adapter identification unit 21 further comprises a high voltage power supply input HV, a low voltage power supply input LV and a bias voltage input bias. The voltage at the high voltage power supply input HV may be a usual chip logic high voltage, for example 12V. Accordingly, the voltage at the low voltage supply input LV may be a conventional chip logic low voltage, such as 5V.
It should be noted that the voltages of the high voltage power input HV and the low voltage power input LV may be provided by a linear regulator (low dropout regulator) inside the chip.
The adapter identifying unit 21 further includes a first PMOS pipe PM1, a second PMOS pipe PM2, a first NMOS pipe NM1, a second NMOS pipe NM2, a first constant current source I1, and a hysteresis comparing unit 212.
The first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1 and the second NMOS tube NM2 are all enhancement type MOS tubes. The gate of the first PMOS tube PM1 is used as a control input terminal. The source electrode of the first PMOS tube PM1 is connected with the high-voltage power input end HV. The drain electrode of the first PMOS tube PM1 is connected with the source electrode of the first NMOS tube NM 1. The gate of the first NMOS tube NM1 is connected with the source of the first PMOS tube PM 1. The drain electrode of the first NMOS tube NM1 is connected with the source electrode of the second PMOS tube PM2. The drain electrode of the second PMOS tube PM2 is used as a detection end. The positive terminal of the first constant current power supply I1 is connected with the low-voltage power supply input terminal LV. The negative end of the first constant current power supply I1 is connected with the source electrode of the second NMOS tube NM 2. The gate of the second NMOS transistor NM2 is connected to the low voltage power input terminal LV. The drain electrode of the second NMOS tube NM2 is connected with the source electrode of the second PMOS tube PM2. The input end of the hysteresis comparison unit 212 is connected to the negative end of the first constant current power supply I1. The output of the hysteresis comparison unit 212 serves as a state output.
The current of the first constant current source I1 is typically in the microampere level, so that the first constant current source I1 does not affect the low voltage power input LV.
According to the above circuit structure, the embodiment uses the first NMOS and the second PMOS to isolate the high voltage input terminal from the corresponding external voltage in the protection system mentioned later, wherein the second PMOS is used to isolate the negative voltage, and the first NMOS is used to isolate the high voltage.
In this embodiment, the first NMOS transistor and the second PMOS transistor are used to isolate the voltage input terminal from the corresponding external voltage in the protection system mentioned later, that is, the second PMOS transistor is used to isolate the negative voltage, and the first NMOS transistor is used to isolate the high voltage. However, in other embodiments of the present invention, the first NMOS transistor and the second PMOS transistor may be replaced by other circuit structures (usually more complex in structure), and thus the present invention is not limited by the specific circuit structures described above.
In this embodiment, the voltage clamping unit 211 is connected between the gate and the source of the second PMOS transistor PM 2. The voltage clamping unit 211 is configured to ensure that the source gate Voltage (VSG) of the second PMOS transistor PM2 does not exceed the withstand voltage value of the device.
In the specific circuit structure shown in fig. 2, the voltage clamping unit 211 includes a third PMOS tube PM3, a fourth PMOS tube PM4, a third NMOS tube NM3, and a second constant current power supply I2. The third PMOS pipe PM3, the fourth PMOS pipe PM4, and the third NMOS pipe NM3 are all enhancement type. The source electrode of the third PMOS tube PM3 is connected with the source electrode of the second PMOS tube PM 2. The drain electrode of the third PMOS tube PM3 is connected with the grid electrode and is connected with the source electrode of the fourth PMOS tube PM 4. The drain electrode of the fourth PMOS tube PM4 is connected with the grid electrode and connected with the grid electrode of the second PMOS tube PM 2. The drain electrode of the third NMOS tube NM3 is connected with the grid electrode of the second PMOS tube PM 2. The gate of the third NMOS transistor NM3 is connected to the bias voltage input bias. The positive terminal of the second constant current power supply I2 is connected with the source electrode of the third NMOS tube NM 3. The negative electrode of the second constant current power supply I2 is grounded.
The second constant current power supply I2 is used for guaranteeing clamping of the second PMOS tube PM2, the constant current source is usually composed of a low-voltage device, and a third NMOS tube is used for isolating high voltage on the grid electrode of the second PMOS tube. The second constant current power supply I2 may have a size of 1. Mu.A to 10. Mu.A. The clamping circuit in the voltage clamping unit 211 can be adjusted according to the process requirements.
The bias voltage input bias is used to ensure the conduction of the third NMOS transistor NM3, and in this embodiment, the bias voltage input bias is a separate voltage input. In other embodiments, bias voltage input bias may be connected to low voltage input LV to provide the same voltage.
In this embodiment, the hysteresis comparison unit 212 is a schmitt trigger S1. In other embodiments, the hysteresis comparison unit 212 may be a comparator with hysteresis.
It should be noted that in other embodiments of the present invention, the voltage clamping unit may further include a first diode, a second diode, a third NMOS transistor, and a second constant current power supply. The third NMOS tube is enhanced. The positive electrode of the first diode is connected with the source electrode of the second PMOS tube. The negative electrode of the first diode is connected with the positive electrode of the second diode. The negative electrode of the second diode is connected with the grid electrode of the second PMOS tube. And the drain electrode of the third NMOS tube is connected with the grid electrode of the second PMOS tube. And the grid electrode of the third NMOS tube is connected with the bias voltage input end. The positive electrode end of the second constant current power supply is connected with the source electrode of the third NMOS tube. The negative electrode of the second constant current power supply is grounded.
In addition, in other embodiments, the number of diodes may be three to five, similar to the above structure, and directly connected in series. In general, the diode is arranged to prevent the second PMOS transistor from exceeding the corresponding withstand voltage.
The multi-cell management protection chip 20 provided in this embodiment may be used to realize functions such as monitoring, protection and management of a cell. It can be formed by using a battery management chip of the model VAS5118 of Qiji technology company, and by designing the corresponding adapter identification unit 21 in a modified manner and combining it with other structures in the chip in the manner described above. The battery management protection chip 20 according to the present embodiment may be obtained by modifying a battery management chip of the bq769x0 series (bq 76920, bq76930, bq76940, etc.) model number of texas instruments, or a battery management chip of the OZ890 model number of concavo-convex electronics (O2 Micro). That is, in general, a plurality of existing battery management chips having the above-described pin structures and end portions are combined with the corresponding structures and modes by adding the adapter recognition unit 21, the multi-cell management protection chip 20 of the present embodiment can be obtained.
In the multi-battery management protection system provided in this embodiment, the multi-battery management protection system further includes a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a resistor R1, and a battery BT, where the battery BT includes a plurality of batteries (not labeled) connected in series.
The drain electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the fifth NMOS tube NM 5. One end of the resistor R1 is connected with the grid electrode of the fifth NMOS tube NM5, and the other end of the resistor R1 is connected with the source electrode of the fifth NMOS tube NM 5. The ground pin VSS of the multi-cell management protection chip 20 is connected to the source of the fourth NMOS transistor NM4 and to the negative electrode of the battery BT. The discharge driving output pin DSG of the multi-cell management protection chip 20 is connected to the gate of the fourth NMOS transistor NM 4. The charging drive output pin CHG of the multi-cell management protection chip 20 is connected to the gate of the fifth NMOS transistor NM 5. The source of the fifth NMOS transistor NM5 is connected to the charging negative terminal. The positive electrode of the battery BT is connected to the charging positive electrode terminal.
In this embodiment, as shown in fig. 2, the first constant current power supply I1 and the second constant current power supply I2 are located inside the chip, and the resistor R1 is located in a peripheral circuit outside the chip, but the three components can affect whether the corresponding voltage turns on the fifth NMOS NM5, so as to affect whether the charging path can be completely turned off.
In order to ensure that the charging path is completely closed, the current difference between the first constant current source I1 and the second constant current source I2 is set in this embodiment, and the product of the current difference and the resistor R1 is smaller than the turn-on voltage of the fifth NMOS transistor NM 5. For example, if the resistance of the resistor R1 is 1MΩ, the current difference (i.e. I1-I2) is set to less than 1 μA (or 0.7 μA).
In this embodiment, the battery may be a lithium battery (e.g., lithium ion and phosphate battery) or a lithium polymer battery.
In the multi-cell management protection system provided in this embodiment, when the charge control is enabled, the charge driving output enable end EN of the multi-cell management protection chip 20 is at a logic low level, the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, and the output voltage of the charge driving output pin CHG is equal to the voltage of the high-voltage power input end HV in the chip interior, so that the fifth NMOS tube NM5 in the external circuit is turned on, and the voltage of the charge negative end is equal to the ground voltage of the ground pin VSS.
In the multi-battery management protection system provided in this embodiment, when the charging control is turned off, the charging driving output enable terminal EN is at a logic high level, the first PMOS tube PM1 is turned off, and at this time, the voltage of the corresponding detection terminal, that is, the voltage of the charging driving output pin CHG, is divided into three cases by different external conditions: external suspension, external load and external adapter.
First, when the outside is floating, the internal low voltage input terminal LV pulls the voltage of the charging driving output pin CHG to the voltage of the internal low voltage input terminal LV through a small current, and the internal hysteresis comparison unit 212 generates a status signal, and the output is at a logic low level, that is, as described above, a "0" is stored in the corresponding register, which indicates that no adapter is connected at this time.
Second, when the external load is connected, the discharging driving output pin DSG is also turned off and the discharging loop is also turned off while the charging control is turned off, so that the voltage at the charging negative terminal is pulled to the positive terminal voltage of the battery BT, the second PMOS tube PM2 is turned on, but the first NMOS tube NM1 and the second NMOS tube NM2 isolate the internal circuit from the positive terminal of the battery BT, and the internal hysteresis comparing unit 212 generates a status signal and outputs a logic low level, that is, "0" is stored in the corresponding register, indicating that no adapter is connected at this time.
Third, when the adapter is connected externally, the second PMOS tube PM2 is turned on, the voltage of the charging driving output pin CHG is equal to the voltage of the charging negative terminal plus the product of the constant current power supply (I1-I2) and the resistor R1 (as described above, the product of the current difference and the resistor R1 is smaller than the turn-on voltage of the corresponding NMOS conduction), since the gate of the second PMOS tube PM2 can only reach the voltage of the ground pin VSS at the lowest level (the voltage of the ground pin VSS is the lowest voltage in the chip, the second PMOS tube PM2 is located inside the chip), the source of the second PMOS tube PM2 is pulled to the PMOS conduction voltage, and the internal hysteresis comparison unit 212 generates a status signal, and outputs a logic high level, that is, "1" is stored in the corresponding register, indicating that the adapter is connected at this time.
As is known from the driving method of the above-described multi-cell management protection chip 20, the chip isolates the internal circuit from both external high voltage and negative voltage by controlling and detecting the output driving. In the present specification, the high voltage means the highest voltage of the plurality of batteries, and the negative voltage means the ground voltage lower than the chip ground pin VSS.
In addition, the multiple battery management protection chips 20 can identify the removal and access of the adapter, peripheral devices and detection circuits are saved, and the reliability of the battery protection system is improved.
It can be seen that the multi-cell management protection chip 20 of the present invention not only can be used for identifying whether the adapter is connected or not, but also can ensure the corresponding voltage isolation function, and prevent the chip from being affected by high voltage and negative voltage due to the load and the adapter state.
That is, with the above-described circuit design, the plurality of battery management protection chips 20 can output different states including a state of whether or not an adapter is connected after the charging path is closed in the corresponding plurality of battery management protection systems.
By integrating the adapter identifying unit 21 inside the chip, in the multi-battery management protection system, even if an abnormality occurs, an error instruction is issued to open the charging path, and since the multi-battery management protection chip 20 detects that the adapter is not removed, the charging path is not opened, thereby improving the reliability of the multi-battery management protection system. Meanwhile, since no additional PMOS transistor devices (such as the PMOS transistor Q3 in fig. 1) are required to be disposed in the peripheral circuit, it is known that the multiple battery management protection chip 20 can save a peripheral detection circuit outside the chip, and the reliability of the corresponding multiple battery management protection system is improved.
It should be noted that the battery management protection chip 20 provided in this embodiment is not limited to use in the protection system shown in fig. 2. The battery management protection chip 20 may be used in various protection system circuits, for example, a charging path and a discharging path may be shared or may be separately controlled. The internal detection current is adjusted according to the application requirements, and any circuit mode that needs to isolate high voltage from negative voltage and detect negative voltage can be considered as the application range of the invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (7)
1. A multi-cell management protection chip, comprising:
The device comprises a grounding pin, a charging drive output enabling end, a charging drive output pin, a discharging drive output pin and a register;
Characterized by further comprising:
the adapter identification unit comprises a control input end, a detection end and a state output end;
the control input end is connected with the charging drive output enabling end; the detection end is connected with the charging drive output pin; the state output end is connected with the register;
The adapter identification unit further comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first constant current power supply and a hysteresis comparison unit;
The first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are all enhancement type MOS tubes;
The grid electrode of the first PMOS tube is used as the control input end;
The source electrode of the first PMOS tube is connected with the input end of the high-voltage power supply;
the drain electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube;
The grid electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube;
the drain electrode of the first NMOS tube is connected with the source electrode of the second PMOS tube;
The drain electrode of the second PMOS tube is used as the detection end;
The positive electrode end of the first constant current power supply is connected with the input end of the low-voltage power supply;
the negative electrode end of the first constant current power supply is connected with the source electrode of the second NMOS tube;
The grid electrode of the second NMOS tube is connected with the input end of the low-voltage power supply;
the drain electrode of the second NMOS tube is connected with the source electrode of the second PMOS tube;
The drain electrode of the second NMOS tube is also connected with the drain electrode of the first NMOS tube;
the input end of the hysteresis comparison unit is connected with the negative end of the first constant current power supply;
the output end of the hysteresis comparison unit is used as the state output end;
the power supply end of the hysteresis comparison unit is connected with the input end of the low-voltage power supply, and the other end of the hysteresis comparison unit is grounded;
a voltage clamping unit is connected between the grid electrode and the source electrode of the second PMOS tube;
the hysteresis comparison unit is a schmitt trigger.
2. The multi-cell management protection chip of claim 1, wherein the adapter identification unit further comprises a high voltage power supply input, a low voltage power supply input, and a bias voltage input.
3. The multi-cell management protection chip of claim 2, wherein the voltage clamping unit comprises a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a second constant current power supply;
The third PMOS tube, the fourth PMOS tube and the third NMOS tube are all enhanced;
the source electrode of the third PMOS tube is connected with the source electrode of the second PMOS tube;
The drain electrode of the third PMOS tube is connected with the grid electrode and the source electrode of the fourth PMOS tube;
The drain electrode of the fourth PMOS tube is connected with the grid electrode and connected with the grid electrode of the second PMOS tube;
the drain electrode of the third NMOS tube is connected with the grid electrode of the second PMOS tube;
the grid electrode of the third NMOS tube is connected with the bias voltage input end;
the positive electrode end of the second constant current power supply is connected with the source electrode of the third NMOS tube;
And the negative electrode of the second constant current power supply is grounded.
4. The multi-cell management protection chip of claim 2, wherein the voltage clamping unit comprises a first diode, a second diode, a third NMOS transistor, and a second constant current power supply;
The third NMOS tube is of an enhanced type;
The anode of the first diode is connected with the source electrode of the second PMOS tube;
The cathode of the first diode is connected with the anode of the second diode;
The cathode of the second diode is connected with the grid electrode of the second PMOS tube;
the drain electrode of the third NMOS tube is connected with the grid electrode of the second PMOS tube;
the grid electrode of the third NMOS tube is connected with the bias voltage input end;
the positive electrode end of the second constant current power supply is connected with the source electrode of the third NMOS tube;
And the negative electrode of the second constant current power supply is grounded.
5. A multi-cell management protection system, comprising the multi-cell management protection chip according to any one of claims 1 to 4, further comprising a fourth NMOS transistor, a fifth NMOS transistor, a resistor, and a battery pack, the battery pack comprising a plurality of cells connected in series;
The drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
One end of the resistor is connected with the grid electrode of the fifth NMOS tube, and the other end of the resistor is connected with the source electrode of the fifth NMOS tube;
the grounding pin of the multi-cell management protection chip is connected with the source electrode of the fourth NMOS tube and the cathode of the battery pack;
the discharging driving output pins of the multiple battery management protection chips are connected with the grid electrode of the fourth NMOS tube;
The charging drive output pin of the battery management protection chip is connected with the grid electrode of the fifth NMOS tube;
The source electrode of the fifth NMOS tube is connected with a charging negative electrode terminal;
the positive electrode of the battery pack is connected with the charging positive electrode terminal.
6. The multi-cell management protection system according to claim 5, wherein the product of the current difference between the first constant current power supply and the second constant current power supply and the resistor R1 is smaller than the turn-on voltage of the fifth NMOS transistor.
7. The multi-cell management protection system of claim 5, wherein the cell is a lithium cell or a lithium polymer cell.
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