CN109449118B - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN109449118B CN109449118B CN201811275693.XA CN201811275693A CN109449118B CN 109449118 B CN109449118 B CN 109449118B CN 201811275693 A CN201811275693 A CN 201811275693A CN 109449118 B CN109449118 B CN 109449118B
- Authority
- CN
- China
- Prior art keywords
- layer
- light shielding
- tft
- shielding layer
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims description 46
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- 239000010408 film Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 9
- 238000000059 patterning Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention relates to the technical field of display, and discloses a preparation method of an array substrate and the array substrate, wherein the preparation method of the array substrate comprises the following steps: forming a first light shielding layer between the fingerprint identification sensor in the display area and an active layer of the TFT above the fingerprint identification sensor, wherein the first light shielding layer is used for shielding the TFT; forming a second light shielding layer between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor, the second light shielding layer for shielding infrared rays of the infrared sensor from being irradiated onto the TFT; the thickness of first light shield layer is less than the thickness of second light shield layer, can solve the light shield layer and to the different contradictions of different regional TFT electrical property influences in the array substrate, has both guaranteed that the active layer pattern edge that corresponds above the fingerprint identification sensor relates to less abnormal area, guarantees again that the active layer that corresponds above the infrared sensor can not leak the light to make the channel on the whole TFT even, and have good mobility.
Description
Technical Field
The invention relates to the technical field of display, in particular to a preparation method of an array substrate and the array substrate.
Background
An active matrix organic light emitting diode (AMO L ED) display device is widely applied due to its advantages of self-luminescence, wide viewing angle, fast response, etc., and currently, a backplane in the AMO L ED generally employs a low-temperature polysilicon TFT (thin film transistor) with high carrier mobility, which is mainly implemented by excimer laser annealing (E L a), solid-phase crystallization or metal-induced crystallization, etc., whereas E L a is the only existing mass production technology for manufacturing polysilicon.
However, the preparation process of the low-temperature polysilicon back plate is complex, and particularly, infrared light emitted by the infrared sensor easily directly hits a TFT channel when the back plate with local transparent display is not provided with a light shielding layer, so that the characteristics of the TFT are affected by the infrared light, and the threshold voltage (V) of the TFT is causedth) And the drift causes the phenomenon that infrared light spots appear on the finally formed display screen. At present, a method for eliminating infrared light spots is generally adopted, namely a light shielding layer is arranged below a buffer layer or amorphous silicon (a-Si) during manufacturing of an array substrate, the light shielding layer is thicker in order to shield infrared light, but the existence of the light shielding layer can influence the size of an abnormal area related to the edge of an upper polysilicon (p-Si) pattern, and the size of the abnormal area related to the edge of the upper polysilicon (p-Si) pattern is gradually increased along with the gradual increase of the thickness of the light shielding layer, namely the larger the thickness of the light shielding layer is, the larger the defect area around the position, above the light shielding layer, of the a-Si after being converted into the p-Si is, the moreThe TFT mobility characteristics are affected, affecting the final display quality.
Therefore, how to solve the contradiction that the shading layer in the L TPS-AMO L ED display product has different influences on the electrical performance of the TFTs in different areas of the array substrate is a problem which needs to be researched urgently.
Disclosure of Invention
The invention provides a preparation method of an array substrate and the array substrate, wherein the preparation method of the array substrate can well solve the contradiction that a light shielding layer has different influences on the electrical properties of TFTs in different areas of the array substrate, and ensures that the TFT channels on the whole array substrate are uniform and have good electrical properties such as mobility.
In order to achieve the purpose, the invention provides the following technical scheme:
a preparation method of an array substrate comprises the following steps:
forming a first light shielding layer between the fingerprint identification sensor in the display area and an active layer of the TFT above the fingerprint identification sensor, wherein the first light shielding layer is used for shielding the TFT;
forming a second light shielding layer between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor, the second light shielding layer being for shielding infrared rays of the infrared sensor from being irradiated onto the TFT;
the thickness of the first shading layer is smaller than that of the second shading layer.
In the preparation method of the array substrate, the first shading layer and the second shading layer with different thicknesses are arranged, so that the contradiction that the shading layers have different influences on the electrical properties of the TFTs in different areas of the array substrate can be well solved, and the specific process is as follows: and forming a first light shielding layer between the fingerprint identification sensor in the display area and the active layer of the TFT above the fingerprint identification sensor, and forming a second light shielding layer between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor, wherein the thickness of the first light shielding layer is smaller than that of the second light shielding layer. The first light shielding layer is arranged between the active layer and the fingerprint identification sensor, the active layer on the first light shielding layer is shielded by the first light shielding layer, the thickness of the first light shielding layer is smaller, so that the defect area of the edge of the active layer pattern above the first light shielding layer is smaller, the influence of the first light shielding layer on the edge of the active layer pattern above the first light shielding layer is smaller, the related abnormal area is smaller, the defects of a TFT channel are smaller, and the mobility characteristic of the TFT is better; through set up the second light shield layer between active layer and infrared sensor, the thickness of second light shield layer is great, and is better to the effect of sheltering from of the infrared light that infrared sensor sent to be difficult to appear the phenomenon that the infrared light directly hits the TFT channel, make TFT mobility characteristic receive less infrared light influence, thereby be favorable to guaranteeing TFT's threshold voltage's stability, and then reduce the appearance of infrared facula on the display screen.
Therefore, the preparation method of the array substrate can well solve the contradiction that the shading layer has different influences on the electrical properties of the TFTs in different areas of the array substrate, and not only can the edges of the active layer patterns corresponding to the upper part of the fingerprint identification sensor be ensured to relate to smaller abnormal areas, but also the active layer corresponding to the upper part of the infrared sensor can not leak light, so that the channels on the whole TFT are uniform, and the TFT has good electrical properties such as mobility and the like.
Preferably, the first light-shielding layer and the second light-shielding layer are formed by using a double patterning process.
Preferably, the material of the first light shielding layer is molybdenum metal or amorphous silicon; and/or the material of the second shading layer is molybdenum metal or amorphous silicon.
Preferably, the thickness of the first light shielding layer is 50-200nm, and the thickness of the second light shielding layer is more than 220 nm.
Preferably, the process of forming the TFT active layer specifically includes:
and forming buffer layers on the first shading layer and the second shading layer, forming an amorphous silicon layer on the buffer layers, forming a polycrystalline silicon layer on the amorphous silicon layer through an annealing process, and carrying out graphical processing on the polycrystalline silicon layer to form active layers of the TFTs (thin film transistors) positioned on the first shading layer and the second shading layer.
Preferably, forming a buffer layer on the first light-shielding layer and the second light-shielding layer specifically includes:
depositing a silicon nitride layer on the light shielding layer by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the silicon nitride layer is 50-150 nm;
and depositing a silicon dioxide layer on the silicon nitride layer by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the silicon dioxide layer is 100-350 nm.
Preferably, forming an amorphous silicon layer on the buffer layer specifically includes: and depositing an amorphous silicon layer with the thickness of 30-60 nm on the buffer layer by adopting a plasma enhanced chemical vapor deposition method, and heating the amorphous silicon layer for 0.5-3 h at the temperature of 400-450 ℃.
Preferably, the conditions of the excimer laser annealing process are as follows: the laser pulse frequency is 300Hz, the laser overlapping rate is 92% -98%, and the laser pulse width<100ns, a laser scanning speed of 9.6-2.4 mm/s, and a laser energy density of 300-500 mJ/cm2。
In addition, the present invention also provides an array substrate, including a first light shielding layer and a second light shielding layer, wherein:
the first light shielding layer is formed between the fingerprint identification sensor in the display area and an active layer of the TFT above the fingerprint identification sensor and used for shielding the TFT;
the second light shielding layer is formed between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor and is used for shielding the infrared ray of the infrared sensor from irradiating the TFT;
the thickness of the first shading layer is smaller than that of the second shading layer.
In the array substrate, because the thickness of the first light shielding layer is smaller than that of the second light shielding layer and the thickness of the first light shielding layer is smaller, the defect area at the edge of the active layer pattern above the first light shielding layer is smaller, so that the influence of the first light shielding layer on the edge of the active layer pattern above the first light shielding layer is smaller, the related abnormal area is smaller, the defects of a TFT channel are smaller, and the mobility characteristic of the TFT is better; the second shading layer is large in thickness and good in shading effect on infrared light emitted by the infrared sensor, so that the phenomenon that the infrared light directly hits a TFT channel is not prone to occurring, the TFT mobility characteristic is affected by less infrared light, the stability of the threshold voltage of the TFT is guaranteed, and the occurrence of infrared light spots on a display screen is reduced; through having set up the first light shield layer and the second light shield layer of different thickness, can solve the light shield layer well and to the different contradictions of different regional TFT electrical property influence in the array substrate, both guaranteed that the active layer pattern edge that corresponds above the fingerprint identification sensor relates to less abnormal area, guaranteed again that the active layer that corresponds above the infrared sensor can not the light leak to make the channel on the whole TFT even, and have good mobility isoelectrical characteristic, improved the product yield.
Preferably, the thickness of the first light shielding layer is 50-200nm, and the thickness of the second light shielding layer is more than 220 nm.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic distribution diagram of fingerprint recognition sensors and infrared sensors in an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first light-shielding layer and a second light-shielding layer in an array substrate according to an embodiment of the present invention;
icon: 1-a fingerprint recognition sensor; 2-a light-shielding layer; 21-a first light-shielding layer; 22-a second light-shielding layer; 3-an active layer; 4-an infrared sensor; 5-a buffer layer; 6-substrate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, a method for manufacturing an array substrate according to an embodiment of the present invention includes:
step S101, as shown in fig. 4, forming a first light shielding layer 21 between the fingerprint identification sensor 1 in the display area and the active layer 3 of the TFT above the fingerprint identification sensor 1, wherein the first light shielding layer 21 is used for shielding the TFT;
step S102, forming a second light shielding layer 22 between the infrared sensor 4 in the display area and the active layer 3 of the TFT above the infrared sensor 4, wherein the second light shielding layer 22 is used for shielding the infrared ray of the infrared sensor 4 from irradiating the TFT;
in step S103, the thickness of the first light-shielding layer 21 is smaller than that of the second light-shielding layer 22.
In the preparation method of the array substrate, by arranging the light shielding layers 2 with different thicknesses, the contradiction that the light shielding layers 2 have different influences on the electrical properties of the TFTs in different areas in the array substrate can be well solved, and the specific process is as follows: according to step S101, a first light shielding layer 21 is formed between the fingerprint recognition sensor 1 in the display area and the active layer 3 of the TFT above the fingerprint recognition sensor 1, then according to step S102, a second light shielding layer 22 is formed between the infrared sensor 4 in the display area and the active layer 3 of the TFT above the infrared sensor 4, and finally according to step S103, the thickness of the first light shielding layer 21 is smaller than that of the second light shielding layer 22. By arranging the first shading layer 21 between the active layer 3 and the fingerprint identification sensor 1, the active layer 3 on which the first shading layer 21 is positioned is shielded by the first shading layer 21, and the thickness of the first shading layer 21 is smaller, so that the defect area of the edge of the pattern of the active layer 3 above the first shading layer 21 is smaller, the influence of the first shading layer 21 on the edge of the pattern of the active layer 3 above the first shading layer is smaller, the related abnormal area is smaller, the defect of a TFT channel is smaller, and the mobility characteristic of the TFT is better; through set up second light shield layer 22 between active layer 3 and infrared sensor 4, the thickness of second light shield layer 22 is great, and the effect of sheltering from to the infrared light that infrared sensor 4 sent is better to be difficult to appear the phenomenon that the infrared light directly hits the TFT channel, make TFT mobility characteristic receive less infrared light influence, thereby be favorable to guaranteeing TFT's threshold voltage's stability, and then reduce the appearance of infrared facula on the display screen.
Therefore, the preparation method of the array substrate can well solve the contradiction that the shading layer 2 has different influences on the electrical properties of the TFTs in different areas of the array substrate, not only ensures that the pattern edges of the active layer 3 corresponding to the upper part of the fingerprint identification sensor 1 relate to smaller abnormal areas, but also ensures that the active layer 3 corresponding to the upper part of the infrared sensor 4 does not leak light, so that the whole TFT has uniform channels and has good electrical properties such as mobility.
On the basis of the above method for manufacturing the array substrate, in order to conveniently and quickly manufacture the light shielding layer 2, in a preferred embodiment, the first light shielding layer 21 and the second light shielding layer 22 are formed by using a double patterning process.
In the preparation method of the array substrate, firstly, the substrate 6 is pre-cleaned, then a film layer is deposited on the display area of the substrate 6 corresponding to the fingerprint identification sensor 1, then, patterning is performed by a single exposure etching process to form a first light-shielding layer 21, then, a film layer is deposited on the display area of the substrate 6 corresponding to the infrared sensor 4, and is patterned through a one-time exposure etching process to form a second light-shielding layer 22, the first shading layer 21 and the second shading layer 22 with different thicknesses are sequentially prepared in different areas of the substrate 6 through the preparation process, in addition, film layers can be integrally deposited in the display area of the substrate 6, then, patterning is carried out through a one-time exposure etching process to form a first light shielding layer 21, finally, patterning is carried out through the one-time exposure etching process to form a second light shielding layer 22, and the preparation process of the light shielding layer 2 is selected according to the specific practical situation of the array substrate.
The film layer can be deposited by directly adopting a magnetron sputtering mode, the magnetron sputtering mode is used as a physical vapor deposition mode, the film layer can be conveniently and quickly deposited at the corresponding position of the display area of the substrate 6, and the product yield of the film layer is high. Of course, other processes capable of meeting the requirements can be adopted for depositing the film layer. When the patterning process is performed in the exposure etching process, it is required to ensure that the patterns of the first light shielding layer 21 and the second light shielding layer 22 correspond to the position design of the active layer on the upper layer of the array substrate.
Specifically, the material of the first light-shielding layer 21 may be metal molybdenum or amorphous silicon; and/or, the material of the second light shielding layer 22 may be molybdenum metal or amorphous silicon.
In the method for manufacturing the array substrate, the material for manufacturing the first light-shielding layer 21 and the material for manufacturing the second light-shielding layer 22 may be the same, and molybdenum or amorphous silicon may be selected, or other materials capable of satisfying the function may be selected; the material for preparing the first light shielding layer 21 and the material for preparing the second light shielding layer 22 may also be the same, the material for preparing the first light shielding layer 21 may be molybdenum metal or amorphous silicon, the material for preparing the second light shielding layer 22 may be other materials capable of satisfying the function except for molybdenum metal and amorphous silicon, similarly, the material for preparing the second light shielding layer 22 may be molybdenum metal or amorphous silicon, and the material for preparing the first light shielding layer 21 may be other materials capable of satisfying the function except for molybdenum metal and amorphous silicon; the specific material of the first shading layer 21 and the second shading layer 22 can be selected according to the actual situation of the array substrate.
Specifically, the thickness of the first light-shielding layer 21 may be 50-200nm, and the thickness of the second light-shielding layer 22 >220 nm.
In the above method for manufacturing the array substrate, in order to ensure that the thickness of the first light shielding layer 21 is smaller than that of the second light shielding layer 22, the thicknesses of the first light shielding layer 21 and the second light shielding layer 22 are set in the manufacturing method, the setting process may be realized by film deposition or by a patterning process, the thickness of the first light shielding layer 21 may be 50-200nm, and the thickness of the second light shielding layer 22 is greater than 220nm, wherein the thickness of the first light shielding layer 21 may be 50nm, 100nm, 150nm, and 200nm, the thickness of the second light shielding layer 22 may be 230nm, 250nm, 270nm, and 300nm, and the specific thicknesses of the first light shielding layer 21 and the second light shielding layer 22 are set according to the actual situation of the array substrate.
In a preferred embodiment, the process of forming the TFT active layer 3 specifically includes:
forming a buffer layer 5 on the first shading layer 21 and the second shading layer 22, forming an amorphous silicon layer on the buffer layer 5, forming a polycrystalline silicon layer on the amorphous silicon layer through an annealing process, and performing a patterning process on the polycrystalline silicon layer to form the active layer 3 of the TFT on the first shading layer 21 and the second shading layer 22.
In the preparation method of the array substrate, a film layer is deposited on a substrate 6, a first shading layer 21 and a second shading layer 22 are formed through a composition process twice, a buffer layer 5 is formed on the first shading layer 21 and the second shading layer 22, an amorphous silicon layer is formed on the buffer layer 5, the amorphous silicon layer is formed into a polycrystalline silicon layer through an annealing process, and finally the polycrystalline silicon layer is subjected to patterning processing to form the active layer 3 of the TFT positioned on the first shading layer 21 and the second shading layer 22, wherein the patterns of the active layer 3 correspond to the patterns of the first shading layer 21 and the second shading layer 22 respectively, and the active layer 3 can be prepared conveniently and quickly through the method.
Specifically, forming the buffer layer 5 on the first light-shielding layer 21 and the second light-shielding layer 22 specifically includes:
depositing a silicon nitride layer on the light shielding layer 2 by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the silicon nitride layer is 50-150 nm;
and depositing a silicon dioxide layer on the silicon nitride layer by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the silicon dioxide layer is 100-350 nm.
In the preparation method of the array substrate, the buffer layer 5 is deposited by adopting a plasma enhanced chemical vapor deposition method, and the buffer layer 5 is of a double-layer structure SiNx(silicon nitride layer)/SiO2And the (silicon dioxide) film is prepared by depositing a 50-150 nm silicon nitride layer on the light shielding layer 2 and then depositing a 100-350 nm silicon dioxide layer on the silicon nitride layer when the buffer layer 5 is prepared.
In a preferred embodiment, forming an amorphous silicon layer on the buffer layer 5 specifically includes: depositing an amorphous silicon layer with the thickness of 30-60 nm on the buffer layer 5 by adopting a plasma enhanced chemical vapor deposition method, and heating the amorphous silicon layer for 0.5-3 h at the temperature of 400-450 ℃.
In a preferred embodiment, the conditions of the excimer laser annealing process are as follows: the laser pulse frequency is 300Hz, the laser overlapping rate is 92% -98%, and the laser pulse width is wideDegree of rotation<100ns, a laser scanning speed of 9.6-2.4 mm/s, and a laser energy density of 300-500 mJ/cm2。
In the preparation method of the array substrate, the conversion from amorphous silicon to polycrystalline silicon is carried out through the excimer laser annealing process, so that the low-temperature polycrystalline silicon transistor can be manufactured on the flexible substrate 6, and the transistor has good performance stability.
In addition, as shown in fig. 2, the present invention further provides an array substrate, including a first light shielding layer 21 and a second light shielding layer 22, wherein:
the first light shielding layer 21 is formed between the fingerprint identification sensor 1 and the active layer 3 of the TFT above the fingerprint identification sensor 1 in the display area, and the first light shielding layer 21 is used for shielding the TFT;
a second light shielding layer 22 is formed between the infrared sensor 4 in the display region and the active layer 3 of the TFT above the infrared sensor 4, the second light shielding layer 22 for shielding infrared rays of the infrared sensor 4 from being irradiated onto the TFT;
the thickness of the first light-shielding layer 21 is smaller than that of the second light-shielding layer 22.
In the array substrate, because the thickness of the first shading layer 21 is smaller than that of the second shading layer 22, the first shading layer 21 is used for shading the active layer 3 on the first shading layer 21, and the thickness of the first shading layer 21 is smaller, so that the defect area at the edge of the pattern of the active layer 3 above the first shading layer 21 is smaller, the influence of the first shading layer 21 on the edge of the pattern of the active layer 3 above the first shading layer is smaller, the related abnormal area is smaller, the defect of a TFT channel is smaller, and the mobility characteristic of the TFT is better; the thickness of the second shading layer 22 is large, the shading effect on infrared light emitted by the infrared sensor 4 is good, so that the phenomenon that the infrared light directly hits a TFT channel is not easy to occur, the TFT mobility characteristic is influenced by less infrared light, the stability of the threshold voltage of the TFT is favorably ensured, and the occurrence of infrared light spots on a display screen is reduced. Therefore, through the arrangement of the first light shielding layer 21 and the second light shielding layer 22 with different thicknesses, the contradiction that the light shielding layer 2 has different influences on the electrical properties of the TFTs in different areas of the array substrate can be well solved, the fact that the pattern edges of the active layer 3 corresponding to the upper portion of the fingerprint identification sensor 1 relate to small abnormal areas is guaranteed, the fact that the active layer 3 corresponding to the upper portion of the infrared sensor 4 does not leak light is also guaranteed, and therefore the channel on the whole TFT is uniform, and the TFT has good electrical characteristics such as mobility.
Specifically, the thickness of the first light-shielding layer 21 may be 50-200nm, and the thickness of the second light-shielding layer 22 >220 nm.
In the array substrate, in order to ensure that the thickness of the first light shielding layer 21 is smaller than that of the second light shielding layer 22, the thickness of the first light shielding layer 21 may be 50-200nm, and the thickness of the second light shielding layer 22 is greater than 220nm, wherein the thickness of the first light shielding layer 21 may be 50nm, 100nm, 150nm, 200nm, and the thickness of the second light shielding layer 22 may be 230nm, 250nm, 270nm, 300nm, and the specific thicknesses of the first light shielding layer 21 and the second light shielding layer 22 are set according to the actual situation of the array substrate.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A preparation method of an array substrate is characterized by comprising the following steps:
forming a first light shielding layer between the fingerprint identification sensor in the display area and an active layer of the TFT above the fingerprint identification sensor, wherein the first light shielding layer is used for shielding the TFT;
forming a second light shielding layer between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor, the second light shielding layer being for shielding infrared rays of the infrared sensor from being irradiated onto the TFT;
the thickness of the first shading layer is smaller than that of the second shading layer.
2. The production method according to claim 1,
and respectively forming the first shading layer and the second shading layer by adopting a twice composition process.
3. The manufacturing method according to claim 2, wherein the material of the first light shielding layer is molybdenum metal or amorphous silicon; and/or the material of the second shading layer is molybdenum metal or amorphous silicon.
4. A method according to any one of claims 1 to 3, wherein the thickness of the first opacifying layer is 50-200nm and the thickness of the second opacifying layer is >220 nm.
5. The method according to claim 1, wherein the process of forming the TFT active layer specifically comprises:
and forming buffer layers on the first shading layer and the second shading layer, forming an amorphous silicon layer on the buffer layers, forming a polycrystalline silicon layer on the amorphous silicon layer through an annealing process, and carrying out graphical processing on the polycrystalline silicon layer to form active layers of the TFTs (thin film transistors) positioned on the first shading layer and the second shading layer.
6. The manufacturing method according to claim 5, wherein forming a buffer layer on the first light shielding layer and the second light shielding layer specifically includes:
and sequentially depositing a silicon nitride layer and a silicon dioxide layer on the light shielding layer by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the silicon nitride layer is 50-150 nm, and the thickness of the silicon dioxide layer is 100-350 nm.
7. The method according to claim 5, wherein forming an amorphous silicon layer on the buffer layer specifically comprises: and depositing an amorphous silicon layer with the thickness of 30-60 nm on the buffer layer by adopting a plasma enhanced chemical vapor deposition method, and heating the amorphous silicon layer for 0.5-3 h at the temperature of 400-450 ℃.
8. The method for producing according to claim 5, which isCharacterized in that the annealing process is carried out under the following conditions: the laser pulse frequency is 300Hz, the laser overlapping rate is 92% -98%, and the laser pulse width<100ns, a laser scanning speed of 9.6-2.4 mm/s, and a laser energy density of 300-500 mJ/cm2。
9. An array substrate, comprising a first light shielding layer and a second light shielding layer, wherein:
the first light shielding layer is formed between the fingerprint identification sensor in the display area and an active layer of the TFT above the fingerprint identification sensor and used for shielding the TFT;
the second light shielding layer is formed between the infrared sensor in the display area and the active layer of the TFT above the infrared sensor and is used for shielding the infrared ray of the infrared sensor from irradiating the TFT;
the thickness of the first shading layer is smaller than that of the second shading layer.
10. The array substrate of claim 9, wherein the first light shielding layer has a thickness of 50-200nm and the second light shielding layer has a thickness >220 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811275693.XA CN109449118B (en) | 2018-10-30 | 2018-10-30 | Array substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811275693.XA CN109449118B (en) | 2018-10-30 | 2018-10-30 | Array substrate and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109449118A CN109449118A (en) | 2019-03-08 |
| CN109449118B true CN109449118B (en) | 2020-07-31 |
Family
ID=65549016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811275693.XA Active CN109449118B (en) | 2018-10-30 | 2018-10-30 | Array substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109449118B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110399797A (en) * | 2019-06-25 | 2019-11-01 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111653590B (en) * | 2020-05-07 | 2022-08-05 | Oppo（重庆）智能科技有限公司 | Display module assembly, display screen assembly and electronic equipment |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100399151C (en) * | 2006-01-23 | 2008-07-02 | 友达光电股份有限公司 | Display panel structure with shield structure |
| US9836165B2 (en) * | 2014-05-16 | 2017-12-05 | Apple Inc. | Integrated silicon-OLED display and touch sensor panel |
| CN105807521A (en) * | 2016-05-24 | 2016-07-27 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN107886037B (en) * | 2016-09-30 | 2021-11-16 | 北京小米移动软件有限公司 | Display device and electronic apparatus |
| CN106711157B (en) * | 2017-01-23 | 2019-07-02 | 武汉华星光电技术有限公司 | The production method of LTPS array substrate |
| KR102599536B1 (en) * | 2017-01-26 | 2023-11-08 | 삼성전자 주식회사 | Electronic device having a biometric sensor |
| CN107104110B (en) * | 2017-05-24 | 2020-03-10 | 京东方科技集团股份有限公司 | Array substrate, preparation method, display panel and display device |
| CN107527940B (en) * | 2017-08-24 | 2020-01-10 | 京东方科技集团股份有限公司 | Back plate and manufacturing method thereof |
| CN107942555A (en) * | 2017-11-22 | 2018-04-20 | 广东欧珀移动通信有限公司 | Display screen, display screen component and electronic equipment |
-
2018
- 2018-10-30 CN CN201811275693.XA patent/CN109449118B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109449118A (en) | 2019-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109148491B (en) | Array substrate, preparation method thereof and display device | |
| JP6416128B2 (en) | Thin film transistor fabrication method | |
| US9515190B2 (en) | Method for manufacturing polysilicon thin film transistor | |
| CN103123910B (en) | Array base palte and manufacture method, display unit | |
| CN109449118B (en) | Array substrate and preparation method thereof | |
| CN102881571B (en) | Active layer ion implantation method and active layer ion implantation method for thin-film transistor | |
| US8377760B2 (en) | Thin film transistor | |
| TWI556415B (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN105742240B (en) | A kind of manufacturing method of LTPS array substrate | |
| CN104678643B (en) | The production method of display base plate and display panel | |
| WO2017107274A1 (en) | Low-temperature polysilicon thin film transistor and preparation method therefor | |
| CN105575819A (en) | Metal oxide thin film transistor with top gate structure and manufacturing method thereof | |
| CN106505033A (en) | Array base palte and preparation method thereof, display device | |
| WO2016101401A1 (en) | Method for manufacturing low-temperature polycrystalline silicon tft substrate and structure of low-temperature polycrystalline silicon tft substrate | |
| WO2016101400A1 (en) | Method for manufacturing low-temperature polycrystalline silicon tft substrate and structure of low-temperature polycrystalline silicon tft substrate | |
| US20170285381A1 (en) | Array substrate and manufacturing method therefor, and display panel | |
| CN106601754A (en) | Thin film transistor array substrate and preparation method thereof, and display device | |
| CN107046042A (en) | A kind of low temperature polycrystalline silicon backboard and its manufacture method, display device | |
| CN109003943B (en) | Array substrate and preparation method thereof | |
| WO2018133148A1 (en) | Thin-film transistor, manufacturing method thereof, and liquid crystal panel | |
| CN204129400U (en) | A kind of COA substrate and display device | |
| CN107425074B (en) | Thin film transistor, manufacturing method thereof, array substrate and display panel | |
| CN203312302U (en) | Thin film transistor, array substrate and display | |
| US20110001135A1 (en) | Method for manufacturing self-aligned thin-film transistor and structure thereof | |
| JP6040438B2 (en) | Thin film forming substrate and thin film forming method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |