CN109446686B - Method for analyzing logical connection relation between devices in equipment - Google Patents
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- CN109446686B CN109446686B CN201811314561.3A CN201811314561A CN109446686B CN 109446686 B CN109446686 B CN 109446686B CN 201811314561 A CN201811314561 A CN 201811314561A CN 109446686 B CN109446686 B CN 109446686B
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Abstract
The invention provides a method for analyzing the logical connection relation between internal devices of equipment, which is used for analyzing the logical connection relation between the internal devices of embedded equipment and comprises the following steps: drawing a connection relation schematic diagram of devices in the equipment; analyzing the connection relation diagram to generate an equipment description file; and analyzing the connection relation between the internal devices of the equipment according to the equipment description file. The method can display the complete data flow diagram starting from any point in a certain mode in the use of the equipment, and provides certain convenience for work.
Description
Technical Field
The invention relates to the technical field of embedded equipment, in particular to a method for analyzing a logical connection relation between devices in equipment.
Background
For upper software, it is not clear how to connect the inside of the embedded device, and the embedded device is often regarded as a black box. However, in actual use, software personnel and technical support personnel often participate, and certain knowledge of the internal connection relationship of the equipment is needed. The general hardware design drawings are generally large, and the difficulty of interpretation is large for software and technical support personnel, which is not favorable for related personnel to clearly grasp the data flow direction of the equipment.
Disclosure of Invention
The present invention is directed to solve the above problems in the prior art, and provides a method for analyzing a logical connection relationship between devices inside a device, so as to solve the deficiencies in the prior art.
Specifically, an embodiment of the present invention provides a method for analyzing a logical connection relationship between internal devices of an apparatus, where the method is used to analyze a logical connection relationship between internal devices of an embedded apparatus, and the method includes:
drawing a connection relation schematic diagram of devices in the equipment;
analyzing the connection relation diagram to generate an equipment description file;
and analyzing the connection relation between the internal devices of the equipment according to the equipment description file.
As a further improvement of the above technical solution, drawing a connection relationship diagram of the internal device of the device includes using a graphic description language to express the connection relationship diagram of the internal device of the device; the device internal device comprises a board card, a chip, a bus and a connecting line, and the connection relation diagram of the device internal device expressed by adopting a graphic description language comprises the following steps: adopting a board card to represent a board card; representing a chip by adopting nodes with group attributes; representing the bus by adopting nodes without group attributes; the connecting lines are represented by directional lines having edge properties.
As a further improvement of the above technical solution, the drawing of the device internal connection relationship diagram specifically further includes:
analyzing a hardware structure diagram of hardware, and determining a connection line between a bus and a chip;
selecting a drawing tool to draw a schematic diagram of the internal connection relation of the equipment;
determining all bus nodes in each chip, and adding the serial numbers of the buses into the labels of the nodes if a plurality of buses with the same name exist in the chip; generating a group node for all bus nodes of a chip, and setting the label of the node as the name of the chip; if a plurality of chips with the same name are arranged in one board card, the serial number of the chip is added into the label;
and storing the drawn graphs until all the chips of each board card are drawn, wherein the file name is the name of the corresponding board card.
As a further improvement of the above technical solution, the analysis of the connection relation diagram adopts a line-by-line keyword matching analysis.
As a further improvement of the above technical solution, a rule for analyzing the connection relation diagram is as follows:
determining whether the node is a chip node or a bus node according to whether the node has the group attribute;
generating a unique number value of the node in a board card according to the node identifier; the bus nodes in the same group have a subordinate relationship with the group node identifiers on the node identifiers, and the inclusion relationship between the bus nodes and the chip nodes is generated according to the node identifiers;
determining a label value according to the label attribute value of the node;
finding two corresponding bus nodes according to the source attribute and the destination attribute of the edge; and determining whether the edge is a unidirectional edge or a bidirectional edge according to the direction attribute of the edge so as to determine the connection relation of the two nodes.
As a further improvement of the above technical solution, the analyzing a connection relationship between internal devices of the device according to the device description file specifically includes:
generating all chip structures according to the board description file;
generating all bus structures of the corresponding chips and data flow information of the bus structures according to the board card side information;
generating internal connection relations of all board cards of the equipment according to the chip structure and the data stream information;
and analyzing the connection relation between the board cards according to the connectors with the same name between the board cards.
As a further improvement of the above technical solution, the data stream information includes a sending direction and a receiving direction.
As a further improvement of the above technical solution, the method for analyzing a logical connection relationship between devices inside the device further includes: and describing the internal connection relation of the equipment by adopting a dot script language.
As a further improvement of the above technical solution, the method for analyzing a logical connection relationship between devices inside the device further includes: and converting the equipment connection relation described by the dot script language into a picture file by using a dot conversion graph tool.
As a further improvement of the above technical solution, the method for analyzing a logical connection relationship between devices inside the device further includes: and drawing a device internal connection relation sketch by adopting yEd Graph Editor software.
Compared with the prior art, the technical scheme provided by the invention at least has the following beneficial effects: the method can display the complete data flow diagram starting from any point in a certain mode during the use of the equipment, and provides certain convenience for work.
Drawings
Fig. 1 is a schematic flowchart of a method for analyzing a logical connection relationship between devices in an apparatus according to an embodiment of the present invention;
FIG. 2 is a simplified diagram of a motherboard according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a network card according to an embodiment of the present invention;
FIG. 4 is a description file generated by the motherboard according to the embodiment of the present invention;
FIG. 5 is a first half of a description file generated by a network card according to an embodiment of the present invention;
fig. 6 is a second half of a description file generated by the network card according to the embodiment of the present invention;
FIG. 7 is a dot script language of a complete receive path diagram according to an embodiment of the present invention;
FIG. 8 is a diagram of a complete receive path according to an embodiment of the present invention;
FIG. 9 is a dot script language of a complete transmission path diagram according to an embodiment of the present invention;
FIG. 10 is a diagram of a complete transmit path according to an embodiment of the present invention.
Detailed Description
By analyzing a large number of embedded devices, it is concluded that the embedded devices generally have the following characteristics: any one device is composed of 1 or more boards. The board card is connected with the board card through the connector. The board card is composed of a plurality of chips. The chips are connected through buses. Many external buses are led out from the chip. The data flow can be seen as a single connection from bus a through the chip to bus B. The buses of the chip can be divided into three types: a control bus: the control bus is used for control and is used for accessing registers or other contents of the chip. A data bus: the data bus is used for data transmission and is used for information transmission between devices or inside the devices. Control data bus: such as a pci bus, and simultaneously takes control and data functions into consideration.
Example 1
As shown in fig. 1, embodiment 1 of the present invention provides a method for analyzing a logical connection relationship between internal devices of an apparatus, for analyzing a logical connection relationship between internal devices of an embedded apparatus, including:
and S101, drawing a schematic diagram of the connection relation of the internal devices of the equipment.
Drawing a connection relation sketch of the internal device of the equipment comprises the steps of expressing the connection relation sketch of the internal device of the equipment by adopting a graphic description language (graphic); the internal device of the equipment comprises a board card, a chip, a bus and a connecting line, and a connector on the board card is also regarded as a chip; the method for expressing the connection relation sketch of the internal device of the equipment by adopting the graphic description language comprises the following steps: adopting a board card diagram to show a board card; the board card can be represented by one or more diagrams; representing the chip by adopting nodes with group attributes; representing a bus by adopting nodes without group attributes; the connecting lines are represented by directional lines having edge properties.
The drawing of the internal connection relation diagram of the equipment specifically comprises the following steps:
analyzing the hardware structure diagram of the hardware and determining the connection between the bus and the chip.
And selecting a drawing tool to draw a schematic diagram of the internal connection relation of the equipment.
When the drawing tool is used for drawing the sketch of the internal connection relation of the equipment, the file format can be a format generated by any text graphic mark language, such as a graphll language.
The drawing tool can be yEd Graph Editor software.
Determining all bus nodes in each chip, and adding the serial numbers of the buses into the labels of the nodes if a plurality of buses with the same name exist in the chip; generating a group node for all bus nodes of a chip, and setting the label of the node as the name of the chip; if a plurality of chips with the same name are arranged in one board card, the number of the chip is added into the label.
And storing the drawn graphs until all the chips of each board card are drawn, wherein the file name is the name of the corresponding board card.
The following description will be made by taking a test device of a motherboard (motherboard) + network card (network _ card) as an example.
Because there are mainboard and network card, the integrated circuit board number is 2, consequently needs to draw two sketch maps. The schematic drawing of the mainboard is shown in fig. 2, and the schematic drawing of the network card is shown in fig. 3.
The following is a description by taking a mainboard schematic diagram as an example: as shown in FIG. 2, the dashed box is a chip, where "cpu" and "pci _ connector:0" are the names of the chips. The dashed box corresponds to a node with a group attribute in the graph ml. The solid-line box is a bus within the chip, where "pci" is the name of the bus. The solid box corresponds to a node without a group attribute in the graph ml. The dashed box may contain a plurality of solid boxes. I.e. there may be various buses within a chip. Arrows indicate the relationship between buses. I.e. corresponding to an edge in the graph ml map.
And S102, analyzing the connection relation diagram to generate an equipment description file.
And analyzing the connection relation diagram by adopting line-by-line keyword matching analysis.
The rule for analyzing the connection relation diagram is as follows:
and determining whether the node is a chip node or a bus node according to whether the node has the group attribute.
< node id = "n1" yfiles. Foldertype = "group" >: and numbering the node according to the node id, wherein the node with the group attribute is the node of the chip.
Generating a unique number value of the node in a board card according to the node identifier; the bus nodes in the same group have an affiliation with the group node identifiers on the node identifiers, and the inclusion relationship between the bus nodes and the chip nodes is generated according to the node identifiers.
Bus nodes within the same group have an affiliation in node identification with the identification of the group node. For example: the bus node within the same group (i.e., the group node) is identified as n0, then the nodes of this group without buses are identified as n0: nx, x being a number. The node identifiers of the group without the bus adopt a combination of a group node identifier n0 plus an identifier name nx.
< node id = "n1:: n5" >: obtaining the identifier of the node, which is a bus node; determining from the node id whether it is in relationship with a chip node; the numbering of the nodes is required to reflect the relationship with the chip nodes.
And determining the label value of the node according to the label attribute value of the node.
NodeLabel … test NodeLabel >: and obtaining the table of the node.
And finding out two corresponding bus nodes according to the source attribute and the destination attribute of the edge.
< edge id = "e3" source = "n2:: n1" target = "n3:: n0" >: this is the key of the edge, and the edge is determined from which bus node to which bus node by the source and target, and the information of the edge is recorded.
And determining whether the edge is a unidirectional edge or a bidirectional edge according to the direction attribute of the edge so as to determine the connection relation of the two nodes.
Arrows source = "none" target = "standard"/>: an attribute representing an edge, and a bidirectional edge if neither edge is a "none". If only one side is a none, then it is a unidirectional side.
And obtaining the chip of the board card, all buses under the chip and all edges on the board card according to the keywords. After the information is stored, the device description file is generated.
The above description is continued by taking as an example the testing device of one motherboard (motherboard) + network card (network _ card).
And analyzing the file corresponding to the diagram to generate an equipment description file. The corresponding motherboard description file of fig. 2 is shown in fig. 4. The network card description file corresponding to fig. 3 is shown in fig. 5 and fig. 6.
The analysis method is as follows: the solid line boxes in the figure generate the bus data structure: struct cm _ desc _ chip _ bus xxx __ yyy __ zzz. There are member variables of the bus type (bus), the bus number (postList), the number in the figure (graph id), which chip (graph cid) it belongs to, etc. (where xxx denotes the name of the board, yyy denotes the name of the chip, and zzz denotes the name of the bus)
The dashed boxes in the figure generate the chip data structure: struct cm _ desc _ chip xxx __ yyy. Member variables including the name of the chip (chip _ desc), the chip number (chip _ post), the number in the figure (graph id), and which buses (chip _ bus) there are. (wherein xxx represents the name of the board and yyyy represents the name of the chip)
The arrows in the figure then produce all the edges of the board: struct cm _ desc _ edge xxx _ edges [ ]. Each edge contains two members, a head (srcId) and a tail (tgtId). srcId and tgtId are graphId for the bus (where xxx represents the card name)
And finally, producing a board card data structure: struct cm _ desc _ board xxx. It has three members: the name of the board (board _ desc), the chip of the board (chip _ list) and the edge of the board (edges). (wherein xxx indicates the name of the board)
In one drawing, chip node and bus node numbers must be unique, so in this embodiment, the calculation method for converting node id into node number may be: the description of the node id is two, nx and Nx:: ny, and the description of the node id is analyzed to obtain x and y (the default value of the former y is-1), and the number of the node is finally obtained, wherein ((x) < < 8) | (((y) > = 0).
And S103, analyzing the connection relation between the internal devices of the equipment according to the equipment description file.
Analyzing the connection relationship among the internal devices of the equipment according to the equipment description file specifically comprises the following steps:
generating all chip structures according to the board description file; generating all bus structures of the corresponding chips and data flow information of the bus structures according to the board card side information; the data flow information comprises a sending direction and a receiving direction; generating internal connection relations of all board cards of the equipment according to the chip structure and the data stream information; and analyzing the connection relation between the boards according to the connectors with the same name between the boards.
If a board card can be inserted into multiple slots on the device, the board card is a slot-variable board card, for example: the network card (network _ card) is a variable slot card; the name of the connector of the network card is not numbered, and the name of the connector of the network card is pci _ connector; if a board card can only be inserted into a certain fixed slot position, the board card is a fixed slot position board card, for example: the motherboard (monoboard) is a fixed slot board card, and the name of the connector of the motherboard needs to be provided with a position number, the name of the connector of the motherboard is pci _ connector:0, and 0 is the position number. The following three conditions are satisfied by the connector of two boards: the names of the connectors are the same; the position number of the connector of the fixed slot position board card is required to be equal to the slot position number of the variable slot position board card; the number of buses and the location of the buses contained in the two connectors must be the same to match.
And describing the internal connection relation of the equipment by adopting a dot script language. And converting the equipment connection relation described by the dot script language into a picture file by using a dot conversion graph tool.
The above description is continued by taking as an example the testing device of one motherboard (motherboard) + network card (network _ card).
And generating the device connection relation according to the description file. The device comprises a mainboard and a network card, and the connection relation of the whole device is established after a basic data structure is established for the two card (the mainboard and the network card). The method comprises the following specific steps:
A. all chip nodes are established according to the member chip _ list in the description board structure.
B. All bus nodes below the chip are established according to edges (edges) in the board structure and the chip node. The bus nodes are in a bidirectional linked list structure.
The bus nodes have members such as bus types, bus global numbers and the like. The bus global number is the devBusNodeId number, and the devBusNodeId is obtained according to the information such as the slot position number of the board card, the bus position, the node number and the like, and is globally unique in the whole equipment.
The bus node (busA) also needs to set its receiving bus node and the previous transmitting bus node in the data flow. If there is a data stream
The receiving node of the busA is the busB (busB ← busA) and the previous-stage sending node of the busA is the busB (busB → busA). The data flow mentioned here means that the data flow from the CPU is the transmission direction and the data flow to the CPU is the reception direction.
C. After the basic data structures of the two boards are established, they need to be connected through the connector pci _ connector.
Both the monoteboard and the network _ card have the same connector pci _ connector chip. The pci _ connector chip in the network _ card is not numbered, which means that the network _ card can be inserted into any device that satisfies its condition. In the example where only a summary of pci is used on both connectors pci _ connectors, the matching condition is satisfied and both can be connected.
Connecting the two connectors, namely establishing the relationship between a pci bus node (named as network _ card _ pci _ connector __ pci) in a pci _ connector chip in the network _ card and a pci bus node (named as single _ pc _ connector _0__ pci) in a pci _ connector chip in the single board: the previous sending node of the network _ card _ pci _ connector __ pci is the single board _ pci _ connector _0__ pci (single board _ pci _ connector _0__ pci → network _ card _ pci _ connector __ pci); the receiving node of network _ card _ pci _ connector __ pci is single _ pci _ connector _0__ pci (single _ pci _ connector _0__ pci ← network _ card _ pci _ connector __ pci).
After the connection relationship is established, because the bus nodes are in a linked list structure, the receiving data flow or the sending data flow of a complete path from any bus node can be tracked.
Starting from the chip bus of the external chip in the example, a complete receive path and transmit path data stream is obtained.
Starting from network _ card _ external __ copper, obtaining that the receiving node of the bus node is network _ card _ phy __ mdi, starting from network _ card _ phy __ mdi, obtaining the receiving node of the bus node until a certain bus node has no receiving node. A complete receive path is described in the dot script language, as shown in fig. 7, and the tool for dot transforming the graph is used to generate the png graph, as shown in fig. 8.
The method comprises the steps of starting from network _ card _ external __ copper to obtain the previous-stage sending node of the bus node as network _ card _ phy __ mdi, starting from network _ card _ phy __ mdi to obtain the previous-stage sending node of the bus node until a certain bus node has no previous-stage sending node. A complete transmission path is described in the dot script language, as shown in fig. 9, and a png graph is generated with the dot drawing tool, as shown in fig. 10.
The method and the device for generating the internal logic connection relation of the equipment finally generate the board card connection sketch drawn according to a certain rule. And the receiving direction and the sending direction of the data graph can be traced from the bus of any chip in the equipment. The method is beneficial for software developers and technicians to know the internal logical connection relation of the equipment in real time in the running process of the equipment. More functions can be expanded on the generated internal logic connection relation. If the detection function is implemented on each node, all buses of all chips of the equipment can be detected, the running states of all devices in the equipment are obtained, and finally the running states can be displayed in a graph mode.
Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules.
The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (8)
1. A method for analyzing the logic connection relationship between internal devices of an equipment is used for analyzing the logic connection relationship between the internal devices of an embedded equipment, and is characterized by comprising the following steps:
drawing a connection relation schematic diagram of devices inside the equipment;
analyzing the connection relation diagram to generate an equipment description file;
analyzing the connection relation between the internal devices of the equipment according to the equipment description file;
drawing a connection relation sketch of the internal device of the equipment comprises the step of expressing the connection relation sketch of the internal device of the equipment by adopting a graphic description language; the device internal device comprises a board card, a chip, a bus and a connecting line, and the connection relation diagram of the device internal device expressed by adopting a graphic description language comprises the following steps: adopting a board card diagram to show a board card; representing a chip by adopting nodes with group attributes; representing the bus by adopting nodes without group attributes; representing the connecting line by a directional straight line with edge attribute;
analyzing a hardware structure diagram of hardware, and determining a connection line between a bus and a chip;
selecting a drawing tool to draw a schematic diagram of the internal connection relation of the equipment;
determining all bus nodes in each chip, and adding the serial numbers of the buses into the labels of the nodes if a plurality of buses with the same name exist in the chip; generating a group node for all bus nodes of a chip, and setting the label of the node as the name of the chip; if a plurality of chips with the same name are arranged in one board card, the serial number of the chip is added into the label;
and storing the drawn graphs until all the chips of each board card are drawn, wherein the file name is the name of the corresponding board card.
2. The method according to claim 1, wherein the analysis of the connection diagram is performed by a line-by-line keyword matching analysis.
3. The method for analyzing logical connection relationships between devices inside equipment according to claim 2, wherein a rule for analyzing the connection relationship diagram is as follows:
determining whether the node is a chip node or a bus node according to whether the node has the group attribute;
generating a unique number value of the node in a board card according to the node identifier; the bus nodes in the same group have subordination relation with the group node identification on the node identification, and the inclusion relation between the bus nodes and the chip nodes is generated according to the node identification;
determining a label value according to the label attribute value of the node;
finding two corresponding bus nodes according to the source attribute and the destination attribute of the edge; and determining whether the edge is a unidirectional edge or a bidirectional edge according to the direction attribute of the edge so as to determine the connection relation of the two nodes.
4. The method for analyzing the logical connection relationship between the internal devices of the device according to claim 1, wherein analyzing the connection relationship between the internal devices of the device according to the device description file specifically includes:
generating all chip structures according to the board card description file;
generating all bus structures of the corresponding chips and data flow information of the bus structures according to the board card side information;
generating internal connection relations of all board cards of the equipment according to the chip structure and the data stream information;
and analyzing the connection relation between the board cards according to the connectors with the same name between the board cards.
5. The method according to claim 4, wherein the data flow information includes a transmission direction and a reception direction.
6. The method for analyzing logical connection relationship between devices inside a device according to claim 1, wherein the method for analyzing logical connection relationship between devices inside a device further comprises: and describing the internal connection relation of the equipment by adopting a dot script language.
7. The method for analyzing logical connection relationship between internal devices of an apparatus according to claim 6, wherein the method for analyzing logical connection relationship between internal devices of an apparatus further comprises: and converting the equipment connection relation described by the dot script language into a picture file by using a dot conversion graph tool.
8. The method for analyzing logical connection relationship between devices inside a device according to claim 1, wherein the method for analyzing logical connection relationship between devices inside a device further comprises: and drawing a device internal connection relation sketch by adopting yEd Graph Editor software.
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| CN1862545A (en) * | 2005-12-28 | 2006-11-15 | 华为技术有限公司 | Method and system for drawing schematic diagram design document |
| CN103208857A (en) * | 2013-03-19 | 2013-07-17 | 国电南瑞科技股份有限公司 | Five-prevention interlocking topology analysis method based on substation scalable vector graphics (SVG) primary connection diagram |
| KR20150031135A (en) * | 2013-09-13 | 2015-03-23 | 한국기계연구원 | Method of analysiing reliability using 3d scenegraph |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1862545A (en) * | 2005-12-28 | 2006-11-15 | 华为技术有限公司 | Method and system for drawing schematic diagram design document |
| CN103208857A (en) * | 2013-03-19 | 2013-07-17 | 国电南瑞科技股份有限公司 | Five-prevention interlocking topology analysis method based on substation scalable vector graphics (SVG) primary connection diagram |
| KR20150031135A (en) * | 2013-09-13 | 2015-03-23 | 한국기계연구원 | Method of analysiing reliability using 3d scenegraph |
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