CN109428713A - The method of circuit structure and acquisition PUF value for PUF - Google Patents
The method of circuit structure and acquisition PUF value for PUF Download PDFInfo
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- CN109428713A CN109428713A CN201710769656.3A CN201710769656A CN109428713A CN 109428713 A CN109428713 A CN 109428713A CN 201710769656 A CN201710769656 A CN 201710769656A CN 109428713 A CN109428713 A CN 109428713A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- Computer Networks & Wireless Communication (AREA)
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- Static Random-Access Memory (AREA)
Abstract
The invention discloses a kind of circuit structure for PUF and the methods for obtaining PUF value.The circuit structure includes: transistor array, including n × m transistor；The first electrode of each transistor is suitable for being applied supply voltage；First decoder, including n the first signal ends, i-th of first signal ends connect the grid of the transistor of the i-th row by i-th wordline；First decoder selects the transistor of any a line and the row transistor is connected；Second decoder, including m second signal end, j-th of second signal end connect the second electrode of the transistor of jth column by j-th strip bit line；Second decoder selects two transistors in by the transistor of the row of selection conducting, obtains the output voltage of the two transistors, and the two output voltages are delivered to comparing unit；And comparing unit obtains PUF value according to comparison result for comparing the size of the two output voltages.Present invention decreases the areas of circuit structure.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of to be used for PUF (Physical Unclonable
Function, the unclonable function of physics) circuit structure and obtain PUF value method.
Background technique
Currently, the best secret key of a device for identification, is exactly to utilize the unclonable function of so-called physics
(PUF) key being calculated, the physical characteristic that PUF is arbitrarily generated during being manufactured based on device production, due in process
Small uncontrollable random variation, so that these features become the unique feature of each device.Although these variation nothings
Method predefines or control, but if they can be measured or sufficiently stable in sufficiently low noise, they can be with
For PUF.
These measurements can be used for the distinctive private cipher key of the construction device, and PUF is that the bioassay of no life device is special
Sign, it is similar with the fingerprint of the mankind or retina.As by identical DNA " manufacture " the but twins with unique fingerprint, use
Identical source technique manufacture lifeless object thus some PUF are also unique.Due to unavoidable small change
Change, to a certain extent, perfect clone is practically impossible, and PUF is exactly excellent to provide the fact that be utilized
Gesture.
Currently, in some cases, can use traditional SRAM (Static Random Access Memory, static state
Random access memory) or latch as PUF.But as device becomes small, the yield of chip is also increasing, because
This is with the increase of quantity, and traditional SRAM (or latch) PUF quantity also ramps, and each SRAM includes six
Transistor (each latch includes four transistors), so as to cause the increase of PUF area specific gravity.
Summary of the invention
The inventors found that above-mentioned exist in the prior art problem, and therefore it is directed in described problem at least
One problem proposes a kind of new technical solution.
According to the first aspect of the invention, a kind of circuit structure for the unclonable function PUF of physics is provided, is wrapped
Include: transistor array, the transistor array include n × m transistor, and wherein n and m is positive integer, and n >=1, m >=2；Its
In each transistor first electrode be suitable for be applied supply voltage；First decoder comprising n the first signals
End, wherein i-th of first signal end connects the grid of the transistor of the i-th row by i-th wordline, wherein 0≤i≤n-
1, and i is integer；First decoder is used to select the transistor of any a line and the row transistor is connected；Second
Decoder comprising m second signal end, wherein j-th of second signal end connects jth column by j-th strip bit line
The second electrode of transistor, wherein 0≤j≤m-1, and j is integer；Second decoder is used for by the institute of selection conducting
Two transistors of selection in capable transistor are stated, and are obtained in the two transistors by corresponding two second signal ends
Second output voltage of the second electrode of the first output voltage of the second electrode of first transistor and second transistor,
And first output voltage and second output voltage are delivered to comparing unit；And the comparing unit, for than
Compared with the size of the first output voltage and the second output voltage, and PUF value is determined according to comparison result and exports the PUF value.
In one embodiment, if the comparing unit judges that first output voltage is greater than or equal to described second
Output voltage, it is determined that PUF value is 1；If judging, first output voltage is less than second output voltage, it is determined that PUF
Value is 0.
In one embodiment, the transistor is NMOS transistor, and the first electrode is drain electrode, second electricity
Extremely source electrode；Alternatively, the transistor is PMOS transistor, the first electrode is source electrode, and the second electrode is drain electrode.
In one embodiment, second decoder includes: the first output end and second output terminal；It is described relatively more single
Member includes: the first amplifier, the second amplifier and comparator；First output end of second decoder is connected to described
The output end of the input terminal of one amplifier, first amplifier is connected to the first input end of the comparator；Described second
The second output terminal of decoder is connected to the input terminal of second amplifier, and the output end of second amplifier is connected to
Second input terminal of the comparator；Wherein, first amplifier receives the first output electricity from second decoder
Pressure, by output after first output voltage amplification to the comparator；Second amplifier connects from second decoder
Second output voltage is received, by output after second output voltage amplification to the comparator；The comparator compare by
The size of amplified first output voltage and second output voltage after being amplified is determined according to comparison result
PUF value simultaneously exports the PUF value.
In one embodiment, first amplifier to the amplification factor of first output voltage received with
Second amplifier is equal to the amplification factor of second output voltage received.
In one embodiment, the amount of bits for determining the circuit structure according to the transistor array is
In one embodiment, the circuit structure further include: logic control element, the control with second decoder
End connection processed, for controlling the second decoder selection and institute to second decoder output the first control encoded signal
Corresponding two transistors of the first control encoded signal are stated to obtain corresponding first output voltage and the second output voltage.
In one embodiment, the logic control element is for receiving digitally encoded signal, and by the digital coding
Signal is converted to the first control encoded signal, and the first control encoded signal is output to second decoder.
In one embodiment, the control of the second control output end of the logic control element and first decoder
End connection processed；The logic control element is also used to export the second control encoded signal to first decoder, described in control
First decoder selects a row transistor and the row transistor is connected.
In an embodiment of the present invention, a kind of circuit structure for PUF is provided.In the circuit structure, each ratio
Special unit only needs a transistor, compared with traditional SRAM PUF circuit in the prior art or latch PUF circuit, this
The circuit structure of invention can be substantially reduced the area of PUF.
According to the second aspect of the invention, a kind of side that PUF value is obtained using foregoing circuit structure is provided
Method characterized by comprising supply voltage is applied to the first electrode of each of the transistor array transistor；
The transistor of any a line is selected using first decoder and the row transistor is connected；Utilize second decoding
Device selects two transistors in by the transistor of the row of selection conducting, and obtains first in the two transistors
Second output voltage of the second electrode of the first output voltage of the second electrode of transistor and second transistor, and by institute
It states the first output voltage and second output voltage is delivered to comparing unit；And it is relatively more described using the comparing unit
The size of first output voltage and second output voltage, and PUF value is determined according to comparison result and exports the PUF value.
In one embodiment, if the step of determining PUF value according to comparison result includes: that first output voltage is big
In or equal to second output voltage, it is determined that PUF value is 1；If first output voltage is less than the second output electricity
Pressure, it is determined that PUF value is 0.
In one embodiment, it is selected in by the transistor of the row of selection conducting using second decoder
The step of two transistors includes: to be controlled using logic control element to second decoder output the first control encoded signal
It is defeated to obtain corresponding first to make the second decoder selection two transistors corresponding with the first control encoded signal
Voltage and the second output voltage out.
In one embodiment, encoded signal is controlled to second decoder output first using logic control element
The step of include: that the logic control element receives digitally encoded signal, and the digitally encoded signal is converted to the first control
The first control encoded signal is output to second decoder by encoded signal processed.
In one embodiment, the transistor of any a line is selected using first decoder and make the row crystal
The step of pipe is connected includes: to be controlled using the logic control element to first decoder output the second control encoded signal
First decoder is made to select a row transistor and the row transistor is connected.
By the above method, the method for obtaining PUF is realized using the circuit structure of the embodiment of the present invention.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and
Its advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes the embodiment of the present invention, and is used for together with the description
Explain the principle of the present invention.
The present invention can be more clearly understood according to following detailed description referring to attached drawing, in which:
Figure 1A is the circuit structure diagram for schematically showing the SRAM of the PUF with one embodiment in the prior art.
Figure 1B is the circuit structure diagram for schematically showing the SRAM of the PUF with another embodiment in the prior art.
Fig. 2A is the circuit structure diagram for schematically showing latch in the prior art (latch).
Fig. 2 B is the circuit structure diagram for schematically showing the latch of the PUF with one embodiment in the prior art.
Fig. 2 C is the circuit structure for schematically showing the latch of the PUF with another embodiment in the prior art
Figure.
Fig. 3 is to schematically show the electrical block diagram according to an embodiment of the invention for PUF.
Fig. 4 is the connection figure for schematically showing the circuit structure according to an embodiment of the invention for PUF.
Fig. 5 is the connection figure for schematically showing the circuit structure in accordance with another embodiment of the present invention for PUF.
Fig. 6 schematically shows the circuit connection diagram of comparing unit according to an embodiment of the invention.
Fig. 7 is the testing result schematic diagram shown using the circuit structure of one embodiment of the present of invention.
Fig. 8 is the flow chart for showing the method that PUF value is obtained using circuit structure according to an embodiment of the invention.
Specific embodiment
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
Simultaneously, it should be appreciated that for ease of description, the size of various pieces shown in attached drawing is not according to reality
What the proportionate relationship on border was drawn.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to this hair
Bright and its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain item exists
It is defined in one attached drawing, then in subsequent attached drawing does not need that it is further discussed.
Figure 1A is the circuit structure diagram for schematically showing the SRAM of the PUF with one embodiment in the prior art.Figure
1B is the circuit structure diagram for schematically showing the SRAM of the PUF with another embodiment in the prior art.Here SRAM
Indicate a bit cell of the circuit structure of SRAM PUF.As shown in FIG. 1A and 1B, SRAM includes: two PMOS (P-
Channel Metal Oxide Semiconductor, P-channel metal-oxide-semiconductor) transistor P1 and P2 be (as PU
(Pull Up, pull-up) transistor) and two NMOS (N-channel Metal Oxide Semiconductor, N ditches
Road metal-oxide semiconductor (MOS)) transistor N1 and N2 (as PD (Pull Down, drop-down)).Those skilled in the art should manage
Solution, SRAM further includes two PG (Pass Gate, pass through door) transistor, and only Figure 1A and Figure 1B are not shown.As shown in Figure 1A,
In the absolute value of the threshold voltage of P1 | Vtp1| the absolute value of the threshold voltage greater than P2 | Vtp2| in the case where, the number of node OUT
According to for " 0 ", and the data of another node OUTB are " 1 ", and in this case, which exports a PUF value, such as can
Think 1.As shown in Figure 1B, in the absolute value of the threshold voltage of P1 | V 'tp1| the absolute value of the threshold voltage less than P2 | V 'tp2|
In the case where, the data of node OUT are " 1 ", and the data of another node OUTB are " 0 ", in this case, the SRAM
Another PUF value is exported, such as can be 0.
Fig. 2A is the circuit structure diagram for schematically showing latch in the prior art (latch).Fig. 2 B is schematic
Ground shows the circuit structure diagram of the latch of the PUF with one embodiment in the prior art.Fig. 2 C is to schematically show now
There is the circuit structure diagram of the latch of the PUF in technology with another embodiment.Here latch indicates latch PUF
Circuit structure a bit cell.As shown in Fig. 2A, Fig. 2 B and Fig. 2 C, there are two phase inverters 21 and 22 for the latch.The
One phase inverter 21 may include a PMOS transistor P1 and a NMOS transistor N1 (not shown), and second anti-
Phase device 22 may include a PMOS transistor P2 and a NMOS transistor N2 (not shown).As shown in Figure 2 A, exist
The absolute value of the threshold voltage of the PMOS transistor P1 of first phase inverter | Vtp1| more than or equal to second phase inverter
The absolute value of the threshold voltage of PMOS transistor P2 | Vtp2| in the case where, the data of node OUT are " -1 ", and another node
The data of OUTB are " -0 ".It should be noted that the negative sign of " -1 " and " -0 " here is merely to other states (Fig. 2 B
With the state of Fig. 2 C) it distinguishes, might not truly there be the negative sign.In fact, generally occur in the prior art Fig. 2 B and
State shown in fig. 2 C.As shown in Figure 2 B, in the absolute value of the threshold voltage of the PMOS transistor P1 of first phase inverter |
Vtp1| the absolute value of the threshold voltage less than the PMOS transistor P2 of second phase inverter | Vtp2| in the case where, node OUT's
Data are " 0 ", and the data of another node OUTB are " 1 ".In this case, which exports a PUF value, example
It such as can be 0.As shown in Figure 2 C, in the absolute value of the threshold voltage of the PMOS transistor P1 of first phase inverter | Vtp1| it is remote
The absolute value of threshold voltage greater than the PMOS transistor P2 of second phase inverter | Vtp2| in the case where, the data of node OUT
For " 1 ", and the data of another node OUTB are " 0 ".In this case, which exports another PUF value, such as
It can be 1.
As device becomes small, the yield of chip is also increasing, therefore with the increase of quantity, traditional SRAM
Or the PUF quantity of latch also ramps, and each SRAM includes six transistors, each latch may include
Four transistors, so as to cause the increase of PUF area specific gravity.
Fig. 3 is to schematically show the electrical block diagram according to an embodiment of the invention for PUF.
As shown in figure 3, the circuit structure may include transistor array 30.The transistor array 30 may include n × m
A transistor, wherein n and m is positive integer, and n >=1, m >=2.Wherein the first electrode of each transistor is suitable for being applied power supply
Voltage.In description below, the transistor array will be described in detail in conjunction with Fig. 4 or Fig. 5.In this embodiment, each crystal
Pipe can be used as a bit cell.
As shown in figure 3, the circuit structure can also include the first decoder 31.First decoder 31 may include n
First signal end (is not shown) in Fig. 3.Wherein, i-th of first signal end connects the transistor of the i-th row by i-th wordline
Grid, wherein 0≤i≤n-1, and i is integer.First decoder is used to select the transistor of any a line and makes this
Row transistor conducting, such as make the grid of the row transistor be applied grid voltage so that the row transistor turns.
As shown in figure 3, the circuit structure can also include the second decoder 32.Second decoder may include m the
Binary signal end (is not shown) in Fig. 3.Wherein, the transistor that j-th of second signal end is arranged by j-th strip bit line connection jth
Second electrode, wherein 0≤j≤m-1, and j is integer.Second decoder is used for by the crystal of the row of selection conducting
Two transistors are selected in pipe, and first crystal in the two transistors is obtained by corresponding two second signal ends
Second output voltage of the second electrode of the first output voltage of the second electrode of pipe and second transistor, and by this first
Output voltage and second output voltage are delivered to comparing unit 33.
As shown in figure 3, the circuit structure can also include comparing unit 33.The comparing unit 33 is defeated for comparing first
The size of voltage and the second output voltage out, and PUF value is determined according to comparison result and exports the PUF value.In one embodiment
In, if the comparing unit 33 judges that the first output voltage is greater than or equal to the second output voltage, it is determined that PUF value is 1；If sentencing
The first output voltage break less than the second output voltage, it is determined that PUF value is 0.
Since in the fabrication process, each transistor will not be identical with another transistor, therefore can use this
The physical characteristic of a little transistors obtains PUF, for example, after transistor is applied grid voltage to conducting, these transistors
Conducting resistance it is not exactly the same, therefore after the first electrode of transistor (such as drain electrode or source electrode) applies supply voltage,
Second electrode (such as source electrode or drain electrode) will obtain output voltage, these output voltages are not completely equivalent, in this way in quilt
It selects arbitrarily to select two transistors in the transistor of the row of conducting, compares the big of the output voltage of the two transistors
It is small, it may thereby determine that PUF value.
In an embodiment of the present invention, a kind of circuit structure for PUF is provided.In the circuit structure, each ratio
Special unit only needs a transistor, and each bit cell needs are made of 6 transistors in traditional SRAM PUF circuit,
Each bit cell needs 4 transistors compositions in traditional latch PUF circuit, therefore circuit structure of the invention can be with
It is substantially reduced the area of PUF.
In one embodiment, as shown in figure 3, the circuit structure can also include logic control element 34.The logic control
First control output end of unit 34 processed is connect with the control terminal of the second decoder 32.The logic control element can be used for
Second decoder 32 output the first control encoded signal controls second decoder 32 selection and the first control encoded signal
Corresponding two transistors obtain corresponding first output voltage and the second output voltage.For example, the logic control element
34 can be used for receiving digitally encoded signal (such as being properly termed as the first digitally encoded signal), and by the digitally encoded signal
The first control encoded signal is converted to, which is output to the second decoder.
In one embodiment, the control of the second control output end of the logic control element 34 and the first decoder 31
End connection.The logic control element 34 can be also used for exporting the second control encoded signal to first decoder 31, and control should
First decoder 31 selects a row transistor and the row transistor is connected.For example, the logic control element 34 can be used for
Another digitally encoded signal (such as being properly termed as the second digitally encoded signal) is received, and the digitally encoded signal is converted to
The second control encoded signal is output to the first decoder by the second control encoded signal.
Fig. 4 is the connection figure for schematically showing the circuit structure according to an embodiment of the invention for PUF.Such as
Shown in Fig. 4, which includes transistor array 301, which is transistor array 30 shown in Fig. 3
One specific embodiment.In this embodiment, as shown in figure 4, the transistor can be NMOS transistor, wherein should
The first electrode of NMOS transistor is drain electrode, and the second electrode of the NMOS transistor is source electrode.
As shown in figure 4, the transistor array 301 may include n × m NMOS transistor, wherein n and m is positive integer,
And n >=1, m >=2.Wherein the drain electrode (i.e. first electrode) of each NMOS transistor is suitable for being applied supply voltage.With NMOS crystalline substance
For body pipe 41, the drain electrode 411 of the NMOS transistor 41 is suitable for being applied supply voltage (power).In this embodiment, often
A NMOS transistor can be used as a bit cell.The transistor array can reduce the area of PUF.
In one embodiment, the amount of bits for determining the circuit structure according to transistor array isThe bit
Quantity can be the quantity of PUF value.Since in actual production, the quantity of m is bigger, such as it can be 8,10 or more
It is multiple etc., therefore (traditional circuit is according to unit number to the amount of bits of SRAM PUF circuit structure compared to the prior art
Measure to determine amount of bits, such as the amount of bits of the circuit structure with n × m sram cell is n × m), such
In the case of, the amount of bits of circuit structure of the invention can dramatically increase, and obtain bit same as the prior art in this way
In the case where quantity, the quantity of bit cell required for the present invention is less, and circuit area is also smaller.Therefore, the present invention in addition to
Area can be reduced, amount of bits can also be increased, in other words, the present invention effectively can significantly promote unit area can
The amount of bits of generation.
As shown in figure 4, the circuit structure can also include the first decoder 31.First decoder 31 may include n
First signal end 311.Wherein, i-th of first signal ends 311iThe grid of the transistor of the i-th row is connected by i-th wordline,
In 0≤i≤n-1, and i be integer.For example, the 0th the first signal end 3110Pass through the 0th article of wordline WL0Connect the 0th row
The grid (such as grid 413 of NMOS transistor 41) of NMOS transistor.In another example the 1st the first signal end 3111Pass through
1 wordline WL1Connect the grid of the NMOS transistor of the 1st row.In another example (n-1)th the first signal end 311n-1Pass through n-th-
1 wordline WLn-1Connect the grid of the NMOS transistor of the (n-1)th row.First decoder 31 is for selecting any a line
NMOS transistor and make the grid of the row NMOS transistor be applied grid voltage so that the row transistor turns.Example
Such as, which NMOS transistor of the first decoder 31 selection, just by the first signal end 311 of the corresponding row transistor to
Corresponding wordline output grid voltage (such as can be greater than or equal to threshold voltage of the grid (for NMOS transistor, the grid
Pole threshold voltage be positive voltage) positive voltage), so that the transistor turns of the row.
As shown in figure 4, the circuit structure can also include the second decoder 32.Second decoder 32 may include m
Second signal end 322.Wherein, the NMOS transistor that j-th of second signal end 322 is arranged by j-th strip bit line connection jth
Source electrode (i.e. second electrode), wherein 0≤j≤m-1, and j is integer.For example, the 0th second signal end 3220Pass through the 0th article
Bit line BL0Connect the source electrode (such as source electrode 412 of NMOS transistor 41) of the NMOS transistor of the 0th column.In another example the 1st
Binary signal end 3221Pass through the 1st article of bit line BL1Connect the source electrode of the NMOS transistor of the 1st column.In another example m-1 second letter
Number end 322m-1Pass through the m-1 articles bit line BLm-1Connect the source electrode of the NMOS transistor of m-1 column.Second decoder 32 may be used also
To include: the first output end 326 and second output terminal 328.Second decoder 32 by first output end 326 and this
Two output ends 328 are connected with comparing unit 33.In addition, second decoder 32 further includes control terminal 324, second decoder
32 are connected by the control terminal 324 with logic control element 34.
Second decoder 32 is used to select two NMOS crystal in by the NMOS transistor of the row of selection conducting
Pipe, and pass through the source of first NMOS transistor in the two NMOS transistors of corresponding two second signal ends 322 acquisition
First output voltage V of pole1With the second output voltage V of the source electrode of second NMOS transistor2, and by first output voltage
V1With second output voltage V2It is delivered to comparing unit 33.
As shown in figure 4, the circuit structure can also include comparing unit 33.The comparing unit 33 is defeated for comparing first
Voltage V out1With the second output voltage V2Size, and PUF value is determined according to comparison result and exports the PUF value.For example, if V1
≥V2, it is determined that PUF value is 1；If V1<V2, it is determined that PUF value is 0.
As shown in figure 4, the circuit structure can also include logic control element 34.The first of the logic control element 34
Control output end 341 is connect with the control terminal 324 of the second decoder 32.The logic control element 34 can be used for receiving number
Encoded signal, and the digitally encoded signal is converted into the first control encoded signal, which is output to
Second decoder controls second decoder 32 selection, two transistors corresponding with the first control encoded signal to obtain
Corresponding first output voltage and the second output voltage.
1 digitally encoded signal of table is converted to the data conversion table of the first control encoded signal
| m3 | m2 | m1 | m0s5 | s4 | s3 | s2 | s1 | s0 |
| 0 | 0 | 0 | 00 | 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 0 | 10 | 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 00 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 10 | 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 01 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 10 | 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 00 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 10 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 01 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 10 | 0 | 1 | 1 | 0 | 0 |
| 1 | 0 | 1 | 00 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 11 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 00 | 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 11 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 00 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 10 | 0 | 0 | 0 | 0 | 0 |
Table 1 is that digitally encoded signal is converted to the first control by logic control element according to an embodiment of the invention
The data conversion table of encoded signal.In this embodiment it is assumed that transistor array shows 6 rowed transistors (the i.e. the 0th column to the 5th column).
In table 1, m0~m3 indicates digitally encoded signal, and s0~s5 indicates the first control encoded signal, a certain for control selections
Two transistors of the 0th capable column into the 5th rowed transistor.Here digitally encoded signal can be logic control element and connect
The square-wave signal received, the first control encoded signal can be the square-wave signal of logic control element sending.
For example, the first decoder selects the transistor turns of the 1st row, logic control element 34 receives digital coding letter
Number 0000, then the digitally encoded signal is converted into the first control encoded signal 000011, and by the first control encoded signal
000011 is output to the second decoder 32, controls second decoder 32 and selects the in the transistor of the 1st row the 0th to arrange and the 1st
Rowed transistor obtains corresponding first output voltage and the second output voltage, for example, can be by the 0th of the 1st row of the conducting the
The voltage of a transistor output is as the first output voltage, the voltage conduct of the 1st transistor output of the 1st row of the conducting
Second output voltage.The two output voltages are transported to comparison list after obtaining the two output voltages by the second decoder
Member.Comparing unit determines PUF value, such as the first output voltage less than second by comparing the size of the two output voltages
Output voltage, it is determined that PUF value is 0, to obtain the 0th rowed transistor of the 1st row and the 1st column crystal of the 1st row of the circuit structure
PUF value determined by managing is 0.
In one embodiment, as shown in figure 4, the second control output end 342 of the logic control element 34 and the first solution
The control terminal 312 of code device 31 connects.The logic control element 34 can be also used for exporting the second control volume to the first decoder 31
Code signal controls first decoder 31 and selects a row transistor and the row transistor is connected.
In an embodiment of the present invention, foregoing circuit structure can be arranged on chip.It is not when detecting some chip
When being required chip, the 0th rowed transistor of the 1st row and the 1st rowed transistor institute of the 1st row of foregoing circuit structure can detecte
Whether determining PUF value is 0, and if it is 0, detection passes through, and chip detected is required chip.
Certainly, above-described embodiment is just with the physical characteristic of two transistors of certain a line as the circuit structure
PUF value, in fact, multiple PUF values can also be determined to form PUF sequential value.For example, it is also possible to be connected in the 1st row transistor
In the case where, logic control element 34 receives digitally encoded signal 0001,0010,0100,0101 etc., to obtain corresponding
PUF value, or can also the 2nd row transistor be connected in the case where, logic control element 34 receives digitally encoded signal
0000,0001,0100,0101 etc., to obtain corresponding PUF value, these obtained PUF values are arranged in a certain order
Column get up, so that it may obtain PUF sequential value.
Fig. 5 is the connection figure for schematically showing the circuit structure in accordance with another embodiment of the present invention for PUF.
As shown in figure 5, the circuit structure includes transistor array 302, which is transistor array 30 shown in Fig. 3
Another embodiment.In this embodiment, as shown in figure 5, the transistor can be PMOS transistor, wherein
The first electrode of the PMOS transistor is source electrode, and the second electrode of the PMOS transistor is drain electrode.
Circuit structure shown in fig. 5 and circuit structure shown in Fig. 4 are essentially identical, except that: electricity shown in Fig. 4
Transistor array in line structure is NMOS transistor array, and the transistor array of circuit structure shown in fig. 5 is PMOS crystalline substance
Body pipe array.
As shown in figure 5, the transistor array 302 may include n × m PMOS transistor, wherein n and m is positive integer,
And n >=1, m >=2.Wherein the source electrode (i.e. first electrode) of each PMOS transistor is suitable for being applied supply voltage.With PMOS crystalline substance
For body pipe 51, the source electrode 511 of the PMOS transistor 51 is suitable for being applied supply voltage.The grid quilt of these PMOS transistors
It is connected to corresponding first signal end 311 of the first decoder 31, such as the grid 513 of the PMOS transistor 51 is connected to
0th the first signal end 311 of the first decoder 310.The drain electrode (i.e. second electrode) of these PMOS transistors is connected to
The corresponding second signal end 322 of two decoders 32, such as the drain electrode 512 of the PMOS transistor 51 are connected to the second decoding
0th second signal end 322 of device 320。
About other devices or unit of circuit structure shown in fig. 5, for example, the first decoder 31, the second decoder 32,
Comparing unit 33 and logic control element 34 have been described in front, and which is not described herein again.
What needs to be explained here is that in Fig. 5, since transistor array uses PMOS transistor array, first
For decoder 31 when selecting the transistor turns of certain a line, the grid voltage of output is less than threshold voltage of the grid (for PMOS
Transistor, the threshold voltage of the grid are negative voltages) negative voltage.
Fig. 6 schematically shows the circuit connection diagram of comparing unit according to an embodiment of the invention.
As shown in fig. 6, the comparing unit 33 may include: the first amplifier 331, the second amplifier 332 and comparator
333.First output end 326 of the second decoder 32 is connected to the input terminal of first amplifier 331, first amplifier 331
Output end be connected to the first input end 3331 of the comparator 333.The second output terminal 328 of second decoder 32 is connected to
The input terminal of second amplifier 332, the output end of second amplifier 332 are connected to the second input of the comparator 333
End 3332.First amplifier 331 receives the first output voltage from the second decoder 32, after first output voltage amplification
It exports to comparator 333.Second amplifier 332 receives the second output voltage from the second decoder 32, by second output voltage
It exports after amplification to comparator 333.For example, amplification factor of first amplifier 331 to the first output voltage received
It is equal to the amplification factor of the second output voltage received with second amplifier 332.The comparator 333, which compares, to be amplified
The size of rear the first output voltage and the second output voltage after being amplified determines PUF value according to comparison result and export should
PUF value.
In general, the first output voltage and the second output voltage are all smaller, it is not easy to compare their size, therefore,
In the embodiment, the first output voltage and the second output voltage first can be amplified into identical multiple, it is then more amplified
The two output voltages, to be easier to determine PUF value.
Fig. 7 is the testing result schematic diagram shown using the circuit structure of one embodiment of the present of invention.The result figure is
PUF output (abscissa) and corresponding sample number after having detected the transistor of certain two same position of 1000 samples
It measures (ordinate).It can be seen from figure 7 that PUF value tends to output low potential (i.e. " 0 ") and high potential (i.e. " 1 ").
Table 2 detects the corresponding data table of obtained transistor output voltage and PUF
Table 2 is the part output voltage of the transistor obtained from the detection of the sample extraction of Fig. 7 and the corresponding data of PUF
Table.Wherein, " la " indicates the corresponding output electricity of the transistor (being considered as first transistor in two transistors) on the left side
It presses (such as first output voltage), " ra " indicates that the transistor on the right (is considered as second crystal in two transistors
Pipe) corresponding output voltage (such as second output voltage).Such as first group of data, la=337mV, ra=469.3mV, la
< ra, then exporting PUF value is 0, other data are similar.
Fig. 8 is the flow chart for showing the method that PUF value is obtained using circuit structure according to an embodiment of the invention.
In step S801, supply voltage is applied to the first electrode of each transistor in transistor array.
In step S802, the transistor of any a line is selected using the first decoder and the row transistor is connected.
In one embodiment, step S802 may include: using logic control element to the first decoder output the
Two control encoded signals control first decoder and select a row transistor and the row transistor is connected.
In step S803, two transistors are selected in by the transistor of the row of selection conducting using the second decoder,
And obtain the second electrode of first transistor in the two transistors the first output voltage and second transistor
Second output voltage of two electrodes, and the first output voltage and the second output voltage are delivered to comparing unit.
In one embodiment, two crystalline substances are selected in by the transistor of the row of selection conducting using the second decoder
The step of body pipe may include: to control second to the second decoder output the first control encoded signal using logic control element
Decoder selection obtains corresponding first output voltage and second with corresponding two transistors of the first control encoded signal
Output voltage.
In one embodiment, the step of encoded signal is controlled to the second decoder output first using logic control element
It suddenly may include: that the logic control element receives digitally encoded signal, and the digitally encoded signal is converted to the first control and is compiled
The first control encoded signal is output to the second decoder by code signal.
In step S804, compare the size of the first output voltage and the second output voltage using comparing unit, and according to than
Relatively result determines PUF value and exports the PUF value.
In one embodiment, if the step of determining PUF value according to comparison result may include: that the first output voltage is big
In or equal to the second output voltage, it is determined that PUF value is 1；If the first output voltage is less than the second output voltage, it is determined that PUF
Value is 0.
By the above method, the method for obtaining PUF is realized using the circuit structure of the embodiment of the present invention.
Further, it can detecte whether chip is desired chip using the obtained PUF.
In one embodiment, multiple PUF values can be determined, and these PUF values are lined up in a certain order
Come, to form PUF sequential value.
So far, the present invention is described in detail.In order to avoid covering design of the invention, this field institute is not described
Well known some details.Those skilled in the art as described above, completely it can be appreciated how implementing skill disclosed herein
Art scheme.
Although some specific embodiments of the invention are described in detail by example, this field
It is to be understood by the skilled artisans that above example is merely to be illustrated, the range being not intended to be limiting of the invention.This field
It is to be understood by the skilled artisans that can be repaired without departing from the scope and spirit of the present invention to above embodiments
Change.The scope of the present invention is defined by the appended claims.
Claims (14)
1. a kind of circuit structure for the unclonable function PUF of physics characterized by comprising
Transistor array, the transistor array include n × m transistor, and wherein n and m is positive integer, and n >=1, m >=2；Its
In each transistor first electrode be suitable for be applied supply voltage；
First decoder comprising n the first signal ends, wherein i-th of first signal end passes through i-th wordline connection
The grid of the transistor of i-th row, wherein 0≤i≤n-1, and i is integer；First decoder is for selecting any a line
The row transistor simultaneously is connected in transistor；
Second decoder comprising m second signal end, wherein j-th of second signal end is connected by j-th strip bit line
The second electrode of the transistor of jth column, wherein 0≤j≤m-1, and j is integer；Second decoder by selection for leading
Two transistors are selected in the transistor of the logical row, and the two transistors are obtained by corresponding two second signal ends
In first transistor second electrode the first output voltage and second transistor second electrode second output electricity
Pressure, and first output voltage and second output voltage are delivered to comparing unit；And
The comparing unit is determined for comparing the size of the first output voltage and the second output voltage, and according to comparison result
PUF value simultaneously exports the PUF value.
2. circuit structure according to claim 1, which is characterized in that
If the comparing unit judges that first output voltage is greater than or equal to second output voltage, it is determined that PUF value
It is 1；If judging, first output voltage is less than second output voltage, it is determined that PUF value is 0.
3. circuit structure according to claim 1, which is characterized in that
The transistor is N-channel metal-oxide semiconductor (MOS) NMOS transistor, and the first electrode is drain electrode, second electricity
Extremely source electrode；
Alternatively,
The transistor is P-channel metal-oxide-semiconductor PMOS transistor, and the first electrode is source electrode, second electricity
Extremely drain.
4. circuit structure according to claim 1, which is characterized in that
Second decoder includes: the first output end and second output terminal；
The comparing unit includes: the first amplifier, the second amplifier and comparator；
First output end of second decoder is connected to the input terminal of first amplifier, first amplifier it is defeated
Outlet is connected to the first input end of the comparator；The second output terminal of second decoder is connected to second amplification
The output end of the input terminal of device, second amplifier is connected to the second input terminal of the comparator；
Wherein, first amplifier receives first output voltage from second decoder, by the first output electricity
Big rear output is pressed to the comparator；Second amplifier receives second output voltage from second decoder,
By output after second output voltage amplification to the comparator；Described first after the comparator is relatively amplified exports
The size of voltage and second output voltage after being amplified, determines PUF value according to comparison result and exports the PUF value.
5. circuit structure according to claim 4, which is characterized in that
First amplifier is to the amplification factor of first output voltage received and second amplifier to reception
The amplification factor of second output voltage arrived is equal.
6. circuit structure according to claim 1, which is characterized in that
The amount of bits that the circuit structure is determined according to the transistor array is n × Cm 2。
7. circuit structure according to claim 1, which is characterized in that further include:
Logic control element, the first control output end are connect with the control terminal of second decoder, are used for described second
Decoder output the first control encoded signal, it is corresponding with the first control encoded signal to control the second decoder selection
Two transistors obtain corresponding first output voltage and the second output voltage.
8. circuit structure according to claim 7, which is characterized in that
The digitally encoded signal is converted to the first control and compiled by the logic control element for receiving digitally encoded signal
The first control encoded signal is output to second decoder by code signal.
9. circuit structure according to claim 7, which is characterized in that
Second control output end of the logic control element is connect with the control terminal of first decoder；
The logic control element is also used to export the second control encoded signal to first decoder, controls first solution
Code device selects a row transistor and the row transistor is connected.
10. a kind of method for obtaining PUF value using circuit structure as claimed in any one of claims 1 to 9, feature exist
In, comprising:
Supply voltage is applied to the first electrode of each of the transistor array transistor；
The transistor of any a line is selected using first decoder and the row transistor is connected；
Using second decoder by selection conducting the row transistor in select two transistors, and obtain this two
The of the second electrode of the first output voltage and second transistor of the second electrode of first transistor in a transistor
Two output voltages, and first output voltage and second output voltage are delivered to comparing unit；And
It is tied using the size of the comparing unit first output voltage and second output voltage, and according to comparing
Fruit determines PUF value and exports the PUF value.
11. according to the method described in claim 10, it is characterized in that, the step of determining PUF value according to comparison result includes:
If first output voltage is greater than or equal to second output voltage, it is determined that PUF value is 1；If described first is defeated
Voltage is less than second output voltage out, it is determined that PUF value is 0.
12. according to the method described in claim 10, it is characterized in that,
Include: the step of two transistors of selection in by the transistor of the row of selection conducting using second decoder
Using logic control element to second decoder output the first control encoded signal, the second decoder choosing is controlled
Two transistors corresponding with the first control encoded signal are selected to obtain corresponding first output voltage and the second output electricity
Pressure.
13. according to the method for claim 12, which is characterized in that
Using logic control element to second decoder output first control encoded signal the step of include:
The logic control element receives digitally encoded signal, and the digitally encoded signal is converted to the first control coding letter
Number, the first control encoded signal is output to second decoder.
14. according to the method for claim 12, which is characterized in that
The transistor of any a line is selected using first decoder and includes: the step of the row transistor is connected
Using the logic control element to first decoder output the second control encoded signal, first decoding is controlled
Device selects a row transistor and the row transistor is connected.
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| CN110598488A (en) * | 2019-09-17 | 2019-12-20 | 山东大学 | Semiconductor unit device, semiconductor chip system, and PUF information processing system |
| CN111695162A (en) * | 2019-03-13 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | Device for generating a PUF signature |
| CN111723408A (en) * | 2019-03-21 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Device for generating a PUF signature |
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