CN109426738A - A kind of hardware decoder and encryption method, electronic device - Google Patents
A kind of hardware decoder and encryption method, electronic device Download PDFInfo
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- CN109426738A CN109426738A CN201710740049.4A CN201710740049A CN109426738A CN 109426738 A CN109426738 A CN 109426738A CN 201710740049 A CN201710740049 A CN 201710740049A CN 109426738 A CN109426738 A CN 109426738A
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- shift register
- feedback shift
- processing unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
Abstract
The present invention provides a kind of hardware decoder and encryption method, electronic device, the hardware decoder includes: storage of array unit, scanner, buffer, packaged unit, proframmable linear feedback shift register, logic unit and control unit, described control unit is from equipment is calculated according to the random address of code book reading source data, and source data is put into the first operand of logic unit, and the general Central Processing Unit or universal graphics processing unit that the pseudo random number that the proframmable linear feedback shift register generates is sent in the calculating equipment are subjected to floating-point Hash operation, and the floating number of return is put into the second operand of the logic unit, target data is generated by logical operation, then it is packaged target data and exports into the output file for calculating equipment.Level of encryption can be improved in the hardware decoder, increases and decodes difficulty.The encryption method has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to computer encryption technology fields, in particular to a kind of hardware decoder and encryption method, electricity
Sub-device.
Background technique
Encryption is a kind of typical engine with very long history, in the leading-edge field of contemporary microelectric technique, many GPCPU
(general Central Processing Unit) or GPGPU (universal graphics processing unit) have the encrypted feature of chip built-in.Encrypted feature point
For two classes: hardware based and software-based.Had an available standard encryption algorithms, and many have been carried out it is hard
In part.However, people find safer be not easy as computer evolution is to having powerful calculating ability and ultrafast calculating speed
The crypto engine broken through by hacker.
It is therefore desirable to propose a kind of hardware decoder and encryption method, electronic device, at least partly to solve above-mentioned ask
Topic.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of hardware decoder and encryption method, electronic device, Ke Yiti
For higher safety, decodes difficulty and increase.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of hardware decoder, comprising:
Storage of array unit, the storage of array unit are used to store the source data read from calculating equipment；
Logic unit, the logic unit is for carrying out XOR operation；
Scanner, the scanner are used to the source data stored in the storage of array unit reading the logic list
In the first operand of member；
Proframmable linear feedback shift register, the proframmable linear feedback shift register is for generating pseudorandom
Number；
Buffer, the buffer are used to store the operation result of the logic unit；
Packaged unit, the packaged unit is for reading the data stored in the buffer and packing；
Control unit, the pseudo random number that described control unit generates the proframmable linear feedback shift register are sent
General Central Processing Unit or universal graphics processing unit into the calculating equipment carry out floating-point Hash operation, and will be described
It calculates the floating number that general Central Processing Unit or universal graphics processing unit in equipment return and is put into the logic unit
In second operand, so that the logic unit carries out logical operation to the source data and floating number, and by the packing
The data that unit is packaged are exported as target data into the output file for calculating equipment.
Optionally, described control unit reads random address from the code book for calculating equipment, and according to described random
Source data is read in address, and read source data is stored to the storage of array unit.
Optionally, described control unit obtains programming key from the calculating equipment, and is based on programming key pair institute
Proframmable linear feedback shift register is stated to be programmed.
Optionally, the proframmable linear feedback shift register includes:
Linear feedback shift register unit group, the linear feedback shift register unit group include multiple be sequentially connected in series
Linear feedback shift register unit, for execute selection and shift function；
Feed array, the feedback control array are anti-for forming the linear feedback shift register unit each other
Feedthrough road；
Feedback control unit, the feedback control unit are arranged in the feed array, logical for controlling the feedback
The open and close in road.
Optionally, linear displacement feedback deposit unit include the trigger being sequentially connected in series, it is XOR gate, first anti-
Phase device and the first Port Multiplier, wherein the output of the input terminal of the trigger and the previous linear displacement feedback deposit unit
End connection, the clock signal terminal of the trigger are connect with clock signal, the output end of the trigger and the XOR gate
First input end is connected with the feedback channel, and the second input terminal of the XOR gate is connect with the feedback channel, described different
Or the output end of door is connect with the first input end of the input terminal of first phase inverter and first Port Multiplier, described first
The output end of phase inverter is connect with the second input terminal of first Port Multiplier, the control terminal and the volume of first Port Multiplier
Journey KEY DECODER output end connects, and linear displacement described in the output end and the latter of first Port Multiplier feeds back deposit unit
Input terminal connection.
Optionally, the linear displacement feeds back deposit unit further include:
Second Port Multiplier, the first input end of second Port Multiplier are connect with the output end of first Port Multiplier, institute
The second input terminal for stating the second Port Multiplier is connect with load data terminal, and the control terminal of second Port Multiplier and loading command end connect
It connects, linear displacement described in the output end and the latter of second Port Multiplier feeds back the input terminal connection of deposit unit.
Optionally, the feed array includes n row × n column exclusive or gate array, and each column XOR gate is sequentially connected in series, wherein
N is the quantity of the linear feedback shift register unit, and the output end of the XOR gate of the i-th column end and i-th of linear feedback are moved
Second input terminal connection of the XOR gate of position deposit unit, the touching of i-th of linear feedback shift register unit
Send out the output end of device in the i-th row in addition to the first input end of remaining XOR gate of the i-th column is connect, n more than or equal to 2, i from 0 to
n-1。。
Optionally, the feedback control unit includes third Port Multiplier, the second phase inverter and third phase inverter, and described second
The connection of the output end of the input terminal of phase inverter and the third phase inverter is simultaneously connect, second reverse phase with programming KEY DECODER
The input terminal of the output end of device and the third phase inverter is connected and is connect with the control terminal of the third Port Multiplier, the third
The first input end of Port Multiplier is connect with the output end of the trigger of linear feedback shift register unit described in other, described
The of XOR gate in second input end grounding of third Port Multiplier, the output end of the third Port Multiplier and the feed array
The connection of one input terminal.
Optionally, the quantity of the proframmable linear feedback shift register is two.
Optionally, described control unit controls the proframmable linear feedback shift register so that each linear shifting
Position feedback deposit unit carries out the linear shifting of one or more feedback or the proframmable linear feedback shift register
Position feedback deposit unit carries out circulation feedback, or carries out instead between two proframmable linear feedback shift registers
Feedback, or seed data is inserted into the proframmable linear feedback shift register.
Optionally, described control unit is handled the general Central Processing Unit calculated in equipment or general graphical single
The most significant word for the floating number that member returns is put into the second operand of the logic unit.
Optionally, described control unit is based on the general Central Processing Unit calculated in equipment or general graphical processing
Variable word length is added when the operation result of the logic unit is put into the buffer in the mantissa for the floating number that unit returns
Buffered data.
The pseudo random number that proframmable linear feedback shift register generates is sent to by hardware decoder according to the present invention
The general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU) for calculating equipment carry out floating-point Hash operation, and float
Value after point Hash operation does random number, original equally distributed random number is become to the random number of nonlinear Distribution, so that astonished
Visitor is difficult to crack, and due to directly utilizing the general Central Processing Unit (GCPU) or universal graphics processing unit for calculating equipment
(GGPU) floating-point Hash operation is carried out, therefore hardware decoder is not necessarily to redesign special FPU Float Point Unit, it not only can benefit
With the powerful floating-point operation ability of general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU), also reduce hard
Computing capability required for part encryption equipment and size, reduce costs.
Further, hardware decoder according to the present invention reads data using code book, i.e. data are not sequentially read,
Increase decoding difficulty.
Further, hardware decoder according to the present invention, according to the key of user, real-time programming proframmable linear feedback
The feedback channel of shift register, so that even if hacker obtains encryption equipment hardware and do not have key that can not program linear feedback shifting
Bit register increases decoding difficulty.
Another aspect of the present invention provides a kind of encryption method based on above-mentioned hardware decoder, comprising:
Source data is read from calculating in equipment, and is put into the storage of array unit of hardware decoder；
The proframmable linear feedback shift register for controlling hardware decoder generates pseudo random number, and by the pseudo random number
It is sent to the general Central Processing Unit for calculating equipment and/or graphics processing unit carries out floating-point Hash operation；
The source data stored in the storage of array unit is read the logic by the scanner of control hardware decoder
In the first operand of unit；
The floating number that the general Central Processing Unit for calculating equipment and/or graphics processing unit return is put into described
In the second operand of logic unit；
It controls the logic unit and carries out logical operation；
The operation result of the logic unit is put into buffer；
Control packaged unit reads the data stored in the buffer and packing；
The data that the packaged unit is packaged are exported as target data into the output file for calculating equipment.
Optionally, described to read source data from calculating equipment, and be put into the storage of array unit of hardware decoder and wrap
It includes:
Random address is read from the code book for calculating equipment, and source data is read according to the random address；
Read source data is stored to the storage of array unit.
Optionally, further includes: obtain programming key from the calculating equipment, and be based on to compile described in the programming key pair
Journey linear feedback shift register is programmed.
Optionally, further includes: control the proframmable linear feedback shift register so that each linear displacement is anti-
The linear displacement for presenting the deposit unit one or more feedback of progress or the proframmable linear feedback shift register is anti-
Feedback deposit unit carries out circulation feedback, or is inserted into seed data in the proframmable linear feedback shift register.
Optionally, by the floating-point of general Central Processing Unit or universal graphics processing unit return in the calculating equipment
Several most significant words is put into the second operand of the logic unit.
Optionally, further includes: the calculating is based on when the operation result of the logic unit is put into the buffer
The slow of variable word length is added in the mantissa for the floating number that general Central Processing Unit or universal graphics processing unit in equipment return
Rush data.
Optionally, further includes: if source data is less than the addressing space of the code book, then the source data is carried out
Clone, and the data after clone are put into after source data and form new source data.
The pseudo random number that proframmable linear feedback shift register generates is sent to meter by encryption method according to the present invention
The general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU) for calculating equipment carry out floating-point Hash operation, and floating-point
Value after Hash operation does random number, original equally distributed random number is become to the random number of nonlinear Distribution, so that hacker
It is difficult to crack, and due to directly utilizing the general Central Processing Unit (GCPU) or universal graphics processing unit for calculating equipment
(GGPU) floating-point Hash operation is carried out, therefore hardware decoder is not necessarily to redesign special FPU Float Point Unit, it not only can benefit
With the powerful floating-point operation ability of general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU), also reduce hard
Computing capability required for part encryption equipment and size, reduce costs.
Further, encryption method according to the present invention reads data using code book, i.e. data are not sequentially read, and increases
Decoding difficulty is added.
Further, encryption method according to the present invention, according to the key of user, real-time programming proframmable linear feedback is moved
The feedback channel of bit register, so that even if hacker obtains encryption equipment hardware and do not have key that can not program linear feedback shift
Register increases decoding difficulty.
Further, encryption method according to the present invention joined the buffered data of variable word length between data, so that
Hacker does not have encryption equipment to be difficult to find data head and data tail, increases decoding difficulty.
Further aspect of the present invention provides a kind of electronic device comprising:
Magnetic disk storage, for storing source data；
First memory, for storing code book；
Second memory, for storing key；
Memory is used for loading procedure and data；
General Central Processing Unit and/or graphics processing unit, for carrying out floating-point Hash operation；And
At hardware decoder as described above, the hardware decoder and the general Central Processing Unit and/or figure
Manage unit communication.
Electronic device proposed by the present invention due to above-mentioned hardware decoder, thus has the advantages that similar.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows hardware decoder according to an embodiment of the present invention and calculates the structural schematic diagram of equipment；
Fig. 2 shows the structural schematic diagrams of proframmable linear feedback shift register according to an embodiment of the present invention；
Fig. 3 shows the structural schematic diagram of linear feedback shift register unit according to an embodiment of the present invention；
Fig. 4 shows the structural schematic diagram of feedback control unit according to an embodiment of the present invention；
Fig. 5 goes out the detailed construction schematic diagram of proframmable linear feedback shift register according to an embodiment of the present invention；
Fig. 6 shows the step flow chart of encryption method according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
Hardware decoder according to an embodiment of the present invention is described in detail below with reference to Fig. 1 to Fig. 5.
The present embodiment proposes a kind of hardware decoder 100, is used as the general Central Processing Unit for calculating equipment 200
(GCPU) or the enhancing function accessories of universal graphics processing unit (GGPU) 26, realization hardware encrypt.Calculating equipment 200 includes magnetic
Disk storage (disk) 21, first memory (Universal Serial Bus Flash Disk 1, UFD1) 22, second are deposited
23, memory (Memory) 24, bus (system reservoir (Universal Serial Bus Flash Disk 2, UFD2)
Bus) 25 and general Central Processing Unit and/or graphics processing unit 26, magnetic disk storage (disk) 21 is for storing source data；
First memory (UFD1) 22 is for storing code book, and second memory (UFD2) 23 is for storing key；Memory 24 is for adding
Carry program and data；Bus 25 is for realizing general Central Processing Unit and/or graphics processing unit 26 and magnetic disk storage
(disk) communication between 21, first memory (UFD1) 22, second memory (UFD2) 23 and memory 24.General purpose central processing
Unit and/or graphics processing unit 26 are for realizing control and computing function, it is however generally that general Central Processing Unit and/or figure
Shape processing unit 26 has powerful Floating-point Computation ability, can be used for carrying out floating-point Hash operation.
As shown in Figure 1, in the present embodiment, hardware decoder 100 includes storage of array unit 11, scanner 12, buffering
Device 13, packaged unit 14, logic unit 15, double proframmable linear feedback shift registers 16 and control unit 17.
Storage of array unit (such as Array) 11 is used to store the source data read from calculating equipment 200, such as stores
The source data read from the magnetic disk storage 21 for calculating equipment 200.In the present embodiment, in order to increase the decoding difficulty of hacker,
Control unit 17 reads random address from the code book for calculating equipment 200, and reads source data according to the random address,
And store read source data into the storage of array unit 11, in this way since data are not sequentially read, increase
Decode difficulty.Illustratively, in the present embodiment, control unit reads two randomly from the code book calculated in equipment 200
Location, and two height double word (Hi& are read from storage from the magnetic disk storage 21 for calculating equipment 200 according to two random address
Lo Dword) source data, and stored into storage of array unit 11.
Scanner (such as Raster) 12 is used to the source data stored in storage of array unit 11 reading the logic
In the first operand of unit 15.Illustratively, in the present embodiment, control unit 17 will store in storage of array unit 11
Source data is sent into scanner 12, and scanner 12 reads the slice of source data according to pre-defined rule (that is, reading first character section
(byte) one (bit), then one of second byte is read, after running through one of all bytes, it is further continued for reading first
The another one of a byte, until all positions are all read).
Buffer (buffer) 13 is used for the operation result of storage logical units 15.
Packaged unit (packer) 14 is for reading the data stored in the buffer 13 and packing, such as packaged unit
(packer) 14 the data in buffer 13 are combined into word (double Dword) in pairs.
Logic unit (cipher logic unit, CLU) 15 is for carrying out XOR operation.One of operand be from
The floating number that the general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU) for calculating equipment 200 return, one
Operand is the source data that scanner 12 is read out.
Double proframmable linear feedback shift register (Dual Programmable Linear-Feedback Shift
Register, DPLSFR) 16 for generating pseudo random number, to send to the general Central Processing Unit (GCPU) for calculating equipment 200
Or universal graphics processing unit (GGPU) carries out floating-point Hash (hashing) operation.In the present embodiment, control unit 17 is from institute
It states and calculates the acquisition programming key of equipment 200, and based on double proframmable linear feedback shift registers described in the programming key pair
16 are programmed.In the present embodiment, due to according to the key real-time programming proframmable linear feedback shift register of user
Feedback channel (link), so that even if hacker obtains encryption equipment hardware and do not have key that can not program linear feedback shift register
Device increases decoding difficulty.
Control unit (cipher control unit, CCU) 17 is for controlling storage of array unit 11, scanner 12, delaying
Rush the operation of device 13, packaged unit 14, logic unit 15 and double proframmable linear feedback shift registers 16.In the present embodiment
In, the pseudo random number that double proframmable linear feedback shift registers 16 generate is sent to the calculating and set by control unit 17
General Central Processing Unit or universal graphics processing unit in standby 200 carry out floating-point Hash operation, and by the calculating equipment
In general Central Processing Unit or universal graphics processing unit return floating number be put into the logic unit 15 second behaviour
In counting, so that the logic unit 15 carries out logical operation to the source data and floating number, and by the packaged unit
14 data being packaged are exported as target data into the output file for calculating equipment 200.
According to the hardware decoder of the present embodiment, the pseudo random number that proframmable linear feedback shift register is generated is sent
Floating-point Hash operation is carried out to the general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU) for calculating equipment, and
Value after floating-point Hash operation does random number, and original equally distributed random number is become to the random number of nonlinear Distribution, so that
Hacker is difficult to crack, and due to directly handling list using the general Central Processing Unit (GCPU) or general graphical that calculate equipment
First (GGPU) carries out floating-point Hash operation, therefore hardware decoder is without redesigning special FPU Float Point Unit, not only can be with
Using the powerful floating-point operation ability of general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU), also reduce
Computing capability and size required for hardware decoder, reduce costs.
Below with reference to Fig. 2 to Fig. 5 to double proframmable linear feedback shift registers according to an embodiment of the present invention into
Row detailed description.
In the present embodiment, hardware decoder 100 is using double proframmable linear feedback shift registers 16, i.e., such as Fig. 2 institute
Show including two proframmable linear feedback shift registers of left-half and right half part.Each proframmable linear feedback shift is posted
Storage includes linear feedback shift register unit group 161, feed array 162 and feedback control unit 163.
Wherein, linear feedback shift register unit group (LFSR cell combos) 161 includes 64 linear feedback shifts
Deposit unit 0~63,64 linear feedback shift register units are sequentially connected in series, for executing selection and shift function.
Feed array 162 is for making each linear feedback shift register unit and other linear feedback shift register lists
Member forms feedback channel ((link/fabrics), to be fed back.Such as exist for each linear feedback shift register unit
63 feedback channels are connect, to be fed back respectively with other 63 linear feedback shift register units.
Feedback control unit (fabrics control unit) 163 is arranged in feed array 162, described for controlling
The open and close of feedback channel, to make have feedback between two linear feedback shift register units or without feedback.
As shown in figure 3, in the present embodiment, it includes the trigger being sequentially connected in series that linear displacement, which feeds back deposit unit,
31, XOR gate 32, the first phase inverter 33, the first Port Multiplier 34 and the second Port Multiplier 35.The input terminal (d sections) of trigger 31 is with before
The output end connection of one linear displacement feedback deposit unit, namely deposit unit is fed back with the previous linear displacement
The second Port Multiplier 35 output end connection.The clock signal terminal (clk) of trigger 31 is connect with clock signal, and is believed in clock
Start-up operation when number being enabled, clock signal stop working when stopping enabled.The output end (i.e. the end Q) and XOR gate of trigger 31
32 first input end connection, and pass through the array 162 and the second of the XOR gate of other linear displacements feedback deposit unit
Input terminal connection.Second input terminal of XOR gate 32 feeds back deposit unit with other linear displacements by the feed array 162
Connection.The output end of XOR gate 32 is connect with the first input end of 33 input terminals of the first phase inverter and the first Port Multiplier 34,
The output end of first phase inverter 33 is connect with the second input terminal of the first Port Multiplier 34, the control terminal and programming of the first Port Multiplier 34
The connection of KEY DECODER output end, the output end of the first Port Multiplier 34 are connect with the second input terminal of the second Port Multiplier 35, and second
The first input end of Port Multiplier 35 is connect with load data terminal, for inputting load data (Loading data), the second multichannel
The control terminal of device 35 is connect with loading command end (loading command), the output end of the second Port Multiplier 35 and the latter institute
State the input terminal connection of linear displacement feedback deposit unit.It can be when needed to can by loading command and load data
It programs in linear feedback shift register and is inserted into seed (seed), to avoid similar random number is generated.
As shown in figure 5, in the present embodiment, feed array 162 includes n row × n column exclusive or gate array, each column XOR gate according to
Secondary series connection, wherein n be the linear feedback shift register unit quantity, i-th column end XOR gate output end with
Second input terminal of the XOR gate of i-th of linear feedback shift register unit connects, and i-th of linear feedback shift is posted
The output end of the trigger of memory cell is connect with the first input end of remaining XOR gate arranged in the i-th row in addition to i-th, and n is big
In be equal to 2, i from 0 to n-1.For example, the output end of the trigger of the 5th linear feedback shift register unit and feed array 162
In the 5th row XOR gate first input end connection, in addition in the 5th row be located at the 5th column in XOR gate other than；Feed array
The XOR gate of the 5th column is sequentially connected in series in 162, and the output end of end XOR gate and the 5th linear feedback shift register list
Second input terminal connection of the XOR gate of member, namely the feedback from other linear feedback shift register units are passed through
Second input terminal of the XOR gate of 5 linear feedback shift register units is input to after XOR operation.
Illustratively, n is equal to 64 in the present embodiment.
As shown in figure 4, in the present embodiment, feedback control unit 163 includes the second phase inverter 40,41 and of third phase inverter
Third Port Multiplier 42, wherein the connection of the output end of the input terminal of the second phase inverter 40 and third phase inverter 41 and with programming key
Decoder connection, for obtaining decoded programming key；The input of the output end and third phase inverter 41 of second phase inverter 40
End connects and connect with the control terminal of third Port Multiplier 42, for selecting the signal of third Port Multiplier, the third Port Multiplier 42
First input end connect with the output end of the trigger of linear feedback shift register unit described in other, that is, pass through feedback
Array 162 is connect with the output end of the trigger 31 of linear feedback shift register unit described in other, the third multichannel
Second input end grounding of device 42, the first of the output end of the third Port Multiplier 42 and the XOR gate in feed array 162 are defeated
Enter end connection.Feed array can be programmed as described previously by programming key (Program key), such as programming key is affirmed
For i unit to the feedback of j unit, the output line of the trigger of i-th of unit is just connected to the first defeated of the XOR gate of j column
Enter end；If do not affirmed, ground voltage is just connected to the first input end of the XOR gate of j column, and ground voltage (connecing zero) arrives
XOR gate is equal to nothing operation, that is, does not feed back.
It is understood that control unit as shown in Figure 4 is both provided with for each XOR gate in feed array, with
Control the feedback of Unit i-th to j-th.The structure of entire proframmable linear feedback shift register is as shown in Figure 5.Control is single
The key of first 17 couples of users is decoded, and uses the Feedback Matrix of decoded key pair proframmable linear feedback shift register
Whether column 162 are programmed, i.e. the disconnection and closure of the feed array 162 of proframmable linear feedback shift register, i.e., select
The feedback signal from other linear feedback deposit units in Port Multiplier depends on decoded key.
It is understood that although in the present embodiment, the proframmable linear feedback shift register is double programmable
Linear feedback shift register, but random number can also be generated using the register of other structures in other embodiments.
Further, it is to be understood that it is anti-that control unit 17 controls the proframmable linear in order to increase decoding difficulty
It presents shift register and carries out various types of feedbacks, such as carry out each linear displacement feedback deposit unit once or more
More feedbacks, or so that the linear displacement of the proframmable linear feedback shift register is fed back deposit unit and recycle instead
Feedback, or fed back between double proframmable linear feedback shift registers that (above-described embodiment only individually may be programmed
Fed back between the linear feedback shift register unit of linear feedback shift register), or compiled as described above described
Seed data (seed) is inserted into journey linear feedback shift register.
Hardware decoder shown in FIG. 1 and the exemplary encryption process for calculating equipment are as follows:.
Firstly, into the user program (user program) of encryption equipment；Then, user is from second memory (UFD2) 23
Selection programming key (programming key)；Then, control unit 17 obtains programming key, and key programs based on programming
Double proframmable linear feedback shift registers (that is, DPLFSR) 16 are programmed (i.e. according to the double programmable lines of programming key confirmation
Whether the feedback channel of property feedback shift register connects)；Then, user's key since selecting second memory (UFD2) 23
(initializing key namely seed are the initial value for being input to 128 DPLFSR)；Then, control unit 17 obtains
Home key, and start double proframmable linear feedback shift registers 16；Then, user's key feeding cipher (password,
Password is for selecting code book, because having several code books in first memory (UFD1) 22)；Then, user program
Code book (map) is selected from first memory (UFD1) 22；Then, user program exports addressable address；Then, user program makes
Two sections of source datas are read from magnetic disk storage 21 with the height double word (i.e. two random address of height double word) of code book；It connects
, control unit 17 obtains two sections of source datas and stores it in storage of array unit 11；Then, user program issues
Encrypted instruction 1；Then, control unit 17 enables the clock signal of DPLFDR16；Then, after setting time, control unit
17 stop the clock signal of DPLFDR16；Then, control unit 17 collect from DPLFDR16 double word (Dwords, two words,
32) pseudo random number；Then, the double word of collection is back to user program by control unit 17, and completes to instruct；Then, user
Program is that each double word executes floating-point Hash operation, and specifically user program is carried out by calculating the GCPU and GGPU of equipment 200
Floating-point Hash operation (FP, Hashing), and being used operation result as random number, i.e., by floating-point Hash operation by puppet with
Machine number is converted to random number；Then, the result of floating-point Hash operation is put into the register of control unit 17 by user program, and
Issue encrypted instruction 2；Then, the floating-point that control unit 17 picks up each double word from register (picks up each DPLFDR16
The Hash operation result of each double word generated)；Then, the most significant word of the floating-point of return is stored in and patrols by control unit 17
In the second operand (operand2) for collecting unit 15, i.e., by the general Central Processing Unit or standard drawing in the calculating equipment
The most significant word (most significant word, MSW) for the floating number that shape processing unit returns is put into logic unit 15
In second operand (operand2), illustratively, in the present embodiment, by first 16 of the floating-point of return (in the present embodiment
Floating-point is single precision, 32) it stores into the second operand of logic unit 15 (operand2)；Then, control unit 17 will
(16 after such as) stores into the register of control unit 17 itself the remaining position of the floating-point of return；Then, user program is sent out
Encrypted instruction 3 out；Then, user program intercepts the instruction (encrypted instruction 3)；Then, control unit 17 is regular by data scanning
It is sent in scanner 12 that (i.e. control unit 17 tells scanner 12, in storage of array unit 11 in first character section (byte)
Which position (bit) should scan, which bit in second byte should be scanned)；Then, scanner
12slice source data is into the first operand (operrand1) of logic unit 15, that is, scanner 12 is read according to pre-defined rule
The slice of source data is taken (that is, reading one (bit) of first character section (byte), then to read one of second byte, read
After one of complete all bytes, it is further continued for reading the another one of first character section, until all positions are all read), then it will read
Data be put into the first operand (operrand1) of logic unit 15；Then, encrypted instruction 3 is continued to execute, circulation executes
Aforementioned process, all data stored in straight storage of array unit 11 are all sent to the first operand of logic unit 15
(operrand1) in；Then, user program issues encrypted instruction 4；Then, control unit 17 executes encrypted instruction 4, with exchange
Upset the source data in the first operand (operrand1) of logic unit 15；Then, encrypted instruction 4 is continued to execute, until following
Ring is to the end of source data；Then, logic unit 15 executes logical operation, such as exclusive or to first operand and second operand
Operation；Then, user program issues encrypted instruction 5；Then, control unit 17 solves code instruction, and by the return being locally stored
The remaining bit of floating-point is stored into buffer 13, i.e., control unit 17 is based on the general Central Processing Unit in the calculating equipment
Or the operation result of the logic unit is being put into the buffer by the mantissa of the floating number of universal graphics processing unit return
When be added variable word length buffered data；Then, control unit 17 is by a bit transition of the operation result of logic unit 15 to slow
It rushes in device 13；Then, circulation executes encrypted instruction 5, until the operation result of logic unit 15 is all put into buffer 13；It connects
, the data in buffer 13 are packaged (assemblies) double word in pairs (being packaged into 64 data) by packaged unit 14；It connects
, user program issues encrypted instruction 6；Then, user program collects data from hardware decoder 100；Then, user program will
In the output file of the data write-in magnetic disk storage 21 of collection；Then, the above process is repeated, until code book reaches end
End, i.e., until user program discovery input file is less than the addressable space of code book, otherwise user program is from first memory
(UFD1) 22 selections are loaded into another code book (map), and from starting to repeat the above process.
It should be appreciated that in above process, can also include the following steps, such as user program exports addressable address, and
User program reads two sections using the height double word (i.e. two random address of height double word) of code book from magnetic disk storage 21
Between source data, user program can be cloned source data if it find that source data is smaller so that data can fill up it is close
The addressable space of code book avoids file too small and is easy to be cracked.For example, the addressing space of code book is 4GB, and source file
Only 0.5GB, the then data for cloning 3.5GB are placed on after source data, to gather together enough 4GB.In addition, when the end data to source data
When being encrypted, if end data again smaller than the addressable space of code book, can equally clone end data, with
It is set to fill up the addressing space of code book.
It will also be appreciated that can be sent out encrypted instruction 7 in certain phase user programs in above process, according to
The instruction, control unit 17 can execute one or more specialized operations, such as make each linear displacement feedback deposit
Unit carries out one or more feedback, or feeds back the linear displacement of the proframmable linear feedback shift register and post
Memory cell carries out circulation feedback, or is fed back (above-mentioned implementation between double proframmable linear feedback shift registers
Example is only fed back between the linear feedback shift register unit of single proframmable linear feedback shift register), Huo Zheru
Upper insertion seed data (seed) in the proframmable linear feedback shift register.
Embodiment two
Encryption method according to an embodiment of the present invention is described in detail below with reference to Fig. 6.
The present embodiment discloses a kind of encryption method based on above-mentioned hardware decoder, comprising:
Step 601, source data is read from calculating equipment, and be put into the storage of array unit of hardware decoder.
Illustratively, in the present embodiment, random address is read from the code book for calculating equipment first, and according to institute
It states random address and reads source data, then store read source data to the storage of array unit.For example, being set from calculating
Code book is selected in standby first memory, and reads the random address of two height double words from code book, and then basis should
Two random address read one section of source data from the magnetic disk storage for calculating equipment.
Step 602, the proframmable linear feedback shift register for controlling hardware decoder generates pseudo random number, and will be described
Pseudo random number is sent to the general Central Processing Unit for calculating equipment and/or graphics processing unit carries out floating-point Hash fortune
It calculates.
Illustratively, the double proframmable linear feedback shift registers are controlled and generate pseudo random numbers, and generate it is pseudo- with
Machine number is sent to the general Central Processing Unit and/or graphics processing unit for calculating equipment, utilizes its powerful floating-point operation ability
Floating-point Hash operation is carried out, and the floating number generated is used to carry out logical operation as random number, in this way by equally distributed puppet
Random number is converted to the random number of nonlinear Distribution, increases decoding difficulty.
Further, it generates in pseudo-random number processes controlling the double proframmable linear feedback shift registers, it can be with
Programming key is obtained from the calculating equipment, and based on double proframmable linear feedback shift registers described in the programming key pair
It is programmed, to be configured flexibly the feedback channel (link) of double proframmable linear feedback shift registers, increases
Decode difficulty.Further, it is also possible to which controlling double proframmable linear feedback shift registers makes each linear displacement feedback
Deposit unit carries out one or more feedback, or keeps the linear displacement of the proframmable linear feedback shift register anti-
Feedback deposit unit carries out circulation feedback, or is fed back between double proframmable linear feedback shift registers (above-mentioned
Embodiment is only fed back between the linear feedback shift register unit of single proframmable linear feedback shift register), or
Person as described above in the proframmable linear feedback shift register be inserted into seed data (seed), with by it is various feedback or
Seed is inserted into increase decoding difficulty.
Step 603, the scanner for controlling hardware decoder reads the source data stored in the storage of array unit
In the first operand of the logic unit.
Illustratively, the source data that storage of array unit stores is sent to scanner, the source scanner slice by control unit
Data are into the first operand (operrand1) of logic unit, that is, scanner reads source data according to pre-defined rule
Slice (that is, reading one (bit) of first character section (byte), then reads one of second byte, runs through all bytes
One after, be further continued for read first character section another one, until all positions are all read), then the data of reading are put into
In the first operand (operrand1) of logic unit.
It should be understood that the process needs to be implemented repeatedly, until the source data stored in storage of array unit is all put into logic list
In the first operand (operrand1) of member.
Step 604, the floating number general Central Processing Unit for calculating equipment and/or graphics processing unit returned
It is put into the second operand of the logic unit.
Illustratively, the general Central Processing Unit calculated in equipment or universal graphics processing unit are returned floating
The most significant word of points is put into the second operand of the logic unit.In addition, by the remaining bit of the floating number of return into
Row is locally stored, such as is put into the register of control unit.
Step 605, it controls the logic unit and carries out logical operation.
Illustratively, such as by the logic unit data in first operand and second operand are made to carry out exclusive or
Operation.
Illustratively, before carrying out logical operation, exchange can also be executed to the data in first operand and upsets behaviour
Make (permuting).
Step 606, the operation result of the logic unit is put into buffer.
Illustratively, such as control unit by operation result one one of logic unit is put into buffer, until
Until all operation results are all put into buffer.
Illustratively, it before or after being put into buffer for one of logic operation result, can also will be locally stored
The remaining bit of floating-point of return store into buffer, i.e., control unit is based on the general purpose central processing in the calculating equipment
The operation result of the logic unit is being put into described delay by the mantissa for the floating number that unit or universal graphics processing unit return
The buffered data of variable word length is added when rushing device.
Step 607, control packaged unit reads the data stored in the buffer and packing.
Illustratively, the data in buffer are packaged into double-word data in pairs, i.e. 64 data by packaged unit.
Step 608, the data that the packaged unit is packaged are exported as target data to the output for calculating equipment
In file.
Illustratively, control unit exports the data that packaged unit is packaged to the calculating equipment as target data
In output file.
It should be understood that the sequence of each step is adjustable in the above process, and if source data is larger, the above process is only
It is the cryptographic operation that with a portion of to source data, therefore also needs to encrypt all sources by repeating aforesaid operations
Data.
In addition, it should be understood that being, for example, less than given threshold if source data is smaller, that is, it is less than the addressing space of code book,
The source data can then be cloned, and the data after clone are put into the end of addressing space, though data fill up it is close
The addressing space of code book.
According to the encryption method of the present embodiment, the pseudo random number that proframmable linear feedback shift register generates is sent to
The general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU) for calculating equipment carry out floating-point Hash operation, and float
Value after point Hash operation does random number, original equally distributed random number is become to the random number of nonlinear Distribution, so that astonished
Visitor is difficult to crack, and due to directly utilizing the general Central Processing Unit (GCPU) or universal graphics processing unit for calculating equipment
(GGPU) floating-point Hash operation is carried out, therefore hardware decoder is not necessarily to redesign special FPU Float Point Unit, it not only can benefit
With the powerful floating-point operation ability of general Central Processing Unit (GCPU) or universal graphics processing unit (GGPU), also reduce hard
Computing capability required for part encryption equipment and size, reduce costs.
Further, encryption method according to the present invention reads data using code book, i.e. data are not sequentially read, and increases
Decoding difficulty is added.
Further, encryption method according to the present invention, according to the key of user, real-time programming proframmable linear feedback is moved
The feedback channel of bit register, so that even if hacker obtains encryption equipment hardware and do not have key that can not program linear feedback shift
Register increases decoding difficulty.
Further, encryption method according to the present invention joined the buffered data of variable word length between data, so that
Hacker does not have encryption equipment to be difficult to find data head and data tail, increases decoding difficulty.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including hardware decoder and encrypts with the hardware
The electronic building brick of device connection.
The hardware decoder includes storage of array unit, and the storage of array unit is read from calculating equipment for storing
The source data taken；Logic unit, the logic unit is for carrying out XOR operation；Scanner, the scanner is used for will be described
The source data stored in storage of array unit is read in the first operand of the logic unit；Proframmable linear feedback shift
Register, the proframmable linear feedback shift register is for generating pseudo random number；Buffer, the buffer is for storing
The operation result of the logic unit；Packaged unit, the packaged unit are used to read the data stored in the buffer simultaneously
It is packaged；The pseudo random number that the proframmable linear feedback shift register generates is sent to by control unit, described control unit
General Central Processing Unit in the calculating equipment or universal graphics processing unit carry out floating-point Hash operation, and by the meter
It calculates the floating number that general Central Processing Unit or universal graphics processing unit in equipment return and is put into the of the logic unit
In two operands, so that the logic unit carries out logical operation to the source data and floating number, and by the pack slip
The data that member is packaged are exported as target data into the output file for calculating equipment.
The electronic building brick includes magnetic disk storage, for storing source data；First memory, for storing code book；
Second memory, for storing key；Memory is used for loading procedure and data；General Central Processing Unit and/or graphics process
Unit, for carrying out floating-point Hash operation.
The electronic device of the present embodiment can be laptop, net book, desktop computer etc. and calculate equipment, can also
For any intermediate products including the semiconductor devices.
The electronic device of the embodiment of the present invention increases and decodes since the hardware decoder for being included improves level of encryption
Difficulty, thus the electronic device have the advantages that it is similar.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (20)
1. a kind of hardware decoder characterized by comprising
Storage of array unit, the storage of array unit are used to store the source data read from calculating equipment；
Logic unit, the logic unit is for carrying out XOR operation；
Scanner, the scanner are used to the source data stored in the storage of array unit reading the logic unit
In first operand；
Proframmable linear feedback shift register, the proframmable linear feedback shift register is for generating pseudo random number；
Buffer, the buffer are used to store the operation result of the logic unit；
Packaged unit, the packaged unit is for reading the data stored in the buffer and packing；
The pseudo random number that the proframmable linear feedback shift register generates is sent to institute by control unit, described control unit
It states and calculates general Central Processing Unit in equipment or universal graphics processing unit carries out floating-point Hash operation, and by the calculating
The floating number that general Central Processing Unit or universal graphics processing unit in equipment return is put into the second of the logic unit
In operand, so that the logic unit carries out logical operation to the source data and floating number, and by the packaged unit
The data of packing are exported as target data into the output file for calculating equipment.
2. hardware decoder according to claim 1, which is characterized in that
Described control unit reads random address from the code book for calculating equipment, and reads source number according to the random address
According to, and read source data is stored to the storage of array unit.
3. hardware decoder according to claim 1, which is characterized in that described control unit is obtained from the calculating equipment
Key is programmed, and is programmed based on proframmable linear feedback shift register described in the programming key pair.
4. hardware decoder according to claim 3, which is characterized in that the proframmable linear feedback shift register packet
It includes:
Linear feedback shift register unit group, the linear feedback shift register unit group include multiple lines being sequentially connected in series
Property feedback shift register unit, for execute selection and shift function；
Feed array, the feedback control array are logical for making the linear feedback shift register unit form feedback each other
Road；
Feedback control unit, the feedback control unit is arranged in the feed array, for controlling the feedback channel
Open and close.
5. hardware decoder according to claim 4, which is characterized in that linear displacement feedback deposit unit include according to
Trigger, XOR gate, the first phase inverter and the first Port Multiplier of secondary series connection, wherein the input terminal of the trigger with it is previous
The output end connection of a linear displacement feedback deposit unit, the clock signal terminal of the trigger are connect with clock signal,
The output end of the trigger is connect with the first input end of the XOR gate and the feedback channel, and the second of the XOR gate
Input terminal is connect with the feedback channel, the input terminal and described first of the output end of the XOR gate and first phase inverter
The first input end of Port Multiplier connects, and the second input terminal of the output end of first phase inverter and first Port Multiplier connects
It connects, the control terminal of first Port Multiplier is connect with the programming KEY DECODER output end, the output of first Port Multiplier
It holds and is connect with the input terminal of the feedback deposit unit of linear displacement described in the latter.
6. hardware decoder according to claim 5, which is characterized in that the linear displacement feedback deposit unit also wraps
It includes:
Second Port Multiplier, the first input end of second Port Multiplier are connect with the output end of first Port Multiplier, and described
Second input terminal of two Port Multipliers is connect with load data terminal, and the control terminal of second Port Multiplier is connect with loading command end,
Linear displacement described in the output end and the latter of second Port Multiplier feeds back the input terminal connection of deposit unit.
7. hardware decoder according to claim 5, which is characterized in that the feed array includes n row × n column XOR gate
Array, each column XOR gate are sequentially connected in series, and wherein n is the quantity of the linear feedback shift register unit, the i-th column end
The output end of XOR gate is connect with second input terminal of the XOR gate of i-th of linear feedback shift register unit, and i-th
In addition to the of remaining XOR gate of the i-th column in the output end and the i-th row of the trigger of a linear feedback shift register unit
The connection of one input terminal, n are more than or equal to 2, i from 0 to n-1.
8. hardware decoder according to claim 7, which is characterized in that the feedback control unit includes third multichannel
Device, the second phase inverter and third phase inverter, the input terminal of second phase inverter are connected with the output end of the third phase inverter
And connect with programming KEY DECODER, the input terminal of the output end of second phase inverter and the third phase inverter connect and with
The control terminal of the third Port Multiplier connects, and the first input end of the third Port Multiplier is posted with linear feedback shift described in other
The output end of the trigger of memory cell connects, the second input end grounding of the third Port Multiplier, the third Port Multiplier
Output end connect with the first input end of the XOR gate in the feed array.
9. hardware decoder according to claim 4, which is characterized in that the proframmable linear feedback shift register
Quantity is two.
10. hardware decoder according to claim 9, which is characterized in that described control unit controls the programmable line
Property feedback shift register so that each linear displacement feedback deposit unit carry out one or more feedback or it is described can
The linear displacement feedback deposit unit of programming linear feedback shift register carries out circulation feedback, or can described in two
It is fed back between programming linear feedback shift register, or is inserted into seed in the proframmable linear feedback shift register
Data.
11. hardware decoder according to claim 1, which is characterized in that described control unit will be in the calculating equipment
General Central Processing Unit or the most significant word of floating number that returns of universal graphics processing unit be put into the logic unit
Second operand in.
12. hardware decoder according to claim 1, which is characterized in that described control unit is based on the calculating equipment
In the mantissa of floating number that returns of general Central Processing Unit or universal graphics processing unit by the fortune of the logic unit
Calculate the buffered data that variable word length is added when result is put into the buffer.
13. a kind of encryption method of hardware decoder described in any one based in claim 1-12, which is characterized in that
Include:
Source data is read from calculating in equipment, and is put into the storage of array unit of hardware decoder；
The proframmable linear feedback shift register for controlling hardware decoder generates pseudo random number, and the pseudo random number is sent
Floating-point Hash operation is carried out to the general Central Processing Unit for calculating equipment and/or graphics processing unit；
The source data stored in the storage of array unit is read the logic unit by the scanner of control hardware decoder
First operand in；
The floating number that the general Central Processing Unit for calculating equipment and/or graphics processing unit return is put into the logic
In the second operand of unit；
It controls the logic unit and carries out logical operation；
The operation result of the logic unit is put into buffer；
Control packaged unit reads the data stored in the buffer and packing；
The data that the packaged unit is packaged are exported as target data into the output file for calculating equipment.
14. encryption method according to claim 13, which is characterized in that it is described to read source data from calculating equipment, and
It is put into the storage of array unit of hardware decoder and includes:
Random address is read from the code book for calculating equipment, and source data is read according to the random address；
Read source data is stored to the storage of array unit.
15. encryption method according to claim 13, which is characterized in that further include:
Programming key is obtained from the calculating equipment, and based on proframmable linear feedback shift register described in the programming key pair
Device is programmed.
16. encryption method according to claim 15, which is characterized in that further include:
The proframmable linear feedback shift register is controlled so that each linear displacement feedback deposit unit carries out once
Or more feedback or the proframmable linear feedback shift register the linear displacement feedback deposit unit recycled
Feedback, or seed data is inserted into the proframmable linear feedback shift register.
17. encryption method according to claim 13, which is characterized in that
The highest of the floating number of general Central Processing Unit or universal graphics processing unit return in the calculating equipment is had
Effect word is put into the second operand of the logic unit.
18. encryption method according to claim 13, which is characterized in that further include:
When the operation result of the logic unit is put into the buffer based on it is described calculating equipment in general purpose central at
The buffered data of variable word length is added in the mantissa for managing the floating number of unit or universal graphics processing unit return.
19. encryption method according to claim 14, which is characterized in that further include:
If source data is less than the addressing space of the code book, the source data is cloned, and by the number after clone
New source data is formed according to being put into after source data.
20. a kind of electronic device characterized by comprising
Magnetic disk storage, for storing source data；
First memory, for storing code book；
Second memory, for storing key；
Memory is used for loading procedure and data；
General Central Processing Unit and/or graphics processing unit, for carrying out floating-point Hash operation；And
At hardware decoder as described in any one in claim 1-12, the hardware decoder and the general purpose central
Manage unit and/or graphics processing unit communication.
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| WO2022120999A1 (en) * | 2020-12-11 | 2022-06-16 | 清华大学无锡应用技术研究院 | Feedback shift register array-based sequence cipher algorithm computing system |
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