CN109409083B - Device for detecting return address tampering in stack - Google Patents
Device for detecting return address tampering in stack Download PDFInfo
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- CN109409083B CN109409083B CN201811108316.7A CN201811108316A CN109409083B CN 109409083 B CN109409083 B CN 109409083B CN 201811108316 A CN201811108316 A CN 201811108316A CN 109409083 B CN109409083 B CN 109409083B
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Abstract
The embodiment of the invention provides a device for detecting the falsification of a return address in a stack, wherein the return address and a hash value are stored and verified through a chain structure.
Description
Technical Field
The present invention relates to the field of computer technology, and more particularly, to an apparatus for detecting a return address in a stack being tampered.
Background
The construction and development of computer technology and internet bring great promotion and impact to all aspects of economy, culture, science and technology and the like of the whole society, and a large number of informatization systems such as telecom, electronic commerce, financial network and the like become key infrastructure of the nation and government, so that how to ensure the safety of a computer system becomes a problem which is urgently needed to be solved before people.
The stack overflow bug is an extremely serious system security bug, which is that the system memory space is damaged by writing overlong data into a limited memory space, so that the system runs abnormally, crashes or restarts. Through stack overflow attack, an attacker can acquire partial or all system control rights by using an address overlay function pointer of an attack code, which is a security risk with great threat.
In the prior art, a main prevention and defense mode for stack overflow attack is to ensure that a return address is not maliciously tampered by a shadow stack and a stack protection technology. But the security of the shadow stack and stack protection is not enough, and an attacker still can find some ways to bypass the two defense technologies for attack.
Disclosure of Invention
To address the above problems, embodiments of the present invention provide an apparatus for detecting tampering of a return address in a stack that overcomes, or at least partially solves, the above problems.
According to a first aspect of the embodiments of the present invention, there is provided an apparatus for detecting a tamper of a return address in a stack, including a hash value calculation module, a verification module, and a Top register:
the hash value calculation module is used for generating an algorithm based on any hash value according to the return address to be verified and the hash value corresponding to the return address to be verified, which are stored in the top frame of the stack in the stack, so as to obtain the hash value to be verified;
wherein, the ith frame in the stack stores the ith return address and a random number; any frame from the (i + 1) th frame to the top frame in the stack stores a return address corresponding to the frame and a hash value corresponding to the return address, wherein the hash value corresponding to the return address generates an algorithm based on the hash value according to the return address stored in the previous frame of the frame and the hash value corresponding to the return address in the stack, and the obtained hash value is obtained; j is more than i and is more than or equal to 1, wherein j is the serial number of the stack top frame;
the verification module is used for confirming that the return address to be verified is tampered if the hash value to be verified is different from the correct hash value generated in advance; the correct hash value is obtained in advance according to an untampered return address of a stack top frame in a stack and a hash value corresponding to the untampered return address based on any hash value generation algorithm;
the Top register is used for storing the correct hash value, and the correct hash value stored in the Top register can only be modified through a preset instruction;
an instruction set including at least a set of call instructions and return instructions different from native in the system in which the stack is located, for performing call and return operations in the stack;
when the operating system where the device is located switches processes, the correct hash value stored in the Top register involved in the process switching needs to be saved or restored;
in the compiler corresponding to the device, it is necessary to ensure that instructions for executing call and return operations in the stack appear in pairs in an instruction set different from the native call instruction and return instruction in the system in which the stack is located;
when a process starts, a value in a Top register needs to be initialized based on an operating system where the device is located or a compiler corresponding to the device.
The device further comprises:
the counter is used for adding one to the count when the stack executes a calling operation and subtracting one from the count when the stack executes a return operation; when the process is finished, if the counting number of the counter is not 0 or the correct hash value in the Top register is modified, an error is reported.
Further, at least one set of instructions is included that is different from the set of call and return instructions native to the system in which the stack is located, wherein the included call and return instructions are privileged instructions;
in the compiler corresponding to the device, an instruction set different from the native call instruction and return instruction in the system in which the stack is located is guaranteed, and the call instruction and return instruction contained therein are present in pairs.
Further, at least one instruction set is included, which is different from the native read instruction and write instruction in the system where the Top register is located, and is used for executing the read operation and the write operation in the Top register; and at least one instruction set containing a set of read instructions and write instructions different from those native to the system in which the Top register is located, wherein the read instructions and the write instructions are privileged instructions.
Further, at least one instruction set is included, different from the read and write instructions native to the system in which the counter resides, for performing read and write operations in the counter; at least one instruction set is included that is different from the set of read and write instructions native to the system in which the counter is located, wherein the read and write instructions included are privileged instructions.
Further, the apparatus further comprises a Salt register:
the Salt register is used for storing a challenge value, the challenge value is used as the other input of the hash function, and the challenge value can only be modified through a preset instruction;
when the operating system of the device carries out process switching, a challenge value stored in a Salt register related to the process switching needs to be saved or restored;
when the process starts, the operating system where the device is located or the compiler corresponding to the device is needed to initialize the value in the Salt register.
Further, the device also comprises a hash calculation module used for executing any hash value generation algorithm;
accordingly, the correct hash value stored in the Salt register cannot be read by instructions other than the pre-privileged instruction.
Further, the verification module is further configured to: and if the return address to be verified is confirmed to be tampered, exception occurs and the program is interrupted.
Further, the verification module is further configured to determine that the return address to be verified is not tampered if the hash value to be verified is the same as the correct hash value generated in advance.
The embodiment of the invention provides a device for detecting the falsification of the return address in the stack, and the return address and the hash value are stored and verified through a chain structure.
Drawings
FIG. 1 is a flowchart illustrating an embodiment of a method for detecting a tamper of a return address in a stack by using an apparatus for detecting a tamper of a return address in a stack;
FIG. 2 is a diagram illustrating a chained hash stack in an apparatus for detecting a tamper in a return address in the stack according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a structure of a chained hash stack in an apparatus for detecting a tamper in a return address in the stack according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a prior art stack configuration according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the difference between the execution of a call instruction and a prior art call instruction in a method for detecting a tamper of a return address in a stack by using an apparatus for detecting a tamper of a return address in a stack according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a difference between a return instruction execution and a prior art return instruction in a method for detecting a tampering of a return address in a stack by using an apparatus for detecting a tampering of a return address in a stack according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating an embodiment of detecting an uncompressed structure and a compressed storage structure of a chain hash stack in a stack;
fig. 8 is a block diagram illustrating an overall architecture of an apparatus for detecting a tamper of a return address in a stack according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
In the following, the present description will first make a clear explanation of the basic concepts and the prior art and the drawbacks.
Memory loopholes: the problem that during the process of writing software, a programmer has time or space design errors on the operation of a memory, so that the program may make behaviors violating the design of the program. The attacker can construct various attacks by using the memory loophole of the program and execute malicious behaviors.
Buffer overflow: the most common memory loophole is that data exceeding the length of a buffer is copied into the buffer, namely, the buffer overflows, so that other data except the buffer is covered. The stack overflow hole is the most common one of buffer overflow holes, that is, an overlong data is copied into the stack, which causes the buffer data on the stack to overflow, thereby covering other critical data on the stack.
Stack (stack): also known as a stack, which is a linear table with limited operations. The limitation is that only insert and delete operations are allowed at one end of the table. This end is referred to as the top of the stack, while the opposite end is referred to as the bottom of the stack. Inserting a new element into a stack, also called pushing, stacking or calling, is to put the new element on the top element of the stack to make it become a new top element of the stack; deleting an element from a stack, also known as popping or popping, deletes the top-of-stack element, making its neighbors a new top-of-stack element.
Stack overflow: is one type of buffer overflow. Overwriting of a useful memory cell due to buffer overflow often causes unpredictable results. During operation, a program generally allocates memory space, which is usually called a buffer, for the temporary data access. If data exceeding the length of the buffer is written into the buffer, so that the buffer cannot accommodate the data, the memory unit outside the buffer is rewritten, and the phenomenon is called buffer overflow. The buffer length is typically related to the type of buffer variable that the user defines himself.
Function calling: when the computer is compiled or run, a function is used to complete the relevant command.
And returning an address: one of the most important data stored in the stack is the function return address. When a function is called, a Call instruction (e.g., a Call instruction) pushes the function return address onto the stack. When the function returns, a Return instruction (e.g., Return instruction) reads the Return address saved in the stack, jumps to the position of the original called function according to the Return address, and continues to execute downwards. The most common method for attacking by using stack overflow vulnerability is to cover the return address by using stack overflow and change the return address into an address set by an attacker. When the function returns, the function jumps to the position set by the attacker, and the code which the attacker wants to execute is executed.
ROP attack: a classical technology for constructing attack behavior by using memory loophole is that because of the popularization of non-executable bit technology (DEP or NX), it is difficult to directly inject code to execute malicious attack, and ROP attack can utilize the code of program itself to use return address as connection to construct attack behavior. The principle of the ROP attack is mainly to use a code segment (becoming an accessory) ending with a Return instruction (e.g., Return instruction) in the code of the program itself, and to continuously enable the program to run the accessory in cooperation with the control of the stack space. When a program executes a Return, the CPU fetches an address from the current stack and jumps to the code pointed to by this address to begin execution. An attacker puts addresses of a series of accessories into a stack, when a CPU runs to Return, the address is taken out and jumps to the accessory to start execution, when the execution of the first accessory is finished, a Return instruction (such as the Return instruction) at the end takes out a second address and jumps to the second accessory to start execution, and the loop is repeated, so that any malicious behavior is constructed.
The key point of attacks such as ROP attacks is to tamper the return address, and some existing technologies also prevent these attacks by protecting the return address. The main relevant jobs are Shadow Stack (Shadow Stack) and Stack protection (Stack cookie, also known as Stack security).
The shadow stack stores a backup of the return address in the stack in another area of the memory through different implementation modes (the memory area is called the shadow stack), the address is compared with the backup before the return address in the stack is used, and if the address is different, the address in the stack is tampered. In short, the essence of the shadow stack is to store a backup of the return address in another location, so that there is no concern that an attacker will modify the return address in the stack. Intel corporation proposed CET Technology (Control-flow implementation Technology) in 2016, which mainly includes two technologies, one of which is a shadow stack.
Stack protection is a practical technique employed in many mainstream compilers, such as the gcc compiler. The return address is saved in the stack, and a canary (i.e., a protection value, which is a random number) is inserted in front of the return address. If an attacker wants to override the return address with stack overflow, the protection value must be overridden. The protection value is a random number that cannot be known by an attacker, and thus the protection value also changes. When the function returns, whether the return address is tampered maliciously can be found by checking whether the protection value is changed.
Then, the above prior art method has the following technical drawbacks.
The shadow stack approach has several problems:
1. the backup in the shadow stack must be absolutely secure, which is very difficult in practical implementations. For example, Intel's CET technology proposes to use a new page attribute to mark individual pages as "shadow stack" pages for protection. But this page attribute can be changed, which was a precedent in previous instances where DEP was bypassed in an actual attack. It is not sufficient to protect a region of memory. If an attacker can modify the return addresses on the shadow stack and the stack at the same time, the protection of the shadow stack can be broken.
2. The backup in the shadow stack requires a single page to store, thus increasing memory access, reducing performance, and also increasing memory overhead.
3. The implementation of the shadow stack is complex. If the safety of the shadow stack is not considered, the design is simpler, but the safety is not enough. If the security of the shadow stack is considered, an additional protection mechanism needs to be added to the memory where the shadow stack is located, so that the design complexity is greatly increased, and the practicability is low.
The stack protection method has several problems:
1. stack protection requires the insertion of a protection value (random number) before the return address. Once an attacker learns the protection value, the return address and the protection value can be easily overwritten while ensuring that the protection value does not change.
2. Stack protection can only protect against stack overflow covering return addresses, but not against other attacks. For example, a return address is modified directly point-to-point using an arbitrary address write.
In summary, neither the shadow stack nor the stack protection is secure enough, and the attacker can still find some way to bypass.
The specific embodiment of the invention provides a method for detecting the tampering of a return address in a stack.
Fig. 1 is a schematic overall flow chart illustrating a method for detecting tampering of a return address in a stack by using a chained hash stack according to an embodiment of the present invention, including:
s1, according to the return address to be verified and the hash value corresponding to the return address to be verified stored in the top frame of the stack in the stack, generating an algorithm based on any hash value to obtain the hash value to be verified;
wherein, the ith frame in the stack stores the ith return address and a random number; any frame from the (i + 1) th frame to the top frame in the stack stores a return address corresponding to the frame and a hash value corresponding to the return address; the hash value corresponding to the return address is obtained based on any hash value generation algorithm according to the return address stored in the previous frame of any frame in the stack and the hash value corresponding to the return address; j is more than i and is more than or equal to 1, wherein j is the serial number of the stack top frame;
s2, if the hash value to be verified is different from the correct hash value generated in advance, confirming that the return address to be verified is tampered; and the correct hash value is obtained in advance according to the return address which is not tampered and the hash value corresponding to the return address which is not tampered of the stack top frame in the stack based on any hash value generation algorithm.
Specifically, embodiments of the present invention utilize a primary hash algorithm to protect the return address. The hash algorithm has unique advantages such as difficulty in reverse-inferring the input of the hash from the output of the hash, and difficulty in an attacker controlling the input to output a desired output value. The invention proposes that both the return address and the hash value are maintained by a chain structure. As shown in fig. 2, the latest Hash value is calculated based on the latest return address (stored in the top frame of the stack) and the previous Hash value (stored in the top frame of the stack). The Hash value in the frame at the top of the stack is calculated according to the return address and the Hash value stored in the previous frame. Thus, the return address and the Hash value in each frame in the stack form a chain.
Fig. 3 shows a stack structure according to an embodiment of the present invention. Compared with the normal stack structure of fig. 4, the stack structure of the embodiment of the present invention stores the return address and the Hash value corresponding thereto in the same frame. It is noted that the Hash value and the return Address stored in the same frame are staggered, i.e. the first return Address (Address 1) and a random number (RAND) are stored together; the first Hash value (Hash 1) is obtained by calculation according to the first return address and the random number and is stored with the second return address; and so on, the second Hash value and the third return address exist together; while the latest Hash value (Hash 3) is stored in a special register (called the Top register). Here, the random number RAND is an initial value of the Top register.
Further, the specific execution processes of the call instruction and the return instruction are described by taking the call instruction and the return instruction as examples in the embodiment of the present invention.
Firstly, the execution process of a normal call instruction and a return instruction is described, and then the execution process of the call instruction and the return instruction in the present invention is described, fig. 5 shows a special process in which the call instruction and the normal execution process are different in the present invention, and fig. 6 shows a special process in which the return instruction and the normal execution process are different in the present invention.
Normal Call instructions (Call instructions) perform: 1) call the return address, 2) store the target address of the Call instruction (Call instruction) into the PC (equivalent to jump to target address execution).
The normal return instruction (return instruction) performs: 1) pop the return address, 2) store the return address in the PC (equivalent to jump to return address execution).
The Call instruction (Call instruction) of the present invention performs: 1) calling the hash value and the return address (the return address of the stack Top frame which is not tampered) in the Top register together, 2) taking the called data (namely the hash value and the return address in the step 1) as the input of a hash function, calculating to obtain a new hash value (a correct hash value), storing the new hash value into the Top register, and 3) storing the target address of a calling instruction (Call instruction) into the PC.
The return instruction (return instruction) of the embodiment of the present invention executes: 1) popping the hash value and the return address (return address to be verified) in the frame at the Top of the stack, calculating the hash value (hash value to be verified) of the popped hash value and the return address (return address to be verified), and 2) comparing the calculated hash value (hash value to be verified) with the hash value (correct hash value) stored in the Top register. If the two are not equal, the abnormal condition is indicated, and the alarm should be given and the program operation should be interrupted. If the two are equal, the execution is normal and continued. 3) The popped hash value is stored in the Top register (popped hash value, not the hash value to be verified). 4) When the hash value to be verified is equal to the correct hash value, storing the return address to be verified in the PC; and when the hash value to be verified is not equal to the correct hash value, generating an exception and interrupting the program.
In another embodiment of the present invention, a method for detecting tampering of a return address in a stack is provided, where the method is used in a processor for executing the method for detecting tampering of a return address in a stack, and the method further includes a Salt register for storing a challenge value, where the challenge value is used as another input of a hash function, and the challenge value can only be modified by a preset instruction.
In another embodiment of the present invention, a method for detecting a tampering of a return address in a stack is provided, where a processor for executing the method for detecting a tampering of a return address in a stack further includes a Salt register, where a stored correct hash value can only be modified by a predetermined instruction; the Salt register is used for storing a hash value corresponding to the return address to be verified, and the correct hash value stored in the Salt register can only be modified through a preset instruction.
In order to implement the foregoing specific embodiment, in practical development, at least one register, including at least a Top register and possibly a Salt register, needs to be added to a processor that executes the method for detecting tampering of a return address in a stack according to the embodiment of the present invention. The Top register is used for storing the latest hash value, and the challenge value stored in the Salt register is another input of the hash function, which is generally a random value or other types of values, so that the difficulty of guessing and breaking the hash function is further increased.
At the very beginning of a process, the Top and Salt registers are set to random numbers or non-random numbers generated by other means, respectively, with random numbers being the most preferred. The hardware should ensure that the correct hash value stored in the Top register and the challenge value stored in the Salt register can only be modified by a preset instruction, otherwise the present invention loses its defensive effect. While protecting several special registers from modification by an attacker is easy to implement. Even if an attacker reads the Salt register, the method can still ensure that the attacker cannot easily tamper with the return address, and still has higher safety.
The hardware need not guarantee that the Top register is not read by an attacker. Whether an attacker can read the Top register has no influence on the safety of the invention.
In another embodiment of the present invention, a method for detecting a return address in a stack being tampered is provided, wherein a challenge value stored in the Salt register and a correct hash value stored in the Top register cannot be read by an instruction other than a privileged preset instruction.
The hardware should try to ensure that the Salt register is not read by an attacker, which is also technically easy to implement. In addition, even if an attacker reads the Salt register, the method can still ensure that the attacker cannot easily tamper the return address, and still has higher safety.
In another embodiment of the present invention, a method for detecting a tampering of a return address in a stack is provided, where the processor for executing the method for detecting a tampering of a return address in a stack further includes a hash calculation module for executing any one of the hash value generation algorithms.
The embodiment of the invention has no more requirements on the selection of the hash algorithm, and can use any hash algorithm, even other encryption and decryption algorithms.
In another embodiment of the present invention, a method for detecting a return address in a stack is tampered, where any return address in the stack and a hash value corresponding to any return address are separately stored in different positions in the same stack frame in the stack. As shown in fig. 7, in the embodiment of the present invention, the return address and the hash value are stored separately and are referred to as an uncompressed structure (or normal structure).
In another embodiment of the present invention, a method for detecting a return address in a stack is tampered, in a 64-bit operating system, any return address in the stack is normally stored in any position in the stack, and a hash value corresponding to any return address is stored in an upper space of any position.
In particular, it has been found that in 64-bit systems, the return address takes 64 bits, but in practice the real return address is not so long, typically only 40 bits. Therefore, the upper 64 bits are idle. Therefore, the hash value can be saved to the upper bits of the 64 bits. This storage structure is called a compressed structure, as shown in fig. 7. The compressed structure differs from the original stack structure only by the value of the return address in the stack (and is completely consistent in layout). This has the major advantage that it is compatible with previous binaries, since most programs follow the following law: (1) the call instruction and the return instruction are matched; (2) only the call instruction and the return instruction use the return address, and other instructions do not use the return address; (3) other values in the stack are positioned according to the offset, and data in other stacks can be directly and correctly used if the layout is maintained. Correspondingly, in order to achieve the above beneficial effects, the operations required to be matched are as follows: the operations required to achieve this goal are: all (or matched parts) of the call instruction and the return instruction in the original program are replaced by the call instruction and the return instruction in the embodiment of the invention, and a compression structure is used. Meanwhile, compared with a non-compression structure, the compression structure has the beneficial effect of saving space.
Of course, in addition to the return address, some data may be stored in the upper 64 bits, such as ASLR's random number, etc. However, in any event, the data does not use up the 64-bit space, and usually leaves 20 bits of free space sufficient to hold the hash value.
In another embodiment of the present invention, a method for detecting a tamper of a return address in a stack is provided, where S2 further includes: and interrupting the program operation and storing the hash value corresponding to the return address to be verified in the Top register.
If the return address to be verified is confirmed to be tampered, the abnormal condition is indicated, an alarm is sent, and the program operation is interrupted.
In another embodiment of the present invention, a method for detecting tampering of a return address in a stack is provided, where if a hash value to be verified is the same as a pre-generated correct hash value, it is determined that the return address to be verified has not been tampered.
In another embodiment of the present invention, a method for detecting tampering of a return address in a stack is provided, which is used in a processor for executing the method for detecting tampering of a return address in a stack, and further comprises a counter for incrementing a count when a Call instruction (e.g., a Call instruction) is executed on the stack and decrementing the count when a return instruction (e.g., a return instruction) is executed on the stack; when the process is finished, if the counting number of the counter is not 0 or the correct hash value in the Top register is modified, an error is reported.
In the specific embodiment of the invention, the situation that an attacker has extremely strong capability and infinite computing capability is considered, so that the attacker can forcibly tamper with the return address through hash collision and construct the same hash value. For such extreme cases, the embodiment of the present invention still finds that an attacker cannot control the value of the Top register, cannot ensure that the value of the Top register after the attack is ended is the same as the initial value, and thus inevitably leaves a trace of the attack.
In the embodiment of the invention, a Number counter is added to record the execution times of the call instruction and the return instruction, so that the Number of the call instruction and the return instruction is ensured to be the same. The process starts, and a Number counter is initialized to 0; executing a call instruction once, and adding one to the count number; executing a return instruction once, and reducing the count number by one; if the process is finished, the number should be 0, otherwise, an error is reported, and the program operation is terminated.
Similarly, when the process finishes exiting, the value of the Top register should be equal to the initial value of the Top register when the process starts, otherwise, the attack is considered to occur, an error is reported, and the operation is terminated.
If the process is considered to be possible to quit halfway, the values of the Top register and the Number register are also required to be saved and monitored, and the values of the Top register and the Number register are ensured to be matched when the process quits halfway.
As shown in fig. 8, an overall block diagram of an apparatus for detecting a return address in a stack according to the present invention is shown, and generally includes:
the hash value calculation module A1 is used for generating an algorithm based on any hash value according to the return address to be verified and the hash value corresponding to the return address to be verified, which are stored in the top frame of the stack in the stack, so as to obtain the hash value to be verified;
wherein, the ith frame in the stack stores the ith return address and a random number; any frame from the (i + 1) th frame to the top frame in the stack stores a return address corresponding to the frame and a hash value corresponding to the return address, wherein the hash value corresponding to the return address generates an algorithm based on the hash value according to the return address stored in the previous frame of the frame and the hash value corresponding to the return address in the stack, and the obtained hash value is obtained; j is more than i and is more than or equal to 1, wherein j is the serial number of the stack top frame;
the verification module A2 is used for confirming that the return address to be verified is tampered if the hash value to be verified is different from the correct hash value generated in advance; the correct hash value is obtained in advance according to an untampered return address of a stack top frame in a stack and a hash value corresponding to the untampered return address based on any hash value generation algorithm;
the Top register A3 is used for storing the correct hash value, and the correct hash value stored in the Top register A3 can only be modified by a preset instruction;
an instruction set including at least a set of call instructions and return instructions different from those native to the system in which the stack is located for performing call and return operations in the stack.
On the basis of the original call instruction and ret instruction, adding a new type of call instruction and return instruction to complete corresponding operation;
or adding two new instructions, wherein each new instruction and one original instruction form a new calling instruction or a return instruction.
For example, a pcall may be used instead of call, pret instead of ret (name is arbitrary); it is also possible to use call + pac instead of call and pbr + ret instead of ret. Wherein, call and ret are original instructions of the instruction set, and the others are newly added instructions. Both methods can fulfill the corresponding requirements.
On the basis of any of the above embodiments of the present invention, there is shown an apparatus for detecting a return address in a stack being tampered, the apparatus further comprising:
the counter is used for adding one to the count when the stack executes a calling operation and subtracting one from the count when the stack executes a return operation; when the process is finished, if the counting number of the counter is not 0 or the correct hash value in the Top register is modified, an error is reported.
In addition to any of the above embodiments of the present invention, there is shown an apparatus for detecting tampering of a return address in a stack, which includes at least a set of instructions different from a call instruction and a return instruction native to a system in which the stack is located, wherein the call instruction and the return instruction are privileged instructions.
On the basis of any of the above embodiments of the present invention, there is shown an apparatus for detecting a tamper of a return address in a stack, which includes at least one instruction set different from a set of a read instruction and a write instruction native to a system in which the Top register is located, for performing a read operation and a write operation in the Top register; and at least one instruction set containing a set of read instructions and write instructions different from those native to the system in which the Top register is located, wherein the read instructions and the write instructions are privileged instructions.
On the basis of any of the above embodiments of the present invention, there is shown an apparatus for detecting a tamper of a return address in a stack, at least including a set of instructions different from a read instruction and a write instruction native to a system in which the counter is located, for performing a read operation and a write operation in the counter; at least one set of instructions is included that is different from the set of read and write instructions native to the system in which the counter is located, the read and write instructions included in the set of instructions being privileged instructions.
On the basis of any of the above embodiments of the present invention, there is shown an apparatus for detecting a return address in a stack being tampered, further comprising a Salt register:
the Salt register is used for storing a challenge value which is used as the other input of the hash function and can only be modified by a preset instruction.
On the basis of any of the above embodiments of the present invention, a device for detecting a tamper of a return address in a stack is shown, further comprising a hash calculation module for executing any one of the hash value generation algorithms;
accordingly, the correct hash value stored in the Salt register cannot be read only by a corresponding preset instruction.
On the basis of any of the foregoing embodiments of the present invention, there is shown an apparatus for detecting a return address in a stack being tampered, where the verification module is further configured to: and if the return address to be verified is confirmed to be tampered, interrupting the running of the program and storing a hash value corresponding to the return address to be verified in the Top register.
On the basis of any of the above embodiments of the present invention, a device for detecting that a return address in a stack is tampered is shown, where the verification module is further configured to determine that the return address to be verified is not tampered if the hash value to be verified is the same as a pre-generated correct hash value.
In another embodiment of the present invention, an apparatus for detecting a tampering of a return address in a stack is provided, where the processor for executing the method for detecting a tampering of a return address in a stack further includes a Top register and a Salt register:
the Top register is used for storing the correct hash value, and the stored correct hash value can only be modified through a preset instruction;
the Salt register is used for storing a hash value corresponding to the return address to be verified, and the correct hash value stored in the Salt register can only be modified through a preset instruction.
In order to make the above invention really applied to real systems, support of various aspects such as a compiler, an operating system and the like is also needed. The operating system needs to know the existence of several special registers (including the Top register and the Salt register, etc.). At the start of each process, the values of these registers are initialized, set to random numbers. When the processes are switched, the values of the registers are saved, and each process is ensured to have own related information and not to influence each other. The compiler also needs to know these special registers. In the case of the non-compressed architecture, the compiler is required to add some code for the operation to use these registers. In the case of a compressed structure, the compiler needs to know the specific layout of the 64-bit return address, which bits are the return address and which bits are the hash value, so that the compiler can add special processing codes to the program conveniently. The invention may also be implemented using a compiler (without hardware support) if the compiler has sufficient support. However, the efficiency achieved in this way is lower than that achieved with pure hardware, with a performance loss of about 3%.
The invention has high flexibility and compatibility. For example, a multi-chain structure is adopted, and different chains are adopted for protection every certain number of return addresses; some addresses are protected and some are not. Thereby increasing the difficulty of cracking by attackers. The invention is also not in conflict with other defense methods and can be used in combination.
Compared with other technologies, the embodiments of the present invention adopt a chain technology, that is, the return address and the hash value are connected as a chain, which is the most core idea of the present invention. The present invention protects the return address using hash calculations, which have unique advantages. For example, knowing the final hash value, it is difficult to derive the original value from this. It is noted, however, that there is still the possibility of replacing the hashing algorithm with another encryption/decryption algorithm. The chain hash brings various advantages such as high security, low performance loss, low design complexity and the like.
Meanwhile, the embodiment of the invention is superior to the existing method in the aspects of safety, performance, design complexity, compatibility, practicability and the like. The present invention is superior in some respects to a particular technique, while other aspects can ensure that it is not inferior to that technique.
Firstly, the invention can strictly ensure that the return address cannot be maliciously tampered, and the security is higher than that of other methods. For example, the shadow stack cannot avoid that the backup data of the shadow stack is not modified, and the stack protection cannot avoid leakage of a protection value.
Second, according to the experiments, the performance loss of the present invention using hardware support is only 0.15%, lower than the existing methods.
In terms of hardware, the invention only needs to add a plurality of registers and a hash operation module, has low design complexity and is easy to realize. Other approaches, such as shadow stacks, may require modifications to the page table management mechanism, which is significantly more complex than the present invention.
The invention has high universality and can be used for any mainstream computer system. Function calls and returns are the most basic program functions that are supported by all computers, and the present invention can be used with all computer systems that support function calls and returns.
The invention has high compatibility and little change to the system, and can be well added into the existing computer system.
In summary, the present invention is a very practical technique that can be easily applied to real systems.
In addition, the invention has some unique advantages. For example, once an attack is successful, existing defense methods cannot be found. The invention can be cracked by an attacker, but the attacker can leave attack traces and can be found by the attacker.
Finally, the method of the present application is only a preferred embodiment and is not intended to limit the scope of the embodiments of the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.
Claims (8)
1. An apparatus for detecting a return address in a stack being tampered, comprising a hash value calculation module, a verification module, and a Top register:
the hash value calculation module is used for generating an algorithm based on any hash value according to the return address to be verified and the hash value corresponding to the return address to be verified, which are stored in the top frame of the stack in the stack, so as to obtain the hash value to be verified;
wherein, the ith frame in the stack stores the ith return address and a random number; any frame from the (i + 1) th frame to the top frame in the stack stores a return address corresponding to the frame and a hash value corresponding to the return address, wherein the hash value corresponding to the return address is a hash value obtained by generating an algorithm based on the hash value according to the return address and the hash value corresponding to the return address stored in the previous frame of the frame in the stack; j is more than i and is more than or equal to 1, wherein j is the serial number of the stack top frame;
the verification module is used for confirming that the return address to be verified is tampered if the hash value to be verified is different from the correct hash value generated in advance; the correct hash value is obtained in advance according to an untampered return address of a stack top frame in a stack and a hash value corresponding to the untampered return address based on any hash value generation algorithm;
the Top register is used for storing the correct hash value, and the correct hash value stored in the Top register can only be modified through a preset instruction;
said device comprising at least one set of instructions, different from the call and return instructions native to the system in which said stack is located, for performing call and return operations in the stack;
when the operating system where the device is located switches processes, the correct hash value stored in the Top register involved in the process switching needs to be saved or restored;
in the compiler corresponding to the device, it is necessary to ensure that instructions for executing call and return operations in the stack appear in pairs in an instruction set different from the native call instruction and return instruction in the system in which the stack is located;
when a process starts, a value in a Top register needs to be initialized based on an operating system where the device is located or a compiler corresponding to the device.
2. The apparatus of claim 1, further comprising:
the counter is used for adding one to the count when the stack executes a calling operation and subtracting one from the count when the stack executes a return operation; when the process is finished, if the counting number of the counter is not 0 or the correct hash value in the Top register is modified, an error is reported.
3. The apparatus of claim 1, wherein a call instruction and a return instruction included in the set of instructions are privileged instructions.
4. The apparatus of claim 1, wherein the apparatus comprises at least one instruction set for performing a read operation and a write operation in the Top register, the instruction set being different from a set of read instructions and write instructions native to a system in which the Top register is located; the read and write instructions included therein are privileged instructions.
5. The apparatus of claim 2, comprising at least one set of instructions, different from the read and write instructions native to the system in which the counter resides, for performing read and write operations in the counter; the read and write instructions included therein are privileged instructions.
6. The apparatus of claim 1, further comprising a Salt register:
the Salt register is used for storing a challenge value, the challenge value is used as the other input of the hash function, and the challenge value can only be modified through a preset instruction;
when the operating system of the device carries out process switching, a challenge value stored in a Salt register related to the process switching needs to be saved or restored;
when a process starts, the value in the Salt register needs to be initialized based on the operating system where the device is located or the compiler corresponding to the device.
7. The apparatus of claim 1, wherein the verification module is further configured to: and if the return address to be verified is confirmed to be tampered, exception occurs and the program is interrupted.
8. The apparatus according to claim 1, wherein the verification module is further configured to determine that the return address to be verified has not been tampered with if the hash value to be verified is the same as the correct hash value generated in advance.
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