CN109408026A - Full adder based on memristor RRAM - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The invention provides a full adder based on a memristor RRAM, which can obtain a three-terminal voter logic by applying voltages at two ends of the memristor through a time sequence relation and applying a state value originally stored by the memristor, and the voter logic of the memristor is provided with a non-logic, so that the simple operation can realize complex operation logic, and the one-bit and multi-bit full adder is realized.
Description
Technical field
The present invention relates to non-volatility memorizer calculating fields, in particular to a kind of to be based on electric resistance changing random access memory
The full adder of (RRAM, Resistive Random Access Memory, abbreviation resistance-variable storing device).
Background technique
With memristor continuous development and von Neumann bottleneck it is continuous significant, storage and calculating integration are continuous
Mentioned by major scholar, in recent years, with the continuous intensification recognized memristor, not only stays in and regarded now
Come for a kind of novel storage material using potential of the memristor in terms of logical operation is constantly excavated.
After Hewlett-Packard proposes to contain logic, the research of the logical operation based on memristor starts to flourish, constantly
There is scholar to propose different improvement project and other new logical algorithms to improve the number of unit of the efficiency and device of operation,
With alleviate operation and storage between speed wide gap, still, for current research, be also merely resting on one-bit full addres with
And its on simpler logical foundations, seldom it is related to complex logic operation, this is because these logics fortune designed at present
It is complicated for operation, it is unable to concurrent operation, high to the uniformity requirements of device, this is also counteracted currently based on memristor logical operation
Development, it is difficult to realize the full adder of multidigit.
Summary of the invention
In view of above-mentioned technical problem, the purpose of the present invention is to provide a kind of full adders based on RRAM, new using one kind
The algorithm logic of type and novel adder framework allow memristor efficiently to realize multidigit full adder.
It is traditional that realize that logical operation generallys use using memristor is the differentiation body for containing logic and containing logic,
That is the mode of electric resistance partial pressure, and one-bit full addres are realized in the form of traditional and-or inverter logic, in the present invention, no longer
Using traditional and-or inverter logic but full adder operation is realized using voting machine logic.
According to an aspect of the invention, there is provided a kind of full adder based on memristor RRAM, the full adder is one
Position full adder realizes full adder operation, expression formula using voting machine logic are as follows:
Wherein, S is expressed as one's own department or unit and signal, C0It is expressed as carry signal, Ci, B, A be expressed as three input signals, M is represented
Be a voting machine logic, corresponding result be three two two-phases of parameter with after again phase or result.
In certain embodiments of the present invention, the one-bit full addres need three memristor units, and operating procedure is such as
Under:
The first step, the resistance value of initialization memristor unit to high-impedance state；
Second step changes the value that stores in memristor and carries out first time write operation, respectively in three memristor units according to
Secondary write-in B, B and A；
Third step continues write operation to obtain to high-order carry signal value C0；
4th step obtains one's own department or unit and signal S by write operation.
In certain embodiments of the present invention, first step operation is omitted by overall situation initialization.
In certain embodiments of the present invention, the digital control module of the one-bit full addres completes it in each write operation
It carries out a read operation therewith afterwards, the data of reading is compared with the data to be written, if identical, it was demonstrated that this writes behaviour
Succeed, can sequentially carry out write operation next time, if it is different, will continue to carry out last time write operation, meanwhile, pulse width will
Increase a clock cycle, and successively go on, when the value and write operation that pulse width has been set to one greatly do not have still
There is accurately writing data, the digital control module prompts the unit to be damaged outward.
In certain embodiments of the present invention, the full adder is 8-bit full adder, using the original of cascaded carry addition
Then, the described in any item one-bit full addres of claim 1-4 are constantly called to realize 8-bit full adder.
In certain embodiments of the present invention, the full adder is n-bit full adder, using 8m-bit full adder as base
This arithmetic element, wherein m is the natural number more than or equal to 1, every 8m-bit equal part is pressed in input, each full adder is according to every 8m
Position add entirely, and in addition to the full add operation of the first order, full add operation later all can be 0 to the carry signal of previous stage and be 1
Operation is carried out simultaneously, to obtain two operation results, after the full add operation operation of the 8-bit of the first order, obtains C8 signal,
According to the value of C8, select the right value of C16 and S [15:8] by a multiple selector, then by C16 selection C24 and S [23:
16] positive value, successively derives backward.
(3) beneficial effect
It can be seen from the above technical proposal that a kind of full adder based on RRAM of the present invention at least has the advantages that
One of them:
(1) due to being calculated based on voting machine logic when, there is no multiple memristor units are concatenated in operating process
Situation, thus it is not high to the coherence request of device, in addition, voting machine logic has fine compared to existing logical algorithm
Concurrency, i.e., can also carry out write operation simultaneously in multiple units simultaneously.This that is, in terms of the pursuit of high speed,
Voting machine logic will have bigger application prospect.Although using voting machine logic carry out logical operation when peripheral circuit compared to
Existing logic can be more complicated, but he can by extension computing unit and each shared peripheral reading circuit of column into
Row optimization；Wherein show that voting machine logic has very big advantage in terms of step and area, is realizing complex logic Shi Nengjia
Fast schedule speed and the number for reducing memristor unit；
(2) the multidigit full adder in the present invention be based on 8-bit ripple adder, and it is enterprising in calculative strategy
Go corresponding optimization, the step number of 8-bit full adder execution needed for operation of the invention and required memristor unit
Tool has great advantage in number.
Detailed description of the invention
Fig. 1 is the realization logic diagram of one-bit full addres of the embodiment of the present invention.
Fig. 2 is the realization microoperation schematic diagram of one-bit full addres of the embodiment of the present invention.
Fig. 3 is write verification of embodiment of the present invention operating impulse figure.
Fig. 4 is the parameter comparison schematic diagram that the Different Logic based on memristor realizes one-bit full addres.
Fig. 5 is the realization logic diagram of 8-bit of embodiment of the present invention full adder.
Fig. 6 is the realization microoperation schematic diagram of 8-bit of embodiment of the present invention full adder.
Fig. 7 is 8-bit of embodiment of the present invention full adder test process resistance variations figure.
Fig. 8 is the parameter comparison schematic diagram for the 8-bit full adder realized based on Different Logic.
Fig. 9 is the realization structural schematic diagram of multidigit of embodiment of the present invention full adder.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
In an exemplary embodiment of the present invention, a kind of full adder based on memristor RRAM is provided.Fig. 1 is the present invention
The realization logic diagram of embodiment one-bit full addres.As shown in Figure 1, be one-bit full addres the present invention is based on the full adder of RRAM,
Full adder operation is realized using voting machine logic.
It is voting machine logic by the logical transition based on and-or inverter,
In addition, by one's own department or unit and signal for giving full adder in formula 1.1 and formula 1.2 and carry signal and three input signals
Between relationship, by the way that voting machine logical AND adder relational expression is blended, can be utilized voting machine logic come it is real
The expression formula relationship of existing adder logic, and abbreviation has been carried out to it, concrete implementation relationship is as shown in formula 1.3 and formula 1.4.
Wherein, Ci, B, A be respectively input signal, S is one's own department or unit and signal, C0For carry signal, what M was represented is once to decide by vote
Device logic, corresponding result be three two two-phases of parameter with after again mutually or as a result, R is its corresponding memristor unit,
What three variables in bracket were corresponding in turn to is top electrode signal, the data of original storage, lower electrode signal.Above formula bracket
Interior variable sequence is not have influential on operation result, can clearly be found by above formula, three input signal phase inequalities
Or obtained one's own department or unit and signal S can be realized by the voting machine logic of two steps, and carry signal C0A step table can be passed through
Certainly device logic is realized, and the result of this single stepping is also exactly solving a step required for one's own department or unit and signal S, therefore
It can save and implement operational step.It is available to go to realize add operation using voting machine logic based on the formula
Specific block diagram, as shown in Figure 1, its corresponding microoperation is as shown in Figure 2.What Fig. 1 left figure indicated is to utilize voting machine logic institute
One's own department or unit of realization and and high-order carry value, and right figure is then the one's own department or unit realized using memristor unit and and high-order carry value.
Wherein, what three oblique lines below R circle respectively represented from left to right be the value that top electrode signal, memristor stored originally and under
Electrode signal, what the oblique line above R circle represented is that apply the value after voltage be also the knot after each arithmetic operation to memristor
Fruit value.In first layer, obtained output signal is followed successively by from left to rightM(Ci,B,A),R(Ci,B,A),Wherein the signal of right sided cell output is carry signal C0, one's own department or unit and signal S are all obtained in the second layer, the operation
It is corresponding with equation 1 above .3 and formula 1.4.In Fig. 1, realize that an one-bit full addres need in total using the thought of voting machine
3 memristor units are wanted, in Fig. 2, primary full add operation is can be completed in 4 operating procedures.Wherein the first step is that initialization is recalled
The resistance value for hindering device unit arrives high-impedance state, for convenience subsequent operation, second step be by the value that stores in change memristor into
Row first time write operation, is sequentially written in B, B and A in three memristor units respectively, third step be to continue with carry out write operation from
And it obtains to high-order carry signal value C0, the 4th step is that one's own department or unit and signal S are obtained by write operation, wherein what the 4th step applied
The resistance state of R1 and R2 determines after voltage value is operated by third step.Furthermore, it is possible to first step operation is omitted by overall situation initialization,
To only need the operation of three steps that can realize the full adder in total.
About the digital control module of one-bit full addres, the code of Front-end Design is realized using Verilog language,
Successful process is not write since a write operation often occurs for RRAM itself, i.e. a upper/lower electrode applies alive mistake
Journey is it is difficult to ensure that operation can be properly completed, and therefore, increase a write verification process, concrete meaning when design
Are as follows: a read operation can be all carried out therewith after the completion of each write operation, and another reason for this design is memristor
Reading rate is very fast, is not take up emulation and test period substantially, the data of reading is compared with the data to be written, such as
Fruit is identical, it was demonstrated that the success of this write operation can sequentially carry out write operation next time, write if it is different, will continue to progress last time
Operation, meanwhile, pulse width will increase a clock cycle, and successively go on, when pulse width is set to one greatly
Fixed value and write operation is still without accurately writing data, then the unit can be prompted outward to be damaged.It is write by this
The means of verifying, we may insure that data can be correctly written in unit, and write verification process is embodied in such as Fig. 3
It is shown.
Fig. 4 is the parameter comparison table that the Different Logic based on memristor realizes one-bit full addres, as shown in figure 4, utilizing this
The voting machine logic of invention realizes one-bit full addres, executes that step is minimum, required memristor number is minimum, does not generate structure
Variation, coherence request are low.
In certain embodiments, full adder is that 8-bit full adder can use string for a 8-bit full adder
Traveling position adder designs also can use carry lookahead adder design, due to consideration that going to realize using memristor itself
Logic wants more complex compared to CMOS, it is preferred to use be cascaded carry addition principle carry out the design of 8-bit full adder with
It realizes, block diagram is as shown in Figure 5.Wherein, defining its input signal is respectively A [7:0] and B [7:0], and Ci is i-th bit upward one
The carry signal value of position, other and so on.Cascaded carry is by the way that the carry output signals Cout of low level to be immediately communicated to
The high-order end input signal Cin makes high-order completion successively full add operation.The maximum feature of ripple adder is any position
Each operation have to wait for the carry signal that low level passes over, therefore the transmitting of carry signal is serial transmission.Such as Fig. 6
It is shown, it gives and removes the step of realizing 8-bit full adder figure using voting machine logic.Wherein, every in step shown in fig. 6
One step is omitted the process for how going generating carry signal and one's own department or unit and signal, and concrete operations are exactly complete according to above-mentioned one
Add the such separate operations of device, because all being initialized to all units before integrated operation, is realizing
Initialization procedure in single add operation step can be omitted, to save the time of operation, in addition, adder can also be with
It is recycled, to save the area of experiment.
The digital control codes that 8-bit full adder is realized want more more complicated for one-bit full addres, but its
Understanding in process is gem-pure.As can be seen from FIG. 5,8-bit full adder is due to the original using cascaded carry addition
Reason realizes that the essence of process is exactly the continuous process for calling one-bit full addres, and the only full add operation of current first order section is completed
Afterwards, flag bit is set to height, obtains carry signal, and the full add operation of next stage can just be gone on smoothly, and successively sequence executes
All one-bit full addres can complete the realization of a 8-bit full adder.
8-bit full adder control logic occupy FPGA resource be also it is considerably less, it includes register and look-up table
Number also only only have it is several hundred, if the number of the occupied gate circuit of control logic will using the design of ASIC
It can be more few.
For 8-bit full adder, the test voltage sequence for enumerating him is relatively complicated, but gives 8-bit in Fig. 7
The variation diagram of full adder each resistance during the test, wherein the resistance changed in operation is carried out with underscore
Mark, step also correspond to Fig. 6, and wherein input data A and B is respectively equal to 01011010 and 10101111, full adder
Be not multiplexed, it can be understood as every three memristor units realize it is primary complete plus namely R1, R2, R3 tri- realizations the
One step adds entirely, and R4, R5, R6 realize the full add operation of second step, later and so on.Final test result is stored in order
In R23, R22, R19, R16, R13, R10, R7, R4, R1, can also be expressed as out [8:0]=R23, R22, R19, R16,
R13, R10, R7, R4, R1 }.
Fig. 8 is the parameter comparison table for the 8-bit full adder realized based on Different Logic, as shown in figure 8, the present invention uses
Voting machine logic realizes 8-bit full adder, and performed step significantly reduces, and the area of the memristor utilized is obviously reduced.
In certain embodiments, in order to realizing the full add operation in the case that bit wide is bigger, simple serial addition
It would become hard to go to meet the requirement designed again, a kind of better strategy is to carry out part by pre-supposing that the value of carry signal
Operation, after true carry signal calculates by selection can really be exported as a result, its concrete operations such as
Shown in Fig. 9.The design scheme of the multidigit full adder according to shown in Fig. 9 is it is found that by basic 8-bit full adder and multichannel
The calling of selector is so as to realizing the realization of n-bit full adder.
Arithmetic element as described in Figure 9 is the full adder based on 8-bit, and each 8-bit full adder is complete by 8 one
The ripple adder for adding device series connection constituted.For the multidigit full adder described in Fig. 9, when needing two signals of operation
A [n-1:0] and B [n-1:0] it is complete value added when, actual operation will be inputted by every 8-bit equal part, then each full adder
It is add entirely according to every 8, also, all 8-bit full adders are all run simultaneously, from the point of view of bandwidth,
It can be run in the ladder time, namely when the multiple selector of the first order is just opened, the full add operation of the second level is just completed,
Subsequent and so on.In addition to the full add operation of the first order, full add operation later all can be 0 He to the carry signal of previous stage
Operation is carried out simultaneously for 1, to obtain two operation results, after the full add operation operation of the 8-bit of the first order, obtains C8 letter
Number, according to the value of C8, the right value of C16 and S [15:8] are selected by a multiple selector, then C24 and S is selected by C16
The positive value of [23:16], successively derives backward, although intermediate produce redundancy logic and redundant area, the speed of operation is big
It improves greatly.Its overall operation time is T8-bit add+ (n/8) TMUX, and wherein T8-bit add indicates that a 8-bit is complete
Add the calculating time of device, TMUX indicates multiple selector itself and the delay on path, and n indicates the bit wide of input signal.For
When bigger input bit wide, in order to avoid series is too many, select the full adder of 16-bit as basic unit, to reduce multichannel
Delay on selector path.
N-bit full adder is equally illustrated in terms of two.When not using any optimization policy, and use completely
When concatenated form goes to realize the full adder of n-bit, required operating procedure is (3*n+1), this is because needing a step by two
In a addend write-in memristor and other units are initialized simultaneously, furthermore each add operation needs 3 steps in total, because
This, completes the n-bit in total and required step is added to be exactly (3*n+1) entirely.For unit number needed for the adder, when examining
Considering adder unit can be recycled, and it is that (n+3) is a that required number of unit, which is minimum, when (n-1) bit arithmetic knot
Produced after beam a one's own department or unit (n-1) and with 1 carry signal, furthermore need again three units can complete n-th complete plus
Operation, therefore, required number of unit is that (n-1+1+3)=(n+3) is a in total, still, if intermediate result all saved,
3n unit is then at most needed, this depends on whether recycling unit of full adder, but if using scheme shown in Fig. 9,
After every 8-bit operation, carry signal obtained by calculation come indicate which adder array be calculate right value, which
One be it is wrong, corresponding address information is write back into controller.For this design, required step is (3*8+1=
25) step, additionally include by judging that the value of carry signal selects which adder array obtains correct calculated value, and by its
The time for writing back controller judges that the time write back also will increase, but be corresponding to (3*n+ above when n is bigger accordingly
1) time still substantially reduces.The number of unit of memristor, and go to consider from minimum and most two kinds of situations, at least
In the case of be (2n/8-1) * (8+3)=unit of (n/4-1) * 11, be (2n/8-1) * (8*3)=6n-24 in most situations
Unit.
So far, attached drawing is had been combined the present embodiment is described in detail.According to above description, those skilled in the art
There should be clear understanding to a kind of full adder based on RRAM of the present invention.
It should be noted that in attached drawing or specification text, the implementation for not being painted or describing is affiliated technology
Form known to a person of ordinary skill in the art, is not described in detail in field.In addition, the above-mentioned definition to each element and method is simultaneously
It is not limited only to various specific structures, shape or the mode mentioned in embodiment, those of ordinary skill in the art can carry out letter to it
It singly changes or replaces.
Algorithm and display are not inherently related to any particular computer, virtual system, or other device provided herein.
Various general-purpose systems can also be used together with teachings based herein.As described above, it constructs required by this kind of system
Structure be obvious.In addition, the present invention is also not directed to any particular programming language.It should be understood that can use various
Programming language realizes summary of the invention described herein, and the description done above to language-specific is to disclose this hair
Bright preferred forms.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that implementation of the invention
Example can be practiced without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this specification.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (6)
1. a kind of full adder based on memristor RRAM, which is characterized in that the full adder is one-bit full addres, using voting machine
Logic realizes full adder operation, expression formula are as follows:
Wherein, S is expressed as one's own department or unit and signal, C0It is expressed as carry signal, Ci, B, A be expressed as three input signals, what M was represented is
Voting machine logic, corresponding result be three two two-phases of parameter with after again phase or result.
2. full adder according to claim 1, which is characterized in that the one-bit full addres need three memristor units,
Its operating procedure is as follows:
The first step, the resistance value of initialization memristor unit to high-impedance state；
Second step changes the value progress first time write operation stored in memristor, successively writes in three memristor units respectively
Enter B, B and A；
Third step continues write operation to obtain to high-order carry signal value C0；
4th step obtains one's own department or unit and signal S by write operation.
3. full adder according to claim 2, which is characterized in that omit first step operation by overall situation initialization.
4. full adder according to claim 2, which is characterized in that the digital control module of the one-bit full addres is each
Write operation carries out a read operation after completing therewith, and the data of reading are compared with the data to be written, if identical,
It proves the success of this write operation, can sequentially carry out write operation next time, if it is different, will continue to carry out last time write operation, together
When, pulse width will increase a clock cycle, and successively go on, when pulse width greatly to one set value simultaneously
And write operation, still without accurately writing data, the digital control module prompts the unit to be damaged outward.
5. a kind of full adder based on memristor RRAM, which is characterized in that the full adder is 8-bit full adder, using serial
The principle of carry addition constantly calls the described in any item one-bit full addres of claim 1-4 to realize 8-bit full adder.
6. a kind of full adder based on memristor RRAM, which is characterized in that the full adder is n-bit full adder, with 8m-
Bit full adder is as basic processing unit, and wherein m is the natural number more than or equal to 1, every 8m-bit equal part is pressed in input, each
Full adder is add entirely according to every 8m, and in addition to the full add operation of the first order, full add operation later all can be to previous stage
Carry signal is 0 and is 1 while carrying out operation, so that two operation results are obtained, the full add operation operation knot of the 8-bit of the first order
Shu Hou obtains C8 signal, according to the value of C8, the right value of C16 and S [15:8] is selected by a multiple selector, then pass through
C16 selects the positive value of C24 and S [23:16], successively derives backward.
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| CN112636745A (en) * | 2020-12-18 | 2021-04-09 | 上海交通大学 | Logic unit, adder and multiplier |
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| 陈偕雄: "使用全加器的逻辑设计技术", 《科技通报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636745A (en) * | 2020-12-18 | 2021-04-09 | 上海交通大学 | Logic unit, adder and multiplier |
| CN112636745B (en) * | 2020-12-18 | 2022-11-15 | 上海交通大学 | Logic unit, adder and multiplier |
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