CN109406986A - Test pattern resets control method, device, computer equipment and storage medium - Google Patents
Test pattern resets control method, device, computer equipment and storage medium Download PDFInfo
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- CN109406986A CN109406986A CN201811183966.8A CN201811183966A CN109406986A CN 109406986 A CN109406986 A CN 109406986A CN 201811183966 A CN201811183966 A CN 201811183966A CN 109406986 A CN109406986 A CN 109406986A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
This application involves a kind of test patterns to reset control method, device, computer equipment and storage medium, wherein this method comprises: the reset obtained in test pattern controls request；It is controlled and is requested according to the reset, test pattern is entered by switching signal；Generate internal reset signal；According to the internal reset signal, Global reset is carried out to internal logic circuit.The test pattern that the present invention realizes no external reset pin IC design resets control, since the time point of circuit reset in test mode can be predicted and controllable, so that testing time arrangement is compact, and then save testing time and testing cost, facilitate chip problem quickly to be positioned, achievees the purpose that efficient test.
Description
Technical field
The present invention relates to circuit testing technology fields, reset control method, device, meter more particularly to a kind of test pattern
Calculate machine equipment and storage medium.
Background technique
Currently, the test of integrated circuit also faces very more challenges with the continuous development of integrated circuit technique.Example
Such as, in the case where the design of the digital circuit of not external reset signal, how efficiently to be tested, be up for solving
The technical issues of.
In the conventional technology, the reset signal generated during the test with POR IP, however PoR unit is in difference
PVT under the time point resetted done to chip interior logic be different, then to allow batch production each chip normally just
It works after beginningization, can only consider worst corner and reserves longer time margin.Therefore, it is designed in the test pattern of chip
In there will naturally be at least following three problem:
1) reset time point is unpredictable and uncontrollable；
2) test vector design has to reserve longer time margin, virtually increases testing cost；
3) if built-in PoR unit itself is problematic, test item is not gone down at all, can not be to the potential of chip
Defect debug.
Summary of the invention
Based on this, it is necessary to which in view of the above technical problems, providing one kind can be adapted for no external reset pin IC design
Test pattern reset control method, device, computer equipment and storage medium.
A kind of test pattern reset control method, which comprises
The reset obtained in test pattern controls request；
It is controlled and is requested according to the reset, test pattern is entered by switching signal；
Generate internal reset signal；
According to the internal reset signal, Global reset is carried out to internal logic circuit.
Described controlled according to the reset is requested in one of the embodiments, enters test pattern by switching signal
The step of include:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
The step of generation internal reset signal includes: in one of the embodiments,
The TESTMODE signal becomes high level after configuring the test word；
By the width for triggering internal reset signal described in the counter controls of internal preset；
Before entering test pattern, carried out according to logic circuit of the internal reset signal to chip interior global multiple
Position.
Internal logic circuit is carried out complete described according to the internal reset signal in one of the embodiments,
After the step of office resets further include:
After carrying out Global reset to the logic circuit of chip interior according to the internal reset signal, guidance circuit into
Enter corresponding test pattern.
A kind of test pattern repositioning control device, described device include:
Module is obtained, the module that obtains is for obtaining the control request of the reset in test pattern；
Switching module, the switching module are used to be controlled according to the reset and request, and enter test mould by switching signal
Formula；
Generation module, the generation module is for generating internal reset signal；
Reseting module, the reseting module are used to carry out internal logic circuit complete according to the internal reset signal
Office resets.
The switching module is also used in one of the embodiments:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
The generation module is also used in one of the embodiments:
The TESTMODE signal becomes high level after configuring the test word；
By the width for triggering internal reset signal described in the counter controls of internal preset；
Before entering test pattern, carried out according to logic circuit of the internal reset signal to chip interior global multiple
Position.
Described device in one of the embodiments, further include:
Guiding module, the guiding module be used for according to the internal reset signal to the logic circuit of chip interior into
After row Global reset, guidance circuit enters corresponding test pattern.
A kind of computer equipment can be run on a memory and on a processor including memory, processor and storage
The step of computer program, the processor realizes above-mentioned any one method when executing the computer program.
A kind of computer readable storage medium, is stored thereon with computer program, and the computer program is held by processor
The step of above-mentioned any one method is realized when row.
Above-mentioned test pattern resets control method, device, computer equipment and storage medium, by obtaining in test pattern
Reset control request；Then it is controlled and is requested according to the reset, test pattern is entered by switching signal；Generate internal reset
Signal；According to the internal reset signal, Global reset is carried out to internal logic circuit.The present invention is realized by the above method
Test pattern without external reset pin IC design resets control, due to time point of circuit reset in test mode be can
Precognition and controllable and then saves testing time and testing cost so that the testing time arranges compact, facilitate chip problem into
Row quickly positioning, has achieved the purpose that efficient test.
Detailed description of the invention
Fig. 1 is the flow diagram that test pattern resets control method in one embodiment；
Fig. 2 is the signal timing diagram that test pattern resets control method in one embodiment；
Fig. 3 is flow diagram the step of generating internal reset signal in one embodiment；
Fig. 4 is to realize that test pattern resets the logic schematic diagram of control method in one embodiment；
Fig. 5 is the structural block diagram of test pattern repositioning control device in one embodiment；
Fig. 6 is the structural block diagram of test pattern repositioning control device in another embodiment；
Fig. 7 is the internal structure chart of computer equipment in one embodiment.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, and
It is not used in restriction the application.
Illustrate the contents of the present invention in order to apparent, firstly, illustrating the general plotting entirely invented.
In traditional test pattern, if test pattern relies on uncontrollable internal reset signal, test effect will cause
The reduction of rate, if useful signal exceeds spec value in the case of POR is out of joint or extreme corner, even if detecting on ATE
Chip is out of joint also can not clear orientation problem point.And the present invention is a kind of mentality of designing from scratch: being written in chip
It tests after word, original POR output signal is substituted with the internal circuit of customization, the global reset signal generated in this way is effective
Property have and can predict and controllable characteristics, it is possible to reduce the meaningless waiting time of ATE test vector reduces testing cost, avoids subsequent
The problem of positioning caused by waste great effort.
In one embodiment, as shown in Figure 1, providing a kind of test pattern reset control method, this method comprises:
Step 102, the reset obtained in test pattern controls request；
Step 104, according to control request is resetted, test pattern is entered by switching signal；
Step 106, internal reset signal is generated；
Step 108, according to internal reset signal, Global reset is carried out to internal logic circuit.
In the present embodiment, firstly, the reset obtained in test pattern controls request.Then, it is requested according to reset control,
Enter test pattern by switching signal.Then, internal reset signal is generated.Here letter can be passed through by generating internal reset signal
Single counter structure realizes global reset control.Finally, being carried out to internal logic circuit complete according to internal reset signal
Office resets, and guidance circuit enters corresponding test pattern.Obviously time of circuit reset in test mode by means of which
Point can be predicted and controllably, since testing time arrangement is compact, save testing time and testing cost.
In a wherein specific embodiment, according to control request is resetted, test pattern is entered by switching signal
Step includes:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
Specifically, with reference to Fig. 2, under the premise of not increasing existing pad quantity, TESTMODE signal is jumped to from " 0 "
After " 1 ", generate the reset signal built in one with internal circuit according to demand, come POR under alternative functions mode generate it is interior
Portion's reset signal.The signal is used as the Global reset of chip, and be advantageous in that: pulsewidth can be predicted and be can control, the letter generated
Number quality is fine, and does not have correlation with the PVT corner of foundry.
In the present embodiment, request is controlled by the reset obtained in test pattern；Then according to control request is resetted, lead to
It crosses switching signal and enters test pattern；Generate internal reset signal；According to internal reset signal, internal logic circuit is carried out
Global reset.The present embodiment resets control by the test pattern that the above method realizes no external reset pin IC design, by
It can predict in the time point of circuit reset in test mode and controllable, so that testing time arrangement is compact, and then save
Testing time and testing cost, facilitate chip problem quickly to be positioned, have achieved the purpose that efficient test.
In one embodiment, a kind of test pattern reset control method is provided, as shown in figure 3, also wrapping in this method
Include the step of generating internal reset signal:
Step 302, TESTMODE signal becomes high level after configuring test word；
Step 304, pass through the width of the counter controls internal reset signal of triggering internal preset；
Step 306, it before entering test pattern, is carried out according to logic circuit of the internal reset signal to chip interior global
It resets.
Specifically, with reference to Fig. 4, for one of the present embodiment typical case: TESTMODE believes after configuring test word
Number become high level, triggers the width of the counter controls internal reset signal of internal preset, the reset signal of generation is entering
Reset operation is carried out to entire chip before various test patterns.Without the reset generated by built-in uncontrollable PoR unit
Signal reset chip reaches the final purpose for saving testing time and testing cost.
In a specific embodiment, the overall situation is being carried out again according to logic circuit of the internal reset signal to chip interior
After position, guidance circuit enters corresponding test pattern.
In the present embodiment, realize it is controllable to the time point of entire test Schaltkreis eset, i.e. to survey after write-in test word
Examination circuit is resetted, and reset signal width is customizable.Meanwhile in test vector design, do not depended on into test pattern
In the working condition of PoR, without reserving unpredictable time margin, improving the accuracy of control while reducing testing cost.
In addition, normal test item unrestricted can also go on, Ke Yigeng even if the PoR of functional mode itself is problematic
Fast positioning circuit potential problems.
Although it should be understood that Fig. 1,3 flow chart in each step successively shown according to the instruction of arrow,
These steps are not that the inevitable sequence according to arrow instruction successively executes.Unless expressly stating otherwise herein, these steps
Execution there is no stringent sequences to limit, these steps can execute in other order.Moreover, Fig. 1, at least one in 3
Part steps may include that perhaps these sub-steps of multiple stages or stage are not necessarily in synchronization to multiple sub-steps
Completion is executed, but can be executed at different times, the execution sequence in these sub-steps or stage is also not necessarily successively
It carries out, but can be at least part of the sub-step or stage of other steps or other steps in turn or alternately
It executes.
In one embodiment, as shown in figure 5, providing a kind of test pattern repositioning control device 500, the device packet
It includes:
Module 501 is obtained, for obtaining the control request of the reset in test pattern；
Switching module 502, for entering test pattern by switching signal according to control request is resetted；
Generation module 503, for generating internal reset signal；
Reseting module 504, for carrying out Global reset to internal logic circuit according to internal reset signal.
In one embodiment, switching module 502 is also used to:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
In one embodiment, generation module 503 is also used to:
TESTMODE signal becomes high level after configuring test word；
By the width for triggering the counter controls internal reset signal of internal preset；
Before entering test pattern, Global reset is carried out according to logic circuit of the internal reset signal to chip interior.
In one embodiment, as shown in fig. 6, providing a kind of test pattern repositioning control device 500, which is also wrapped
It includes:
Guiding module 505, for according to internal reset signal to the logic circuit of chip interior carry out Global reset it
Afterwards, guidance circuit enters corresponding test pattern.
Specific restriction about test pattern repositioning control device 500, which may refer to reset above for test pattern, to be controlled
The restriction of method processed, details are not described herein.
In one embodiment, a kind of computer equipment is provided, internal structure chart can be as shown in Figure 7.The calculating
Machine equipment includes processor, memory and the network interface connected by system bus.Wherein, the processing of the computer equipment
Device is for providing calculating and control ability.The memory of the computer equipment includes non-volatile memory medium, built-in storage.It should
Non-volatile memory medium is stored with operating system, computer program and database.The built-in storage is non-volatile memories Jie
The operation of operating system and computer program in matter provides environment.The network interface of the computer equipment is used for and external end
End passes through network connection communication.To realize that a kind of test pattern resets control method when the computer program is executed by processor.
It will be understood by those skilled in the art that structure shown in Fig. 7, only part relevant to application scheme is tied
The block diagram of structure does not constitute the restriction for the computer equipment being applied thereon to application scheme, specific computer equipment
It may include perhaps combining certain components or with different component layouts than more or fewer components as shown in the figure.
In one embodiment, a kind of computer equipment is provided, including memory, processor and storage are on a memory
And the computer program that can be run on a processor, processor are realized when executing computer program in above each embodiment of the method
The step of.
In one embodiment, a kind of computer readable storage medium is provided, computer program is stored thereon with, is calculated
The step in above each embodiment of the method is realized when machine program is executed by processor.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the computer program can be stored in a non-volatile computer
In read/write memory medium, the computer program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein,
To any reference of memory, storage, database or other media used in each embodiment provided herein,
Including non-volatile and/or volatile memory.Nonvolatile memory may include read-only memory (ROM), programming ROM
(PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory.Volatile memory may include
Random access memory (RAM) or external cache.By way of illustration and not limitation, RAM is available in many forms,
Such as static state RAM (SRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate sdram (DDRSDRAM), enhancing
Type SDRAM (ESDRAM), synchronization link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM
(RDRAM), direct memory bus dynamic ram (DRDRAM) and memory bus dynamic ram (RDRAM) etc..
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of test pattern resets control method, which comprises
The reset obtained in test pattern controls request；
It is controlled and is requested according to the reset, test pattern is entered by switching signal；
Generate internal reset signal；
According to the internal reset signal, Global reset is carried out to internal logic circuit.
2. test pattern according to claim 1 resets control method, which is characterized in that described to be controlled according to the reset
Request, the step of entering test pattern by switching signal include:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
3. test pattern according to claim 2 resets control method, which is characterized in that the generation internal reset signal
The step of include:
The TESTMODE signal becomes high level after configuring the test word；
By the width for triggering internal reset signal described in the counter controls of internal preset；
Before entering test pattern, Global reset is carried out according to logic circuit of the internal reset signal to chip interior.
4. test pattern according to claim 3 resets control method, which is characterized in that described multiple according to the inside
Position signal, after the step of carrying out Global reset to internal logic circuit further include:
After carrying out Global reset according to logic circuit of the internal reset signal to chip interior, guidance circuit enters phase
The test pattern answered.
5. a kind of test pattern repositioning control device, which is characterized in that described device includes:
Module is obtained, the module that obtains is for obtaining the control request of the reset in test pattern；
Switching module, the switching module are used to be controlled according to the reset and request, and enter test pattern by switching signal；
Generation module, the generation module is for generating internal reset signal；
Reseting module, the reseting module are used to carry out internal logic circuit global multiple according to the internal reset signal
Position.
6. test pattern repositioning control device according to claim 5, which is characterized in that the switching module is also used to:
Lower write-in test word is controlled by switching signal TESTMODE signal in test pattern and enters test pattern.
7. test pattern repositioning control device according to claim 6, which is characterized in that the generation module is also used to:
The TESTMODE signal becomes high level after configuring the test word；
By the width for triggering internal reset signal described in the counter controls of internal preset；
Before entering test pattern, Global reset is carried out according to logic circuit of the internal reset signal to chip interior.
8. test pattern repositioning control device according to claim 7, which is characterized in that described device further include:
Guiding module, the guiding module are used to carry out entirely according to logic circuit of the internal reset signal to chip interior
After office resets, guidance circuit enters corresponding test pattern.
9. a kind of computer equipment including memory, processor and stores the meter that can be run on a memory and on a processor
Calculation machine program, which is characterized in that the processor realizes any one of claims 1 to 4 institute when executing the computer program
The step of stating method.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program
The step of method described in any one of Claims 1-4 is realized when being executed by processor.
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| CN201811183966.8A CN109406986A (en) | 2018-10-11 | 2018-10-11 | Test pattern resets control method, device, computer equipment and storage medium |
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Application publication date: 20190301 |