CN109376376A - A kind of logic ciphering type hardware security guard method based on key door insertion algorithm - Google Patents
A kind of logic ciphering type hardware security guard method based on key door insertion algorithm Download PDFInfo
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Abstract
The logic ciphering type hardware security guard method based on key door insertion algorithm that the invention discloses a kind of, protects IC intellectual property by additional key door XOR.It is a kind of logic hardware Encryption Algorithm, is distorted for resisting IP piracy and chip；It gate circuit and can increase key door according to the algorithm of design on automatic identification original integrated circuit, and change circuit is with the integrated circuit for actively preventing IP piracy.Its effect is embodied in, and user inputs specific key while inputting operation data, and IC chip function is normal；Conversely, the output of hardware belongs to chaos state when illegal user's input error key, exception is used.
Description
Technical field
The present invention relates to computer information safety technique field, especially a kind of logic add based on key door insertion algorithm
Close type hardware security guard method.
Background technique
Integrated circuit is globalization from production is designed into, and some areas are inadequate to the protection of intellectual property, often
It will appear the situation of chip tort of intellectual property rights.The common infringement mode about chip have it is pirate, imitated, abuse, distort, with
It illustrates for specific situation down.
Reverse-engineering: currently used there are two types of technology, one kind is that PCB is reverse-engineered, that is, is having electronic product real
Under the premise of object and circuit board are in kind, resolving inversely is carried out to circuit board using reversed research and development technology means, by existing product
The technological documents such as PCB file, bill of materials (BOM) file, principle map file carry out the reduction of 1:1, then recycle these texts
Part carries out PCB making sheet.Another kind is decryption chip, by certain device and method, directly obtains the text in encryption single-chip microcontroller
Duplication or dis-assembling reference after part.
It is illegal to cross batch sales IC: after some incredible integrated circuit foundries obtain integrated circuit drawing, to seek benefit
Benefit carries out excessively exploitation chip and launches.
It therefore, is very necessary to the maintenance of IC intellectual property by the processing for integrated chip.It generally uses at present
It is digital watermarking and sequence number in the technology of authentication chip piracy, the two principle is similar, and by taking digital watermarking as an example, it is in integrated electricity
The digital watermarking of insertion IP supplier before road intellectual property (IP) publication, after abuse generation, by extracting IP user
The IP digital watermarking of offer confirms the real ownership of IP.However, digital watermarking and sequence number are the technologies of Passive Defence, it can only
After forging generation, in proofing chip copyright in court.In addition, such method needs third party authoritative institution due to the granting of watermark
Record is put on record, there is certain overhead.
It is by calculating each logic gate variable edge value of primary circuit that there are also a kind of for protect chip intellectual property
Method carrys out additional logic gates, here variable edge value be according between key cannot around each other and the case where individually being decoded, sets
It is fixed, under non-ideal condition, it is related to the judgement of np complete problem, and the complexity of algorithm is higher.
Summary of the invention
Technical problem to be solved by the present invention lies in it is hard to provide a kind of logic ciphering type based on key door insertion algorithm
Part method for security protection can protect IC intellectual property by additional crucial door.
In order to solve the above technical problems, the present invention provides a kind of logic ciphering type hardware peace based on key door insertion algorithm
All risk insurance maintaining method, includes the following steps:
(1) every output port expression formula Jing Guo one logic gate is calculated according to the circuit diagram of original unencryption, it will forward
The result of 3 layers of logic gate is recalled as input, and result is recorded；
(2) according to the size of producer's ifq circuit and confidentiality intensity, increased key door number is set.
(3) according to the ratio radom insertion XOR gate of radom insertion door .v file is modified；
(4) each logic gate expression formula and input normal form I in matching step (1) obtained record1I2I3, wherein increasing
Second, third kind of situation Ii=Ii1+Ii2、Ii=Ii1Ii2(i=1,2,3) judges whether to reach thresholding and still has matched insert
Enter mode, be, enter step (5), otherwise, executes step (6)；
(5) it is inserted into strong logic key door in pairs, i.e., according to matching result, is inserted into a pair of secret keys door, modifies .v file；
(6) terminate insertion, modify circuit top.v file.
Preferably, in step (1), the character string needed by canonical matching, i.e. specified logical expression are patrolled required
It collects door and is repeatedly substituted for upper level, the number of plies required until reaching backtracking is that each output is converted into when backtracking requires the number of plies
When the case where input of most original, specifically comprise the following steps:
(11) canonical library is established；
(12) input, output are extracted from C432.v file, file is written in wire logical expression data；
(13) the above logical expression is split, i.e., marks the array after segmentation with a pair of of braces " { } ", includes greatly
Only have a logical symbol, such as {~G1 }, { G1&G2 } for every group in number；
(14) logic gate symbol NOT, AND, XOR, OR, XNOR etc. are indicated, forms dictionary array set；
(15) required out gate formula is taken；
(16) judge the wire type that whether there is on the right of equation, be to be transferred to step (17), otherwise terminate；
(17) wire type is replaced with wordbook element；
(18) judge on the right of equation whether the data in all input array set, be to terminate, be otherwise transferred to step
(16)。
Preferably, in step (2), according to the size of producer's ifq circuit and confidentiality intensity, increased key door is set
Number, table 1 are the number ratio arrangement for defaulting newly-increased XOR gate, and operation result takes 3 multiple；The ratio of radom insertion, usually takes
Key door number 33%, i.e., a pair of strong correlation logic encrypt door, a random key door, and specific distribution is shown in Table 1:
Table 1
Preferably, in step (5), door mode is inserted specifically: operation is automatically inserted into script, and there are two this function parameters,
One for the detection of upper step can be inserted into code position that the satisfaction replacement that the script of strong logical key door position is run out requires as a result, its
Two be the former integrated circuit .v file for needing to modify, and script automation is to .v file operation, i.e., according to the satisfaction obtained before
Desired code position is replaced as a result, deleting original code in the position and being inserted into the modified strong association mentioned with this patent
The hardware identification code of logic encryption feature.
The invention has the benefit that (1) Initiative Defense, protects IP；Copyright owner uses an a set of key of batch
Method so that user inputted on website purchase product ID and product batch number, obtain Personal Unlocking Key；Chip user is necessary
Normal use for chip can be realized by inputting correct key, and when input error key, hardware is locked, is in
Function chaos state；Since copyright owner directly provides legitimate user's key, IP piracy and agency's production are effectively contained
Quotient without permission, excessively production the case where；(2) automatic identification and conversion of gate circuit are realized in canonical matching；Extract normal form
Python script principle: the character string needed by canonical matching, i.e. specified logical expression repeatedly replace required logic gate
Change upper level into, the number of plies required until reaching backtracking；(3) stronger attack tolerant；For IP infringer, due to number of keys
Anti- association attack is difficult to crack the chip keys that product designer provides on the net when key door quantity reaches a timing；(4) high
Effect；Be different from existing hardware additional logic gates encryption implementation method, i.e., with ATPG by np complete problem judge whether by
" prime mode attack " and the method for calculating each variable edge value using detection primary circuit, variable edge value is according to close here
It cannot be used between key around setting the case where individually decoded each other, new departure after backtracking method automatic identification sub-circuit directly
It matches common fixed mode and modifies circuit diagram；(5) effectively key space is big；Scheme preferentially uses alternative manner, i.e., every time
The input for the circuit module to be encrypted is encrypted circuit output, can not be weakened since a pair of secret keys door being added every time
The effect of key is added, therefore attacker can only go to decode by brute force attack, and with of such method insertion door
Number increases, and size of key is presented exponential type and increases.
Detailed description of the invention
Fig. 1 is method flow schematic diagram of the invention.
Fig. 2 is the key door inserted mode schematic diagram that strong associated key door of the invention locks.
Fig. 3 is separate keys gate circuit figure of the invention.
Fig. 4 is half associated key gate circuit figure of the invention.
Fig. 5 is that modified circuit diagram is embodied in the present invention.
Fig. 6 is a specific embodiment of the invention flow diagram.
Fig. 7 is present invention key correct waveform diagram when being 550ns.
The waveform diagram for wrong cipher key that Fig. 8 is the present invention when being 550ns.
Fig. 9 is present invention key correct waveform diagram when being 700ns.
The waveform diagram for wrong cipher key that Figure 10 is the present invention when being 700ns.
Figure 11 is the automatic identification and conversion method flow diagram that gate circuit is realized in canonical of the present invention matching.
Specific embodiment
As shown in Figure 1, Y, which represents to meet, is not up to thresholding, and there are the condition of matching scheme, carry out being inserted into strong logic key
Door；N representative is unsatisfactory for above-mentioned condition, is transferred to end.A kind of logic ciphering type hardware security guarantor based on key door insertion algorithm
Maintaining method includes the following steps:
(1) every output port expression formula Jing Guo one logic gate is calculated according to the circuit diagram of original unencryption, it will forward
The result of 3 layers of logic gate is recalled as input, and result is recorded；
(2) according to the size of producer's ifq circuit and confidentiality intensity, increased key door number is set.
(3) according to the ratio radom insertion XOR gate of radom insertion door .v file is modified；
(4) each logic gate expression formula and input normal form I in matching step (1) obtained record1I2I3, wherein increasing
Second, third kind of situation Ii=Ii1+Ii2、Ii=Ii1Ii2(i=1,2,3) judges whether to reach thresholding and still has matched insert
Enter mode, be, enter step (5), otherwise, executes step (6)；
(5) it is inserted into strong logic key door in pairs, i.e., according to matching result, is inserted into a pair of secret keys door, modifies .v file；
(6) terminate insertion, modify circuit top.v file.
For IP infringer, it is difficult to crack the chip keys that product designer provides on the net, below by way of three kinds of logic adds
Close door type comparison carries out attack resistance intensive analysis, the third scheme that this scheme is taken.
(1) separate keys door scheme
If being referred to as " separate keys door " from a key door to other all key doors without path.Such as Fig. 2 institute
The separate keys intercalation model shown, without the path of K1 to K2, K1 and K2 are independent keys door.I1、I2、I3It is inputted for primary circuit,
K1、K2For key input, out is output.G20 is AND gate.
Attack strategies: attacker can attack rapidly, because key door can be decoded dividually without by other key doors
Influence, such as Fig. 3, input for " 001 " or " 000 " can measure K1 secret key bits for export 0ut1 influence, according to the observation may be used
To be inferred to K1.I1、I2、I3Input, K1、K2For key input, out1, out2 are output.
(2) half associated key door schemes
If there is K1, K2 two such key door, and K2 is on each paths that K1 is exported, referred to as half associated key
Door.It is illustrated in figure 4 half associated key door figure.
Attack strategies: attacker wants to reach determining K2 secret key bits, only when K1 key position influence is weakened, eliminates.And
One kind, which being known as " prime mode attack ", can weaken the influence that K1 influences while improving K2 for output, so that attacker can obtain
To key sequence.Such as Fig. 4, if there is a mode can make G11 be 1, then K1 influences to eliminate.Such mode makes C
=0, A=1.
(3) this programme --- strong associated key door locking
Be not between K1, K2 it is independent, effect is interfered with each other and can not be eliminated, and is not available the one of key of reduction and is come
Attempt out another key.Such as shown in Fig. 2, K1 and K2 polymerize in G20 result.But K2 cannot be eliminated by bypassing K1
K1 is influenced and is individually decoded.For example, influencing to eliminate K1 so that I3=0, but as I3=0, out=0 will made.
Attack strategies: attacker can only use force and crack.
Implementation flow chart is as shown in fig. 6, ifq circuit figure is c499.v, and c499top.v, embodiment includes following step
It is rapid:
Step 1: we match the automatic identification and conversion for realizing gate circuit according to canonical according to ifq circuit c499.v
Algorithm is advanced past 3 logic gates for each 3 layers of input forward trace, calculate and pass through a logic gate every time
Output port expression formula, and record as a result, finding and meet I1I2I3Circuit module.
Extract normal form python script principle: the character string needed by canonical matching, i.e. specified logical expression, it will
Required logic gate is repeatedly substituted for upper level, the number of plies required until reaching backtracking.Specific embodiment citing --- C432.v
Circuit realizes that the equation right side of 7 final outputs is converted into 36 combinations initially entered, and process is as shown in figure 11, including with
Lower step:
(1) canonical library is established.
(2) input, output are extracted from C432.v file, file is written in wire logical expression data.
(3) the above logical expression is split, i.e., marks the array after segmentation, braces with a pair of of braces " { } "
Interior every group only has a logical symbol, such as {~G1 }, { G1&G2 }.
(4) logic gate symbol NOT, AND, XOR, OR, XNOR etc. are indicated, forms dictionary array set.
(5) required out gate formula is taken.
(6) judge the wire type that whether there is on the right of equation, be to be transferred to step (7), otherwise terminate.
(7) wire type is replaced with wordbook element.
(8) judge on the right of equation whether the data in all input array set, be to terminate, be otherwise transferred to step
(6)。
Step 2: increased key door number is arranged according to the size of producer's ifq circuit and confidentiality intensity.It surveys herein
In examination, input digit is 41, and output digit is 32, and key digit is 9, is inserted into ratio according to the door of the default encryption of table 1
Example is arranged 3, radom insertion key door, is inserted into key 3 in pairs to 6 according to given normal form.
Step 3: the time with identification is calculated for reduction here according to the ratio radom insertion XOR gate of radom insertion door
Complexity is preferentially inserted into 3 key doors in input port, i.e. in modification original c499.v any 3 in 41 input gates, selects here
G1、G2、G15。
G1 in input array is replaced with G1009 in c499_top.v and c499.v and increases secret key bits K [0] by citing,
Increase sentence in c499.v:
xor XOR2_300(G1,G1009,K0)；
Step 4: each being patrolled in matching record according to the input and output result record set after the obtained backtracking of step 1
Collect gate expression formula and input normal form I1I2I3, wherein situation I can be increasedi=Ii1+Ii2, Ii=Ii1Ii2(i=1,2,3).Take it
In 3 groups, citing wherein one group of replacement in detail here.
Modification is nullified:
and AND4_0(G378,G338,G339,G340,G273)；
It replaces with
and AND2_199(G378,G1001,G273)；
and AND2_200(G1001,G339,G1003)；
and AND2_201(G1003,G1004,G1005)；
xor xor2_202(G1005,K2,G1008)；
or or2_100(G1008,G338,G1007)；
xor XOR2_204(G1007,G260,K1)；
not NOT_205(G1004,G1006)；
and AND2_206(G1006,G339,G1007)；
Circuit diagram such as Fig. 5, the expression formula due to modifying cancellation in c499.v, which is recalled, not NOT_2 (G340, G260), because
This introduces G260；Here it is considered that G260 isG340 is I1, G338 I2, G339 I3.G260, G338, G339 are input,
G1007, G1005 are XOR gate.
Test effect:
When being inserted into 12 keys behind the door according to above-mentioned algorithm, input KEY=9 ' 0,000 00000 (correct key) generates emulation
Figure and the comparison of 1,111 11111 analogous diagram of KEY=9 ', are shown in Table 2 and Fig. 7-10.It can be seen that two working as time point use in table 2
When key input error, output does not differ 1 (550ns) 2 (701ns), causes chip can not normal use.
In Fig. 7, c499.v is inserted into the Vivado software analog simulation datagram of key behind the door, and interception time section is 550ns-
560ns.41 of first behavior input, 32 of output when the correct key of the second behavior, last line is 9 of key.
In Fig. 8, under specific embodiment, it is inserted into key door, and key input is the output analog simulation data of mistake
Figure, interception time section are 550ns-560ns.
In Fig. 9, c499.v is inserted into the Vivado software analog simulation datagram of key behind the door, and interception time section is 694ns-
700ns.41 of first behavior input, 32 of output when the correct key of the second behavior, last line is the 9 of correct key
Position is " 000000000 ".
In Figure 10, under specific embodiment, be inserted into key door, and key input for be it is wrong (for
" 111111111 "), which is 694ns-700ns.
Table 2
| Time point ns | Key correctly exports (latter 8) | Wrong cipher key exports (latter 8) |
| 550 | 0111 1010 | 0111 1011 |
| 701 | 1001 1001 | 1010 1010 |
Claims (4)
1. a kind of logic ciphering type hardware security guard method based on key door insertion algorithm, which is characterized in that including as follows
Step:
(1) every output port expression formula Jing Guo one logic gate is calculated according to the circuit diagram of original unencryption, by forward trace 3
The result of layer logic gate records result as input；
(2) according to the size of producer's ifq circuit and confidentiality intensity, increased key door number is set.
(3) according to the ratio radom insertion XOR gate of radom insertion door .v file is modified；
(4) each logic gate expression formula and input normal form I in matching step (1) obtained record1I2I3, wherein increase by second,
The third situation Ii=Ii1+Ii2、Ii=Ii1Ii2(i=1,2,3) judges whether to reach thresholding and still has matched insertion mould
Formula is to enter step (5), otherwise, is executed step (6)；
(5) it is inserted into strong logic key door in pairs, i.e., according to matching result, is inserted into a pair of secret keys door, modifies .v file；
(6) terminate insertion, modify circuit top.v file.
2. the logic ciphering type hardware security guard method based on key door insertion algorithm as described in claim 1, feature
It is, in step (1), the character string needed by canonical matching, i.e. specified logical expression repeatedly replace required logic gate
Change upper level into, the number of plies required until reaching backtracking, is that each output is converted into the defeated of most original when backtracking requires the number of plies
When the case where entering, specifically comprise the following steps:
(11) canonical library is established；
(12) input, output are extracted from C432.v file, file is written in wire logical expression data；
(13) the above logical expression is split, i.e., the array after being divided with a pair of of braces " { } " label, in braces
Every group only has a logical symbol, such as {~G1 }, { G1&G2 }；
(14) logic gate symbol NOT, AND, XOR, OR, XNOR etc. are indicated, forms dictionary array set；
(15) required out gate formula is taken；
(16) judge the wire type that whether there is on the right of equation, be to be transferred to step (17), otherwise terminate；
(17) wire type is replaced with wordbook element；
(18) judge on the right of equation whether the data in all input array set, be to terminate, be otherwise transferred to step
(16)。
3. the logic ciphering type hardware security guard method based on key door insertion algorithm as described in claim 1, feature
It is, in step (2), according to the size of producer's ifq circuit and confidentiality intensity, increased key door number is set, table 1 is
Default the number ratio arrangement of newly-increased XOR gate, operation result takes 3 multiple；The ratio of radom insertion usually takes key door number
33%, i.e., a pair of strong correlation logic encrypts door, a random key door, and specific distribution is shown in Table 1:
Table 1
4. the logic ciphering type hardware security guard method based on key door insertion algorithm as described in claim 1, feature
It is, in step (5), inserts door mode specifically: operation is automatically inserted into script, and there are two this function parameters, and one is the inspection of upper step
The code position that the satisfaction replacement that the script that survey can be inserted into strong logical key door position is run out requires for needs as a result, secondly repair
The former integrated circuit .v file changed, to .v file operation, i.e., what is obtained before meets what replacement required for script automation
Code position is as a result, deleting original code in the position and being inserted into the modified strong correlation logic encryption spy mentioned with this patent
The hardware identification code of property.
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| CN113378504A (en) * | 2021-08-11 | 2021-09-10 | 北京航空航天大学杭州创新研究院 | Logic encryption-based integrated circuit low-controllability node protection method |
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| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113032791B (en) * | 2021-04-01 | 2024-05-31 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113378504A (en) * | 2021-08-11 | 2021-09-10 | 北京航空航天大学杭州创新研究院 | Logic encryption-based integrated circuit low-controllability node protection method |
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