CN109376116B - The construction method and chip node of the topological structure of chip network - Google Patents
The construction method and chip node of the topological structure of chip network Download PDFInfo
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- CN109376116B CN109376116B CN201910038045.0A CN201910038045A CN109376116B CN 109376116 B CN109376116 B CN 109376116B CN 201910038045 A CN201910038045 A CN 201910038045A CN 109376116 B CN109376116 B CN 109376116B
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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Abstract
This application provides a kind of construction method of the topological structure of chip network and chip nodes, which comprises the first chip node establishes the connection with the second chip node；First chip node is any one chip node in chip network；The master port physical connection for not setting up connection of second chip node and the first chip node；First chip node establishes direct connection relational table using itself connection between the second chip node；For first chip node by not used master port, the second chip node connected to not used master port sends the first signaling；First signaling is used to control the second chip node and executes the movement that the first chip node establishes the first signaling of direct connection relational table and transmission of itself；First chip node receives the second signaling of the second chip node feeding back；Wherein, the second signaling identifies the non-not used master port of itself all master port by the second chip node, to the first chip node feeding back.
Description
Technical field
The present invention relates to chip network technical field, in particular to the construction method of a kind of topological structure of chip network and
Chip node.
Background technique
With the development of computer technology, the performance of one single chip has been difficult to meet the needs of to processing speed.Therefore,
It usually needs for multiple chips to be connected with each other, constitutes a chip network, to achieve the effect that improve processing speed.
In chip network, the communication between chip needs network-based topological structure to realize, existing to establish network
The method of topological structure is to be pre-designed network topology structure, and be preset in chip node, then according to the network
Topological structure connects chip node.
Problem of the prior art is that the chip network based on above method building can only operate in the network being pre-designed
Under topological structure, to dispose the network of different structure, it is necessary to corresponding chip is customized for each network structure, it can not
Flexibly use same chip structural support multiple network.
Summary of the invention
Based on above-mentioned the deficiencies in the prior art, the application proposes the construction method and core of a kind of topological structure of chip network
Piece node, to realize that building obtains the topological structure of chip network.
To solve the above problems, the scheme now proposed is as follows:
The application first aspect provides a kind of construction method of the topological structure of chip network, comprising:
First chip node establishes the connection with the second chip node；Wherein, the first chip node is the chip
Any one chip node in network；The master port physics for not setting up connection of the second chip node and the first chip node
Connection；
First chip node establishes direct connection relational table using itself connection between the second chip node；
Wherein, the direct connection relational table is used to record the connection relationship of the first chip node and the second chip node；
The first chip node is by not used master port, to the second chip of the not used master port connection
Node sends the first signaling；Wherein, the not used master port of the first chip node is for referring to the not sent mistake of master port
Signaling；First signaling be used for control the second chip node execute the first chip node establish itself directly connect
It connects relation table and sends the movement of first signaling；
The first chip node receives the second signaling of the second chip node feeding back；Wherein, second signaling
Identify that the non-not used master port of itself all master port, Xiang Suoshu the first chip node are anti-by the second chip node
Feedback.
Optionally, the first chip node establishes the connection with the second chip node, comprising:
The first chip node receives the third signaling that third chip node is sent；Wherein, the third chip node
With the first chip node physical connection, and be not equal to the second chip node；
The first chip node establishes the connection with the second chip node.
Optionally, the first chip node establishes the connection with the second chip node, comprising:
The first chip node, which identifies, itself, for start node, establishes the connection with the second chip node.
Optionally, first signaling be it is multiple and correspond respectively to one in the first chip node be not used
Master port；Wherein, the first chip node sends the first signaling to the second chip node, comprising:
The first chip node utilizes each not used master port, connects respectively to the not used master port
The second chip node send corresponding first signaling.
Optionally, further includes:
The first chip node receives the direct connection relational table that the second chip node is sent；Wherein, described
The direct connection relational table that two chip nodes are sent, the connection for recording the second chip node and third chip node are closed
System；The third chip node and the second chip node physical connection, and it is not equal to the first chip node.
The application second aspect provides a kind of chip node, and the chip node is the first chip node, and described first
Chip node, comprising:
First establishing unit, for establishing and the connection of the second chip node；Wherein, the first chip node is described
Any one chip node in chip network；The master port for not setting up connection of the second chip node and the first chip node
Physical connection；
Second establishes unit, and for utilizing itself connection between the second chip node, foundation is directly connected to close
It is table；Wherein, the direct connection relational table is used to record the connection of the first chip node and the second chip node
Relationship；
Transmission unit, the second chip section for being connected to the not used master port by not used master port
Point sends the first signaling；Wherein, the not used master port of the first chip node is believed for referring to not sent cross of master port
It enables；First signaling executes the first chip node for controlling the second chip node and establishes being directly connected to for itself
Relation table and the movement for sending first signaling；
Receiving unit, for receiving the second signaling of the second chip node feeding back；Wherein, second signaling is by institute
The second chip node is stated in the non-unused port of the master port for identifying itself, Xiang Suoshu the first chip node feeding back.
Optionally, the first establishing unit, comprising:
Receiving subelement, for receiving the third signaling of third chip node transmission；Wherein, the third chip node with
The first chip node physical connection, and it is not equal to the second chip node；
First establishes subelement, for establishing and the connection of the second chip node.
Optionally, the first establishing unit, comprising:
Recognition unit, whether the first chip node is start node for identification；
Second establishes subelement, identifies that the first chip node is start node, foundation and institute for the recognition unit
State the connection of the second chip node.
Optionally, first signaling be it is multiple and correspond respectively to one in the first chip node be not used
Master port；Wherein, the transmission unit, comprising:
Transmission sub-unit is connected to the not used master port respectively for utilizing each not used master port
The second chip node send corresponding first signaling.
Optionally, the receiving unit is also used to: receiving the direct connection relational table that the second chip node is sent；Its
In, the direct connection relational table that the second chip node is sent, for recording the second chip node and third chip section
The connection relationship of point；The third chip node and the second chip node physical connection, and it is not equal to first chip
Node.
This application provides a kind of construction method of the topological structure of chip network and chip nodes.The chip network
In the construction method of topological structure, the first chip node and the second chip node for not setting up connection establish connection, and based on company
It connects to obtain direct connection relational table, in this way, the first chip node can obtain itself according to direct connection relational table and physics connects
The topological relation between chip node connect.Also, the first chip node is by the not sent master port for crossing signaling to the port
Second chip node of connection sends the first signaling, controls after the second chip node receives the first signaling and executes above-mentioned foundation company
The step of connecing and sending the first signaling, therefore, the second chip node can also obtain certainly according to the direct connection relational table of itself
Topological relation between body and the chip node of physical connection, and successively controlled in chip network and retransmiting the first signaling
Other chip nodes establish itself direct connection relational table, until each of chip network chip node obtain from
The direct connection relational table of body.In this way, passing through the direct connection relational table that obtains each of chip network chip node
Mode, the network topology of available chip network, not needing the preparatory network topology structure of write-in in the chips can be completed core
The building of piece network topology structure, therefore the construction method of the topological structure of chip network provided by the present application and chip node are permitted
Perhaps the structure of chip network changes, and can support various chips network structure.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 a is a kind of schematic diagram of chip network disclosed in the embodiment of the present application；
Fig. 1 b is the schematic diagram of another kind chip network disclosed in the embodiment of the present application；
Fig. 1 c is the schematic diagram of another kind chip network disclosed in the embodiment of the present application；
Fig. 2 is a kind of construction method of the topological structure of chip network disclosed in the embodiment of the present application；
Fig. 3 is a kind of structural schematic diagram of chip node disclosed in the embodiment of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The construction method of the topological structure for the chip network that the application any embodiment provides in order to better understand, first
It needs to carry out brief description to chip network and its topological structure.
The chip network please refers to Fig. 1 a, Fig. 1 b and Fig. 1 c, refers to that multiple chip nodes pass through between the port of chip
Direct physical connection constitute network, wherein each chip node has a unique chip mark in the chip network
Know symbol (chip id in other words).Any one chip node in the chip network, all has directly at least one chip node
Connect physical connection.For any one chip node, there is the chip node of direct physical connection with this chip node, referred to as this
Neighbours' chip node of a chip node.
For example, chip node 102 is chip node 101 and core in a kind of simple chip network as shown in Figure 1a
Neighbours' chip node of piece node 103, chip node 103 and chip node 101 are the neighbor node 102 of chip node 102, core
Piece node 104 is neighbours' chip node of chip node 101.
It should be noted that the chip node, refers to the chip for constituting chip network, the chip network, Ke Yiyou
The multiple chips being integrated on one piece of circuit board are constituted, and can also pass through data by the chip in multiple equipment by chip controls
Transmission line connects and composes.
It should also be noted that, each designed chip has the port of fixed quantity, two chips (are denoted as chip A
And chip B) between have direct physical connection, refer to have between some port of chip A and some port of chip B direct
Electrical connection.For example, the pin of the port for two chips being integrated on one piece of circuit board is directly connected to, alternatively, two equipment
In chip port pass through data transmission link connect.That is, the connection between two chip nodes, it is possible to understand that at
Be connected with each other between two chips by corresponding port, chip A to chip B send information, specifically, chip A by with core
The port of piece B connection sends information to chip B.
The topological structure of the chip network, referring still to Fig. 1 a, it is believed that be a kind of chip id and chip described
The mapping relations between position in chip network, the communication between chip node, the chip network that needs to rely on are opened up
Flutter structure progress.The ID of chip node 101, chip node 102 and chip node 103 is successively 1,2 and 3, if chip node 101
It to be communicated with chip node 103, need to know that chip node that ID is 3 is the neighbours' chip node for the chip node that ID is 2, and
The chip node that ID is 2 is the neighbours' chip node of itself, then could be communicated according to this information.That is, appointing
Chip node anticipate after the topological structure for obtaining entire chip network, it could be quasi- according to the ID of chip any in the chip network
Really communicated with the chip.
The embodiment of the present application provides a kind of construction method of the topological structure of chip network, below with reference to shown in Fig. 1 a
Chip network is illustrated, referring to FIG. 2, the described method includes:
The port of itself is arranged according to the node type of itself for S201, initial phase, the chip node in chip network.
Specifically, step S201 includes, if it itself is initial chip node that chip node, which identifies, by all of itself
Port is set as master port；Itself, for non-initial chip node, all of the port of itself is arranged if chip node identifies
For from port.
Such as: in the chip network shown in Fig. 1 a, chip node 101 is set in advance as initial chip node, chip section
Point 102, chip node 103 and chip node 104 are set as non-initial chip node.Therefore, in initial phase, chip node
The all of the port of itself is set master port by 101, other chip nodes set all of the port of itself to from port.
It should be noted that the initial chip node, is pre-set before executing method provided by the present application.With
For integrated multiple chips on circuit boards, the initial chip node can be before integrated chip to circuit board, by skill
Art personnel preset, and before the topological structure for constructing chip network, can also pass through after all integrated chips to circuit board
Some chip node thereto sends external signal to be set to initial chip node.
It should also be noted that, initial chip node can be any one chip node in chip network, that is,
It says, the status of all chip nodes in chip network is equivalent, when initial chip node is arranged, in chip network times
Chip node of anticipating may be configured as initial chip node.In addition, initial chip node and non-initial chip node
Structure or the program that chip is written also are not different.Initial chip node and non-initial chip node, it should be understood that at only core
The value of some mark of piece node is different, when chip node executes pre-set programs, according to the different values of the mark, tool
Body executes the different branches in pre-set programs, rather than, distinct program is written with to the chip node of different identification.
S202, chip node 101 send connection request to its neighbours' chip node.
Chip node 101 needs to establish connection with its neighbours' chip node after identifying itself for start node.Specifically
, chip node 101 sends connection request to its neighbours' chip node, and connection request includes the chip node for sending connection request
ID, the i.e. ID of itself.
In the chip network shown in Fig. 1 a, the neighbor node of chip node 101 includes chip node 102 and chip node
104.Therefore, in this step, chip node 101 is to send connection request to chip node 102 and chip node 104 respectively.With
Under only with chip network shown in Fig. 1 a, chip node 101, chip node 102 and chip node 103 are example, to the application
The construction method of the topological structure of multi-chip network disclosed in embodiment is illustrated.
It should also be noted that, any one chip node is sent to itself neighbours' chip node to be connected in chip network
Request is connect, can be and once send connection request to all neighbours' chip nodes of itself, is also possible to send to connect every time to ask
When asking, a part is selected all from the neighbours' chip node of itself, is sent to it connection request, next time is again to the neighbour of another part
It occupies chip node and sends connection request, until itself establishes connection with all neighbours' chip nodes.Also, any one core
Piece node all can only send connection request to neighbor node by master port.
Also it is important to note that a chip node needs before sending connection request to neighbours' chip node
Determine that neighbours' chip node did not establish connection with itself.
S203, chip node 102 send connection response information to chip node 101.
The connection response information is to receive the chip node of connection request to the response message of connection request, be can wrap
It includes, sends the ID of the chip node of the connection response information.
It should be noted that any one chip node in the chip network is receiving the transmission of neighbours' chip node
After connection request, all connection response information can be sent to neighbours' chip node.
It is believed that just being established and chip section after chip node 101 receives the connection response information of chip node 102
The connection of point 102, obtains the connection relationship of itself and chip node 102.
The connection relationship of S204, chip node 102 record and chip node 101.
The connection relationship of chip node 102 record and chip node 101, refers to and remembers in the direct connection relational table of itself
The connection relationship of record and chip node 101.
It should be noted that recording the connection relationship with neighbours' chip node, packet in the direct connection relational table of itself
Include: the ID of neighbours' chip node receives the port of connection request and the corresponding relationship of the port and the ID.
It is believed that chip node 102 just establishes itself and chip after the connection request for receiving chip node 101
The connection of node 101 obtains the connection relationship of itself and chip node 101.
Specifically, chip node 102 is by the ID of chip node 101, with 101 physical connection of chip node in step S204
Port and the corresponding relationship of ID of the port and chip node 101 be recorded in the direct connection relational table of itself.
Optionally, step S204 can also be executed before step S203, that is to say, that chip node 102 can also sent out
It send and records the connection relationship before connection response information.
The connection relationship of S205, chip node 101 record and chip node 102.
Similarly, the connection relationship of chip node 101 record and chip node 102, refers to the direct connection relational at itself
The connection relationship with chip node 102 is recorded in table.
Specifically, chip node 101 is by the ID of chip node 102, the port with 102 physical connection of chip node, and
The corresponding relationship of the ID of the port and chip node 102 is recorded in the direct connection relational table of itself.
It is believed that after chip node 101 sends connection request and obtain connection response information to chip node 102, just
The connection for establishing chip node 101 Yu chip node 102 obtains the connection relationship of itself and chip node 102.It is described to connect
Relation record is connect in the movement of direct connection relational table, it is also assumed that being to establish direct connection relational using the connection relationship
Table.
Chip node 101 as described in above-mentioned steps S202 and step S203 sends connection request to chip node 102, and
Receive the process for the connection response information that chip node 102 is sent, it is believed that be 101 active of chip node and chip node
102 establish the process of connection.Corresponding, chip node 102 receives the connection request of chip node 101, and feedback link responds
The process of information, it is also assumed that being the process that chip node 102 passively establishes connection with chip node 101.
It should also be noted that, shown in fig 1 a in chip network, chip node 101 in addition to chip node 102
Connection is established, can also establish connection with chip node 104, therefore, there is certainly record in the direct connection relational table of chip node 101
The connection relationship of body and chip node 102 and chip node 104.
It can be seen that: in chip network, each chip node needs to utilize itself and its neighbours' chip node
Between connection relationship, establish direct connection relational table；Wherein, the direct connection relational table is for recording itself and its neighbour
The connection relationship of chip node.
Also, the direct connection relational table that each chip node is established, record have itself between neighbours' chip node
Connection relationship, in this way, in chip network about the topological structure of this chip node can according to direct connection relational table determine
Out.
Also it should be strongly noted that in step S204, the connection relationship of chip node 102 record and chip node 101,
The property of can choose executes.In step S205, chip node 101 records and chip node in the direct connection relational table of itself
102 connection relationship can specify chip node 101 and chip section by the direct connection relational table of chip node 101 substantially
Network topology between point 102.Therefore, chip node 102, which can choose, does not execute step S204.
Therefore deduce that: in chip network, each chip node responds the foundation of its neighbours' chip node initiation
The request of connection, and before or after sending connection response information, the execution following steps for the property of can choose:
Using itself connection relationship between neighbours' chip node, direct connection relational table is established；This is directly connected to close
It is that table is used to record itself connection relationship between neighbours' chip node, also, the neighbours' chip node proposed herein is hair
Send the chip node for the request for establishing connection.
S206, chip node 101 send signaling to chip node 102.
Wherein, the signaling that chip node 101 is sent, can be referred to as the first signaling.
In the chip network described in Fig. 1 a, chip node 101 is sent to chip node 102 and chip node 104 respectively
Connection request, thus all establish and connect with chip node 102 and chip node 104, then in step S206, chip node
101 be that port by connecting with chip node 102 is needed to send signaling to chip node 102, and by connecting with chip 104
Port to chip node 104 send signaling.
Also, the signaling can only be generated before transmitting by initial chip node, the non-initial chip in chip network
Node can only transmit itself received signaling, and cannot generate signaling.Specifically in the chip network shown in Fig. 1 a, chip node
101 be initial chip node, and after generating and sending signaling, chip node 102, chip node 103 and chip node 104 can only
Signaling is received, and is transmitted to its neighbours' chip node, and signaling cannot be generated.
Optionally, signaling may include historical path table and signaling identifier.
The node and port that the signaling is passed through are described in historical path table in chronological order.Therefore, in chip net
Initial chip node in network, generate signaling after, need to record in the historical path table of the signaling initial chip node ID,
And used port when itself sending signaling to neighbours' chip node.And any one non-initial core in chip network
Piece node, after receiving the signaling, it is also necessary to the port recorded self ID in the historical path table of the signaling, receive signaling,
And again to port used when the transmission of neighbours' chip node.
Signaling identifier can be a character string, a variety of signalings generated for distinguishing initial chip node, if two
Signaling is not same signaling, then the signaling identifier of the two signalings is just different, conversely, if two signalings are same letters
It enables, then the signaling identifier of the two signalings is identical.For example, being denoted as signaling 1 if initial chip node generates two kinds of signalings
With signaling 2, then the signaling identifier of signaling 1 is just different from the signaling identifier of signaling 2, any chip node receives above-mentioned two
After one of kind signaling, so that it may which the signaling received according to the signaling identifier judgement in signaling is specifically that signaling 1 is gone back
It is signaling 2.
It should also be noted that, chip node 101 needs to send signaling to chip node 102 and chip node 104 respectively.
Therefore, two different signalings can be generated in chip node 101, respectively correspond the two neighbours' chip nodes of itself.Specifically,
Chip node 101 generates signaling 1, is sent by the master port 1 of itself connection chip node 102 to chip node 102；Generate letter
2 are enabled, is sent by the master port 2 of itself connection chip node 104 to chip node 104.Chip node 101 also can be generated one
Kind signaling, respectively by the master port of connection chip node 102 and chip node 104, to chip node 102 and chip node
104 send.
If chip node 101 has only generated a kind of signaling, but all sends to chip node 102 and chip node 104 respectively
This signaling, then in the signaling that signaling and chip node 104 that chip node 102 receives receive, historical path table
Content is also different.
Specifically, being replicated to obtain two signalings 1 to it, then by this after chip node 101 generates above-mentioned signaling 1
Two signalings 1 are respectively sent to chip node 102 and chip node 104, and chip node 102 and chip node 104 receive at this time
Be all signaling 1, but sent since the two signalings 1 are chip nodes 101 by different ports, two signalings 1
The content recorded in historical path table is different.
That is, in this case, the signaling that the signaling and chip node 104 that chip node 102 receives receive belongs to
The signaling identifier of same signaling, i.e., two signalings is identical, but historical path table is different, therefore is two different signalings.
The signaling 1 that chip node 102 receives can be denoted as signaling 1-2, the signaling 1 that chip node 104 receives is denoted as 1-4.Other
After chip node receives any of the above-described a signaling, it can identify that the signaling received is signaling 1 by signaling identifier, further
Can identify that the signaling received is signaling 1-2 or signaling 1-4 according to historical path table therein.
It should be strongly noted that chip node 101 sends signaling every time, require to ensure that chip node 101 is to pass through
Not used master port is sent to neighbours' chip node.Wherein, not used master port refers to: chip node 101 does not utilize should
Master port is transmitted across signaling, i.e., the not sent master port for crossing signaling.
Therefore, it can be seen that: in chip network, initial chip node, neighbours' chip node generally have it is multiple, and
And initial chip node can establish the connection with its all neighbours' chip node.For the multiple of initial chip node connection
Neighbours' chip node, initial chip node send signaling, can only send a signaling, can also send multiple signalings.Work as hair
When sending multiple signalings, any two signaling therein can may not be same signaling with same signaling.In addition, wherein
Any two signaling, even same signaling, since two signalings are sent by different ports, the two signalings
Historical path table in content be also different.
In the quantity for the signaling that initial chip node generates, it is used to connect the quantity of the master port of neighbor node less than itself
When, it is limited by signaling quantity, initial chip node is not able to achieve the signaling disposably sent, all occupies all main sides
Mouthful, as soon as in this way, initial chip node, which has, have been used master port and has been not used after initial chip node is transmitted across time signaling
Master port.Therefore, signaling is retransmited in initial chip node, it is necessary to send signaling using master port is not used.
So it was determined that initial chip node sends signaling to neighbours' chip node, refer to by not used
Master port sends signaling to neighbours' chip node.
Optionally, if signaling is multiple and corresponds respectively to a not used master port in initial chip node；Just
Beginning chip node utilizes each not used master port, sends respectively to the chip node that the not used master port connects
Corresponding signaling.
After S207, chip node 102 receive signaling, not connected neighbours' chip node is judged whether there is, if there is not connected neighbour
Chip node is occupied, S208 is thened follow the steps, it is no to then follow the steps S213.
Optionally, described to judge whether itself has not connected neighbor node, it can be by judging being directly connected to for itself
The quantity whether quantity of the ID whether stored in relation table is equal to the neighbours' chip node of itself is realized.It establishes between the chips
After physical connection, the quantity for each chip in network, the neighbours' chip node of itself is known, it is believed that right
In a chip, after physical connection is established in the port of this chip and the port of another chip, this chip can be by this
Port label is to have the port of neighbor node, and therefore, any one chip node all records the neighbours' chip for having itself in network
Number of nodes, and be specifically which port is connect with neighbours' chip node.
In conclusion can identify the direct connection relational table of itself after any one chip node receives the signaling
The quantity of the ID of middle storage, if the quantity of the ID of storage judges that itself has less than the quantity of the neighbours' chip node of itself
Not connected neighbours' chip node, if the quantity of the ID of storage is equal to the quantity of the neighbours' chip node of itself, judgement is come from
Neighbours' chip node that body is not not connected with.
In the above-described example, after chip node 102 receives the first signaling that chip node 101 is sent, the straight of itself is read
The quantity of the ID recorded in connection relational table is connect, chip node 102 is only established with chip node 101 and is connect at this time, therefore from
An ID, that is, the ID of chip node 101 are only recorded in the direct connection relational table of body, and chip node 102 has chip section
101 and chip node 103 are put, totally two neighbours' chip nodes.The quantity of the ID of record is less than neighbours' chip of chip node 102
The quantity of node, therefore, chip node 102 judge the neighbours' chip node for itself having not connected, execute step S208.
The not connected port of itself is set master port by S208, chip node 102.
There is physical connection in itself the not connected port with the port of neighbours' chip node for referring to, but not with institute
It states neighbours' chip node and establishes connection, that is, the port being not recorded in the direct connection relational table of itself.
Optionally, step S208 can be realized in the following ways, and chip node 102 compares the direct connection relational of itself
The port that is recorded in table and itself have the port of neighbours' chip node, so that find out itself has neighbours' chip node, but
It is not recorded in the port in the direct connection relational table, that is, the port not connecting with neighbours' chip node, then by institute
It states port and is set as master port.
Optionally, described to set master port for the port not connecting with neighbours' chip node, it can be, chip node exists
When receiving signaling for the first time, master port just is set by all not connected ports of itself, is also possible to chip node for the first time
When receiving signaling, selected from the multiple not connected ports of itself it is several be set as master port, when hereafter receiving signaling every time, if
Itself still has not connected port, continue to choose in never connectivity port it is several be set as master port, until itself does not connect
Until connecing port.
If chip node 102 connects with the more chips node physics other than chip node 102 and chip node 103
Connect, then when chip node 102 executes step S208, can by with chip node 103 and other chip node physical connections
Port is both configured to master port.
S209, chip node 102 send connection request to the not connected neighbours' chip node of itself.
Wherein, the connection request is sent by chip node 102 by the master port of itself.
In the above-described example, when executing step S208, not connected neighbours' chip node of chip node 102 is chip section
Point 103, step S208 is it is also assumed that be to send signaling to chip node 103.
It is similar with step S202, it, can also be to described more if chip node 102 has multiple not connected neighbours' chip nodes
A not connected neighbours' chip node sends connection request.
It should also be noted that, chip node 102 is not initial chip node, therefore, its neighbours' chip is received at it
After the signaling that node 101 is sent, just executes and establish connection with other the not connected neighbours' chip nodes 103 of itself.
It can be seen that: in chip network, non-initial chip node (can be referred to as the first chip node) is received
After the signaling (third signaling can be referred to as) sent to one neighbours' chip node (third chip node can be referred to as),
(the second chip node can be referred to as) after determining the neighbours' chip node for itself thering are other not set up connection, can just establish with
Neighbours' chip node (i.e. the second chip node) establishes connection.
S210, chip node 103 send connection response information to chip node 102.
S211, chip node 103 record the connection relationship of itself and chip node 102.
In this step, the specific executive mode of chip node 103 can refer to the content of step S204, no longer superfluous herein
It states.Also, the step can also be by the execution of 103 selectivity of chip node.
S212, chip node 102 record the connection relationship of itself and chip node 103.
In this step, the specific executive mode of chip node 102 can refer to the content of step S205, herein also no longer
It repeats.
Also, by step S205 and step S212 it can be seen that each of chip network chip node, utilizes itself
With the connection relationship of neighbours' chip node, direct connection relational table is established, the company of itself and neighbours' chip node is recorded by the table
Connect relationship.In this way, after the splicing and combining of the direct connection relational table of each chip node, it can form the net of chip network
Network topological structure.
S213, chip node 102 judge whether itself has not used master port, if itself has not used master port,
S214 is thened follow the steps, if itself not having not used master port, thens follow the steps S216.
Wherein, not used master port refers to: chip node is not transmitted across signaling using the master port, i.e., not sent cross is believed
The master port of order.Similarly, the port that chip node is transmitted across signaling is referred to as to have used port.
It should be noted that any one non-initial chip node, neighbours' chip node is generally in chip network
Have multiple, also, chip node can establish the connection with its all neighbours' chip node.But in its received signaling
Quantity less than chip node be used for connect neighbor node master port quantity when, limited by signaling quantity, chip node
It is not able to achieve the signaling disposably sent, all occupies all master ports, in this way, being transmitted across a signaling in chip node
Afterwards, chip node, which just has, has used master port and unused master port.Therefore, it before chip node sends signaling, just needs
First to judge whether itself has not used master port.
In the above-described example, chip node 102 identifies that the master port connecting with chip node 103 is that main side is not used
Mouthful, execute step S214.
It, can be by judging the use of master port it should also be noted that, judge whether itself has not used master port
Mark realizes, as soon as each chip node after sending signaling by the master port of itself, by the use mark of this master port
Knowledge is set as having used, when the use mark of all master ports of a chip node is all in use, showing the master of itself
The non-not used master port in port.
S214, chip node 102 send the letter to corresponding neighbours' chip node by the not used master port
It enables.
Wherein, the signaling that chip node 102 is sent to neighbours' chip node, can also be referred to as the first signaling.
In step S213 and step S214, judge itself whether there is not used master port, and unused judging to have
Master port after, by the not used master port to neighbours' chip node send signaling process, be in order to ensure chip
The non-initial chip node of each of network receives at least one signaling, all at least receives a signaling in other words.
Also, in the present embodiment, by step S206 and step S213 ~ S214, it will thus be seen that
In chip network, either initial chip node or non-initial chip node, to its neighbours' chip node
It is all that the neighbours' chip node connected by not used master port to it is sent when sending signaling.
In addition, after non-initial chip node receives signaling (i.e. third signaling), then by not used master port to its
The signaling (i.e. the first signaling) that neighbours' chip node of connection is sent, can be identical signaling, here just for the sake of differentiation
The signaling non-initial chip node received signaling and externally sent, is just respectively defined as third signaling and the first signaling.
After S215, chip node 103 receive signaling, to the chip node feeding back signaling for sending signaling to itself earliest.
It in the above-described example, to the chip node that chip node 103 sends the signaling is earliest chip node 102, because
This, chip node 103 feeds back the signaling to chip node 102.
The signaling that chip node 103 is fed back to chip node 102, can be referred to as the second signaling.Also, chip node
Second signaling of 103 received first signalings and feedback, it is possible to understand that at being the same signaling, it is only for difference chip section
The signaling and be denoted as the first signaling and the second signaling respectively to the signaling that neighbor node is fed back that point is sent.Optionally, chip section
The signaling that point 103 is fed back to chip node 102, i.e. the second signaling can also carry the direct connection relational of chip node 103
Table.
Certainly, the direct connection relational table of chip node 103 can also individually be sent to chip node 102, not carried
In the second signaling of its feedback.
Wherein, what is recorded in the direct connection relational table of chip node 103 is neighbours' chip node of itself and itself
Connection relationship, therefore, then to chip node 102 feed back after, be equal to the neighbours that itself and itself are informed to chip node 102
The connection relationship of chip node, in this way, chip node 102, except the connection for specifying itself and itself neighbours' chip node is closed
Except system, the neighbours' chip node of itself, the connection relationship with its neighbours' chip node are also further specified.
It should also be noted that, step S215 be after chip node 103 receives signaling, execute such as above-mentioned steps S207 and
Judgement described in step S213, and the movement executed after being all judged as NO, if it is above-mentioned any one of judge be it is yes, according to judgement
As a result it executes step S208 to step S212 or executes step S214.That is: chip node 103 need to identify itself and it is all
Neighbours' chip node, which is established, connection, and after being transmitted across signaling to neighbours' chip node by each master port,
It can be to 102 feedback signaling of chip node.
It can be seen that: any one non-initial chip node in chip network, the signaling feedback that itself is received
To earliest to before the chip node for itself sending the signaling, requiring to ensure that itself and itself neighbor node foundation has company
It connects, i.e., the master port itself not being not connected with, it is also necessary to ensure the non-not used master port of itself all master port.
Also, any one non-initial chip node in chip network, to the neighbours' core for sending signaling to itself earliest
In piece node feedback signaling, the direct connection relational table of itself can also be carried.Alternatively, after determination can be with feedback signaling, directly
Connect the direct connection relational table to the neighbours' chip node feeding back itself for itself sending signaling.
S216, chip node 102 are to earliest to the chip node feeding back signaling of itself transmission signaling.
Similarly, chip node 102 is after the signaling for receiving the feedback of chip node 103, it is also desirable to itself not have clear
Not connected master port, and in the case where the non-not used master port of itself all master port, Cai Huixiang chip node 101
Feedback signaling.
In the present embodiment, the chip node that step S215 and step S216 are proposed is by signaling feedback to earliest to itself transmission
Neighbours' chip node of the signaling is to enable the signaling along being transferred to itself path from initial chip node
It is back to initial chip node, after initial chip node receives the signaling of feedback, then can determine the network of chip network
Topology constructing is completed.That is, each chip node and the neighbours' chip node of itself in chip network establish company
It connects, and the connection relationship is recorded in the direct connection relational table of itself.In this way, any one chip in chip network
Node, can be by obtaining the direct connection relational table of other chip nodes and whole in the topological structure for needing whole network
It closes direct connection relational table and obtains the topological structure of chip network.
Also, feed back to earliest to the neighbours' chip node for itself sending the signaling, be because, it is more complex at one
In network, one receives the chip node (being denoted as local chip node) of signaling, may send and believe to multiple neighbours' chip nodes
It enables, and receives the signaling of multiple neighbours' chip node feeding backs, therefore meet the condition of above-mentioned feedback signaling in local chip node
When, there may be multiple neighbours' chip nodes that signaling is sent to local chip node, in order to make side provided by the embodiments of the present application
Method smoothly executes, and the object of feedback should be neighbours' chip node that the signaling is initially sent to local chip node.
Optionally, described to give signaling feedback initially to the neighbours' chip node for itself sending the signaling, it can pass through
The historical path table for inquiring the signaling is found earliest to the neighbours' chip node for itself sending the signaling, then passes through correspondence
Port feedback.
Need to propose is a bit: in network chip, intermediate chip node in chip network is not belonging to leaf section
Point, nor intermediate chip node is to earliest to the chip node feeding back signaling of itself transmission signaling in the case where start node
In, the direct connection relational table carried in the direct connection relational table and itself received feedback signaling of itself can be carried
(i.e. the direct connection relational table of itself neighbours' chip node).Also it or, by the direct connection relational table of itself and itself receives
Feedback signaling in the direct connection relational table that carries be packaged feedback.Certainly, if itself received neighbour of intermediate chip node
The direct connection relational table that chip node is individually fed back, then can be by the direct connection relational table of itself, received neighbours' chip
The direct connection relational table of node is packaged feedback, or is packaged and is carried in the signaling of feedback.
Also need to propose is a bit: the chip node in network chip, will include at least the direct connection relational of itself
Table, to the chip node feeding back for sending signaling to itself earliest, until final feedback arrives initial chip node.Initial chip node
It can arrange according to received all direct connection relational tables and obtain the network topology structure of chip network.
The construction method of topological structure based on said chip network, another embodiment of the application provide a kind of chip section
Point, the construction method of the topological structure for executing said chip network, referring to FIG. 3, the chip node includes:
First establishing unit 301, for establishing and the connection of the second chip node；Wherein, the first chip node is
Any one chip node in the chip network；The master for not setting up connection of the second chip node and the first chip node
Ports physical connection.
Second establishes unit 302, and for utilizing itself connection between the second chip node, foundation is directly connected to
Relation table；Wherein, the direct connection relational table is used to record the company of the first chip node and the second chip node
Connect relationship.
Transmission unit 303, the second chip for being connected to the not used master port by not used master port
Node sends the first signaling；Wherein, the not used master port of the first chip node is for referring to the not sent mistake of master port
Signaling；First signaling be used for control the second chip node execute the first chip node establish itself directly connect
It connects relation table and sends the movement of first signaling.
Receiving unit 304, for receiving the second signaling of the second chip node feeding back；Wherein, second signaling
By the second chip node in the non-unused port of the master port for identifying itself, Xiang Suoshu the first chip node feeding back.
Optionally, the first establishing unit 301 includes:
Receiving subelement, for receiving the third signaling of third chip node transmission；Wherein, the third chip node with
The first chip node physical connection, and it is not equal to the second chip node；
First establishes subelement, for establishing and the connection of the second chip node.
Optionally, the first establishing unit 301 includes:
Recognition unit, whether the first chip node is start node for identification；
Second establishes subelement, identifies that the first chip node is start node, foundation and institute for the recognition unit
State the connection of the second chip node.
Optionally, first signaling be it is multiple and correspond respectively to one in the first chip node be not used
Master port；Wherein, the transmission unit, comprising:
Transmission sub-unit is connected to the not used master port respectively for utilizing each not used master port
The second chip node send corresponding first signaling.
Optionally, the receiving unit is also used to: receiving the direct connection relational table that the second chip node is sent；Its
In, the direct connection relational table that the second chip node is sent, for recording the second chip node and third chip section
The connection relationship of point；The third chip node and the second chip node physical connection, and it is not equal to first chip
Node.
In chip node provided by the embodiments of the present application, first establishing unit establishes the connection with the second chip node, and
Unit is established with second and establishes direct connection relational table according to connection relationship, is then sent with transmission unit to the second chip node
Signaling.Further, any chip node all can serve as the first chip node with itself after receiving signaling in network
One establishes unit, second establishes unit and transmission unit and execute the above process.Finally, any one chip node in network is all
Direct connection relational table is established, and records the connection pass of itself and neighbours' chip node in the direct connection relational table
System, so as to construct the topological structure of chip network.Chip node provided by the embodiments of the present application, can construct hauling automatically
The topological structure of network, therefore chip node provided by the embodiments of the present application is used only, so that it may support multiple network topological structure.
Professional technician can be realized or using the present invention.Profession of the various modifications to these embodiments to this field
It will be apparent for technical staff, the general principles defined herein can not depart from spirit or model of the invention
In the case where enclosing, realize in other embodiments.Therefore, the present invention will not be limited to the embodiments shown herein,
And it is to fit to the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. a kind of construction method of the topological structure of chip network characterized by comprising
First chip node establishes the connection with the second chip node；Wherein, the first chip node is the chip network
In any one chip node；The master port physics for not setting up connection of the second chip node and the first chip node connects
It connects；
First chip node establishes direct connection relational table using itself connection between the second chip node；Wherein,
The direct connection relational table is used to record the connection relationship of the first chip node and the second chip node；
The first chip node is by not used master port, to the second chip node of the not used master port connection
Send the first signaling；Wherein, for referring to, master port is not sent to cross signaling to the not used master port of the first chip node；
First signaling be used for control the second chip node execute the first chip node establish itself be directly connected to close
It is table and the movement for sending first signaling；
The first chip node receives the second signaling of the second chip node feeding back；Wherein, second signaling is by institute
It states the second chip node and identifies the non-not used master port of itself all master port, Xiang Suoshu the first chip node feeding back.
2. the method according to claim 1, wherein the first chip node is established and the second chip node
Connection, comprising:
The first chip node receives the third signaling that third chip node is sent；Wherein, the third chip node and institute
The first chip node physical connection is stated, and is not equal to the second chip node；
The first chip node establishes the connection with the second chip node.
3. the method according to claim 1, wherein the first chip node is established and the second chip node
Connection, comprising:
The first chip node, which identifies, itself, for start node, establishes the connection with the second chip node.
4. the method according to claim 1, wherein first signaling is multiple and corresponds respectively to described
A not used master port in first chip node；Wherein, the first chip node is sent out to the second chip node
Send the first signaling, comprising:
The first chip node utilizes each not used master port, the connected respectively to the not used master port
Two chip nodes send corresponding first signaling.
5. method as claimed in any of claims 1 to 4, which is characterized in that further include:
The first chip node receives the direct connection relational table that the second chip node is sent；Wherein, second core
The direct connection relational table that piece node is sent, for recording the connection relationship of the second chip node and third chip node；
The third chip node and the second chip node physical connection, and it is not equal to the first chip node.
6. a kind of chip node, which is characterized in that the chip node is the first chip node, the first chip node, packet
It includes:
First establishing unit, for establishing and the connection of the second chip node；Wherein, the first chip node is chip network
In any one chip node；The master port physics for not setting up connection of the second chip node and the first chip node connects
It connects；
Second establishes unit, for utilizing itself connection between the second chip node, establishes direct connection relational table；
Wherein, the direct connection relational table is used to record the connection relationship of the first chip node and the second chip node；
Transmission unit, for by not used master port, the second chip node connected to the not used master port to be sent out
Send the first signaling；Wherein, for referring to, master port is not sent to cross signaling to the not used master port of the first chip node；Institute
It states the first signaling and executes the direct connection relational that the first chip node establishes itself for controlling the second chip node
Table and the movement for sending first signaling；
Receiving unit, for receiving the second signaling of the second chip node feeding back；Wherein, second signaling is by described
Two chip nodes are in the non-unused port of the master port for identifying itself, Xiang Suoshu the first chip node feeding back.
7. chip node according to claim 6, which is characterized in that the first establishing unit, comprising:
Receiving subelement, for receiving the third signaling of third chip node transmission；Wherein, the third chip node with it is described
First chip node physical connection, and it is not equal to the second chip node；
First establishes subelement, for establishing and the connection of the second chip node.
8. chip node according to claim 6, which is characterized in that the first establishing unit, comprising:
Recognition unit, whether the first chip node is start node for identification；
Second establishes subelement, identifies that the first chip node is start node for the recognition unit, establishes and described the
The connection of two chip nodes.
9. chip node according to claim 6, which is characterized in that first signaling is multiple and corresponds respectively to
A not used master port in the first chip node；Wherein, the transmission unit, comprising:
Transmission sub-unit, for utilizing each not used master port, connected respectively to the not used master port the
Two chip nodes send corresponding first signaling.
10. chip node according to any one of claims 6 to 9, which is characterized in that the receiving unit is also used
In: receive the direct connection relational table of the second chip node transmission；Wherein, what the second chip node was sent directly connects
Relation table is connect, for recording the connection relationship of the second chip node and third chip node；The third chip node with
The second chip node physical connection, and it is not equal to the first chip node.
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