CN109361411B - Method and device for simplifying synchronous circuit - Google Patents
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Abstract
The application provides a method and a device for simplifying a synchronous circuit, wherein the method comprises the following steps: storing an input GFSK signal sampling point in a static random access memory; reading a signal sampling point stored in the static random access memory according to a preset rule; calculating the cross-correlation value of the current signal sampling point and the local synchronous sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment. The method reduces the chip area by adopting the static random access memory to store the GFSK signal sampling point, and avoids the power consumption caused by shifting because a shift register is not used for storing the input GFSK signal sampling point; in addition, the cross-correlation value in the synchronous circuit is calculated in an iterative mode, and circuit implementation is greatly simplified. The scheme not only simplifies the circuit structure, reduces the realization area and the cost of the circuit, but also greatly reduces the dynamic power consumption of the circuit.
Description
Technical Field
The present application relates to the field of wireless communications technologies, and in particular, to a method and an apparatus for simplifying a synchronization circuit.
Background
The synchronous circuit plays a significant role in a receiver circuit in a communication system, and is an important guarantee that a transceiving system can efficiently and stably transmit.
In the working principle of the synchronization circuit of the conventional method as shown in fig. 1, a local sequence is formed by a known synchronization address (and BPSK mapping is performed, that is, 0 is mapped to-1, and 1 is mapped to 1), the input sequence is a received GFSK waveform, and the output is a cross-correlation value of the input sequence and the local sequence, in the bluetooth 5 system, n is 256 for a non-coding mode, and n is 2048 for a coding mode, assuming that the bit width of an input sampling point is W bits, the number of the input sampling points participating in the cross-correlation operation is n × W, and the sampling points need to be stored in corresponding storage units.
Therefore, in the conventional synchronization mode, an n × W shift register, n multipliers and n adders are required, which directly results in too large circuit area and excessive dynamic power consumption of the circuit caused by circuit level inversion, and each shift operation drives the shift operation of the whole storage unit, so that the power consumption of the whole synchronization circuit is greatly increased, which is not beneficial to the realization of a bluetooth low-power chip.
In view of the above, it is an urgent need to solve the problem of the art to provide a scheme capable of greatly simplifying a synchronization circuit and reducing power consumption and cost of a synchronization circuit of a receiver.
Disclosure of Invention
In view of this, the present application provides a method and an apparatus for simplifying a synchronization circuit, so as to reduce power consumption and cost of a synchronization circuit of a receiver on the basis of greatly simplifying the synchronization circuit.
In order to achieve the purpose, the application provides the following technical scheme:
a method for simplifying a synchronization circuit, the method comprising:
storing an input GFSK signal sampling point in a static random access memory;
reading a signal sampling point stored in the static random access memory according to a preset rule;
calculating the cross-correlation value of the current signal sampling point and the local synchronous sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
Preferably, the specification of the static random access memory is 16 × 128W, where W is a word width of one sampling point of the GFSK signal.
Preferably, the reading the signal sampling points stored in the static random access memory according to the preset rule includes:
and reading one row each time according to a read-then-write rule until the required signal sampling point data stored in the static random access memory is read out.
Preferably, when in the bluetooth communication mode without the coding mode at 8 times of the symbol oversampling rate, the current cross-correlation value is calculated by using the following iterative formula:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1Is the iteration increment.
Preferably, when in the bluetooth communication mode with the coding mode at the symbol oversampling rate of 8 times, the current cross-correlation value is calculated by using the following iterative formula:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.. 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
An apparatus for simplifying a synchronization circuit, the apparatus comprising:
the storage unit is used for storing the sampling point of the input GFSK signal in the static random access memory;
the reading unit is used for reading the signal sampling points stored in the static random access memory according to a preset rule;
the calculating unit is used for calculating the cross-correlation value of the current signal sampling point and the local synchronization sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
Preferably, the specification of the static random access memory is 16 × 128W, where W is a word width of one sampling point of the GFSK signal.
Preferably, the reading unit is specifically configured to read one row at a time according to a rule of reading first and then writing until the required signal sampling point data stored in the static random access memory is read.
Preferably, when in the bluetooth communication mode without the coding mode at 8 times of the symbol oversampling rate, the current cross-correlation value is calculated by using the following iterative formula:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1Is the iteration increment.
Preferably, when in the bluetooth communication mode with the coding mode at the symbol oversampling rate of 8 times, the current cross-correlation value is calculated by using the following iterative formula:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.., 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
According to the technical scheme, the method and the device for simplifying the synchronous circuit are provided, the static random access memory is adopted to store the GFSK signal sampling points, the chip area is reduced, and the shifting register storage unit is not used for storing the input GFSK signal sampling points, so that the power consumption caused by shifting is avoided; in addition, the cross-correlation value in the synchronous circuit is calculated in an iterative mode, and circuit implementation is greatly simplified. Therefore, the scheme provided by the application not only simplifies the circuit structure, reduces the realization area and the cost of the circuit, but also greatly reduces the dynamic power consumption of the circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional synchronous circuit;
FIG. 2 is a diagram of a Bluetooth packet structure in a no-code mode;
FIG. 3 is a diagram of a Bluetooth packet structure in a coding mode;
FIG. 4 is a flowchart of a method for simplifying a synchronization circuit according to an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating the specification of an SRAM provided in the present application;
fig. 6 is a schematic structural diagram of an apparatus for simplifying a synchronization algorithm according to a third embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention designs a synchronous circuit implementation mode with low complexity and low power consumption based on a reusable framework aiming at four data rate modes of a Bluetooth low power consumption standard, as shown in fig. 2 and fig. 3, fig. 2 is a Bluetooth packet structure under a non-coding mode, fig. 3 is a Bluetooth packet structure under a coding mode, in the figure, CRC is a cyclic redundancy check code, CI is a coding flag bit, TERM is a coding end symbol, FEC is a forward error correction code, a synchronous address is used for synchronizing information transmitted by a transmitter by a receiver, for the non-coding mode, the synchronous address is 32 symbols, for the coding mode, the synchronous address is 256 symbols, a synchronous circuit of the receiver completes synchronization of symbol information by using the synchronous addresses, and further completes recovery of other timing information of the symbols, in the traditional synchronous mode, a shift register of n × W is needed, n multipliers and n adders are needed, so that a final value can be obtained, two problems are brought to the circuit implementation mode that the area of the circuit is too large, the register is formed by a trigger, the size is larger than a digital storage tool which is used for generating a corresponding dynamic circuit, and the whole circuit is not beneficial to realize the whole low power consumption of the whole circuit.
In order to reduce the power consumption and the cost of a synchronous circuit of a receiver on the basis of greatly simplifying the synchronous circuit, the application provides a method and a device for simplifying the synchronous circuit, and the specific scheme is as follows:
example one
The embodiment of the application provides a method for simplifying a synchronization algorithm, which is applied to a receiver of a gaussian frequency shift keying communication system, in general, the receiver of the gaussian frequency shift keying communication system receives an air signal, converts the air signal into a digital signal through an ADC (analog to digital converter), demodulates the digital signal into a frequency domain to form a GFSK signal waveform, and then a synchronization circuit of the receiver detects a synchronization address of the input GFSK signal waveform under a multiple symbol sampling rate. In this application we use the 8 times symbol oversampling rate which is relatively common, of course, other oversampling rates can be referred to, and the implementation of the synchronization circuit described in this invention is not limited to the symbol oversampling rate. As shown in fig. 4, fig. 4 is a flowchart of a method for simplifying a synchronization circuit according to an embodiment of the present application. The method comprises the following steps:
s101: storing an input GFSK signal sampling point in a static random access memory;
in the present application, the sampling point of the input GFSK signal is stored by a static random access memory.
For the coded bluetooth mode, the number m of the history sampling points which need to be read simultaneously is 32, and the required specification of the SRAM is 8 × (32W), for the coded bluetooth mode, the number m of the history sampling points which need to be read simultaneously is 128, and the required specification of the SRAM is 16 × (128W), wherein W is the word width of a single sampling point, in order to multiplex the SRAM and reduce the area of a memory cell, the adopted specification of the SRAM is 16 × (128W), and the specific specification structure is shown in fig. 5.
S102: reading a signal sampling point stored in a static random access memory according to a preset rule;
specifically, according to the rule of reading first and then writing, reading one row each time until the required signal sampling point data stored in the static random access memory is read out.
Taking a word as a unit and taking an encoding mode as an example, the read-write rule of the storage unit of the synchronous circuit is as follows:
1. the read-then-write rule is followed, that is, under the same read-write clock, the data of the corresponding address is read first, and then the new data is written into the corresponding storage address, thereby avoiding the conflict of reading and writing the same address.
2. Each time, one line is read, 128 words are summed, and 16 lines are read in a head-to-tail loop mode, that is, after the 128 words in the 16 th line are read by the current read clock, the 128 words in the 1 st line are read by the next read clock, so as to form a closed loop which is connected end to end.
3. Each time a word is written, each row of memory cells is filled sequentially, then the next row is filled, and 2048 cells are written end to end in a cycle.
If the mode is a non-coding mode, only the first 8 rows and the first 32 columns of storage units are needed to be used, and the read-write rule of the storage units of the synchronous circuit is as follows:
1. the read-then-write rule is followed.
2. Reading one row at a time, for a total of 128 words (only the first 32 words are used to calculate the cross-correlation value); 8 rows read end-to-end in a loop.
3. Each time a word is written, each column of memory cells is filled sequentially, then the next column (32 columns used in total) is filled, and 256 cells are written end-to-end in a cyclic manner.
Other specification structures may be derived according to the memory structure and the read/write rules, and the present invention is not limited to the memory structure shown in fig. 5. For example:
1. the memory may also be multiple blocks (e.g., two blocks) and then patched together into one block for operation.
2. The memory may also be modified to other aspect ratios, but the underlying idea is based on the teachings of the invention.
S103: calculating the cross-correlation value of the current signal sampling point and the local synchronous sequence by using an iterative algorithm;
wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
In the application, the cross-correlation value is calculated by using an iterative algorithm, so that the use of n multipliers and n adders in a synchronous circuit is avoided, and the circuit implementation is greatly simplified.
According to the technical scheme, the method for simplifying the synchronization algorithm reduces the chip area by adopting the static random access memory to store the GFSK signal sampling points, and avoids power consumption caused by shifting because a shift register storage unit is not used for storing the input GFSK signal sampling points; in addition, the cross-correlation value in the synchronous circuit is calculated in an iterative mode, and circuit implementation is greatly simplified. Therefore, the scheme provided by the application not only simplifies the circuit structure, reduces the realization area and the cost of the circuit, but also greatly reduces the dynamic power consumption of the circuit.
Example two
On the basis of the first embodiment, the second embodiment of the present application provides a more specific method for simplifying the synchronization algorithm, and the general steps are still shown with reference to fig. 4.
Specifically, in the synchronization algorithm, the local sequence may be replaced by an FSK signal for convenience (i.e., the synchronization address sequence is copied at the symbol oversampling rate and BPSK mapped). An iterative formula for calculating the cross-correlation value of the GFSK signal and the local sequence in the non-coding mode is briefly derived as follows:
an iteration difference can be obtained:
therefore:
wherein P in the above formula is a local synchronization sequence with 8 times symbol oversampling rate corresponding to the synchronization address, P is a local synchronization sequence corresponding to the synchronization address, and xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
In the formula (1), the iterative relationship of the iterative algorithm is shown, and it is not difficult to see that, in the calculation of each iteration increment, corresponding input sampling points need to be uniformly extracted from the input sampling point storage unit, one extraction rule is extracted for each 8 sampling points, the current cross-correlation value is the last cross-correlation value plus the iteration increment, the initial cross-correlation value can be set to zero, and meanwhile, the initial value of the storage unit also needs to be set to zero.
That is, when in the bluetooth communication mode without the coding mode at the symbol oversampling rate of 8 times, the current cross-correlation value is calculated using the following iterative formula:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1For the iteration increment, k is 1, 2, 3.
Similarly, an iterative formula (2) of the cross-correlation value of the GFSK signal and the local sequence in the coding mode can be obtained:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2，i＝0，1，2，...，63
The iterative formula shown in formula (2) takes into account the bit mapping relationship with the coding mode, i.e.: the bluetooth system maps bit 0 to 0011 and bit 1 to 1100 as specified by the coding mode.
As can be seen from formula (2), for the coding mode, for the calculation of each iteration increment, corresponding input sampling points need to be uniformly extracted from the input sampling point storage unit, an extraction rule is to extract one sampling point for each 16 sampling points, the current cross-correlation value is the last cross-correlation value plus the iteration increment, the initial cross-correlation value can be set to zero, and meanwhile, the initial value of the storage unit should also be set to zero.
That is, when in the bluetooth communication mode with the coding mode at the symbol oversampling rate of 8 times, the current cross-correlation value is calculated using the following iterative formula:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.., 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
Compared with the traditional original algorithm, the synchronization circuit of the Bluetooth low-power consumption receiver is greatly simplified. Meanwhile, the static memories with extremely high power consumption and area are combined to realize the algorithms of the formulas (1) and (2), so that the circuit structure is simplified, the realization area and the cost of the circuit are reduced, and the dynamic power consumption of the circuit is greatly reduced.
EXAMPLE III
On the basis of the first embodiment, a third embodiment of the present application provides an apparatus for implementing the simplification method thereof, which is applied to a receiver of a gaussian frequency shift keying communication system, as shown in fig. 6, and fig. 6 is a schematic structural diagram of an apparatus for simplifying a synchronization algorithm provided in the third embodiment of the present application. The simplified apparatus includes: a storage unit 101, a reading unit 102, and a calculation unit 103, wherein,
the storage unit 101 is used for storing the input GFSK signal sampling points in the static random access memory;
in the present application, the specification of the static random access memory may be 16 × 128W, where W is a word width of one GFSK signal sampling point, and the specification is not limited in this application, and may be selected according to actual needs, for example, in the non-coded bluetooth mode, 8 × (32W) may be selected, or a bit larger than the specification of the static random access memory, and in the coded bluetooth mode, 16 × (128W) may be selected, or a bit larger than the specification of the static random access memory.
A reading unit 102, configured to read a signal sampling point stored in the sram according to a preset rule;
the reading unit is specifically configured to read one row at a time according to a read-then-write rule until the required signal sampling point data stored in the static random access memory is read out.
For the static random access memory, a whole row of data can be read at a time, and according to the read-write rule described in the first embodiment, the requirement that all the required data are read at a time and a new sampling point data is written can be met.
The calculating unit 103 is configured to calculate a cross-correlation value between a current signal sampling point and a local synchronization sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
The cross-correlation value is calculated by using an iterative algorithm, so that the use of n multipliers and n adders in a synchronous circuit is avoided, and the circuit implementation is greatly simplified.
According to the technical scheme, the device for simplifying the synchronization algorithm provided by the third embodiment of the application has the advantages that the static random access memory is adopted to store the GFSK signal sampling points, so that the chip area is reduced, and the shift register storage unit is not used for storing the input GFSK signal sampling points, so that the power consumption caused by shifting is avoided; in addition, the cross-correlation value in the synchronous circuit is calculated in an iterative mode, and circuit implementation is greatly simplified. Therefore, the scheme provided by the application not only simplifies the circuit structure, reduces the realization area and the cost of the circuit, but also greatly reduces the dynamic power consumption of the circuit.
Example four
On the basis of the third embodiment, the fourth embodiment of the present application provides a more specific simplified apparatus, which can implement the simplified method described in the second embodiment. The overall structure of the simplified device is shown in fig. 6. Specifically, when the current cross-correlation value is in a bluetooth communication mode without a coding mode at a symbol oversampling rate of 8 times, the current cross-correlation value is calculated by using the following iterative formula:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1Is the iteration increment.
When the current cross-correlation value is in a Bluetooth communication mode with a coding mode under the condition of 8 times of symbol oversampling rate, the current cross-correlation value is calculated by using the following iterative formula:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.., 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
According to the technical scheme, the device for simplifying the synchronization algorithm, which is provided by the fourth embodiment of the application, reduces the area of a chip by adopting the static random access memory to store the GFSK signal sampling points, and avoids power consumption caused by shifting because a shift register storage unit is not used for storing the input GFSK signal sampling points; in addition, the cross-correlation value in the synchronous circuit is calculated in an iterative mode, and circuit implementation is greatly simplified. Therefore, the scheme provided by the application not only simplifies the circuit structure, reduces the realization area and the cost of the circuit, but also greatly reduces the dynamic power consumption of the circuit.
Specifically, the same or similar parts between the embodiments may be referred to each other, and are not described in detail in this application.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for simplifying synchronization circuitry, the method being applied to a bluetooth communication system, comprising:
storing an input GFSK signal sampling point in a static random access memory;
reading a signal sampling point stored in the static random access memory according to a preset rule;
calculating the cross-correlation value of the current signal sampling point and the local synchronous sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
2. The method of claim 1, wherein the static random access memory has a size of 16 x (128W), where W is the word width of one sample point of the GFSK signal.
3. The method according to claim 1, wherein the reading the signal sampling points stored in the static random access memory according to the preset rule comprises:
and reading one row each time according to a read-then-write rule until the required signal sampling point data stored in the static random access memory is read out.
4. The method of claim 1, wherein the current cross-correlation value is calculated using the following iterative formula when in a bluetooth communication mode without a coding mode at 8 times symbol oversampling rate:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1Is the iteration increment.
5. The method of claim 1, wherein the current cross-correlation value is calculated using the following iterative formula when in a bluetooth communication mode with a coding mode at 8 times symbol oversampling rate:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.., 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
6. An apparatus for simplifying a synchronization circuit, the apparatus being applied to a bluetooth communication system, comprising:
the storage unit is used for storing the sampling point of the input GFSK signal in the static random access memory;
the reading unit is used for reading the signal sampling points stored in the static random access memory according to a preset rule;
the calculating unit is used for calculating the cross-correlation value of the current signal sampling point and the local synchronization sequence by using an iterative algorithm; wherein the initial cross-correlation value is set to zero, and the current cross-correlation value is the sum of the last cross-correlation value and the iteration increment.
7. The apparatus of claim 6, wherein the static random access memory has a size of 16 x (128W), where W is the word width of one sample point of the GFSK signal.
8. The apparatus of claim 6, wherein the reading unit is specifically configured to read one row at a time according to a read-then-write rule until the required signal sample point data stored in the SRAM is read out.
9. The apparatus of claim 6, wherein the current cross-correlation value is calculated using the following iterative formula when in a Bluetooth communication mode without a coding mode at 8 times symbol oversampling rate:
Ck+1′＝ΔC′k+1+C′k
＝((xk+8-xk)×P0+(xk+16-xk+8)×P1+...+(xk+256-xk+248)×P31)+C′k，
wherein P represents a local synchronization sequence corresponding to the synchronization address, xiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the kth output, Δ C'k+1Is the iteration increment.
10. The apparatus of claim 6, wherein the current cross-correlation value is calculated using the following iterative formula when in a Bluetooth communication mode with a coding mode at a symbol oversampling rate of 8 times:
C′k+1＝((xk+16-xk)×P0+(xk+32-xk+16)×P2+…+(xk+2048-xk+2032)×P254)+C′k
wherein, P4i＝-P4i+2I-0, 1, 2.., 63, P denotes a local sync sequence corresponding to a sync address, and x denotes a local sync sequence corresponding to a sync addressiIs an input GFSK signal sampling point, C'kIs the cross-correlation result of the k-th output.
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