CN109360005B - Radio frequency chip, electronic tag and identification method thereof - Google Patents
Radio frequency chip, electronic tag and identification method thereof Download PDFInfo
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- CN109360005B CN109360005B CN201811190507.2A CN201811190507A CN109360005B CN 109360005 B CN109360005 B CN 109360005B CN 201811190507 A CN201811190507 A CN 201811190507A CN 109360005 B CN109360005 B CN 109360005B
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Abstract
The invention discloses a radio frequency chip, an electronic tag and an identification method thereof. The method comprises the following steps: a first antenna connection portion and a second antenna connection portion; a third antenna connection section; the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, and the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part; and the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting part, the control output end is connected with the fourth end of the adjustable capacitor circuit, and the signal processing circuit is used for outputting a control signal to the fourth end of the adjustable capacitor circuit according to signals input by the first input end and the second input end of the signal processing circuit. Whether the electronic label is transferred can be judged by detecting the change of the basic physical characteristics on the chip bonding pad, and the counterfeiting cost is increased by using the unpredictability and randomness of the physical characteristics.
Description
Technical Field
The embodiment of the invention relates to a radio frequency identification technology, in particular to a radio frequency chip, an electronic tag and an identification method thereof.
Background
With the widespread application of electronic tags in retail markets, the necessity of electronic tag anti-counterfeiting has gradually attracted attention. By tearing the genuine product label off from the genuine product and attaching it to the inferior product, there are more and more cases of selling counterfeit and shoddy products. Various electronic tag chip anti-transfer technologies exist in the prior art, but most of the electronic tag chip anti-transfer technologies are based on the characteristic of utilizing special packaging materials, so that the prior art is greatly influenced by material cost.
Disclosure of Invention
The invention provides a radio frequency chip, an electronic tag and an identification method thereof, which aim to realize the anti-transfer of the electronic tag by using basic physical and electrical characteristics.
In a first aspect, an embodiment of the present invention provides a radio frequency chip, including:
a first antenna connection part and a second antenna connection part for connecting an antenna;
a third antenna connection section;
the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part, and the adjustable capacitor circuit can adjust the capacitance between the third end and the first end and between the third end and the second end according to a control signal of an input end of the fourth end;
the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting portion, the control signal output end is connected with the fourth end of the adjustable capacitor circuit, and the signal processing circuit is used for outputting a control signal to the fourth end of the adjustable capacitor circuit according to signals input by the first input end and the second input end of the signal processing circuit.
In a second aspect, an embodiment of the present invention further provides an electronic tag, where the electronic tag includes any one of the radio frequency chips described above and an antenna, and the antenna is connected to the first antenna connection portion and the second antenna connection portion of the radio frequency chip.
In a third aspect, an embodiment of the present invention further provides an identification method of an electronic tag, where the electronic tag includes a radio frequency chip and an antenna, the radio frequency chip includes a first antenna connection portion and a second antenna connection portion, and the first antenna connection portion and the second antenna connection portion are connected to the antenna; a third antenna connection section; the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part, and the adjustable capacitor circuit can adjust the capacitance between the third end and the first end and between the third end and the second end according to a control signal of an input end of the fourth end; the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting part, and the control signal output end is connected with the fourth end of the adjustable capacitor circuit;
the identification method of the electronic tag comprises the following steps: a control signal output end of the signal processing circuit outputs a control signal to a fourth end of the adjustable capacitor circuit, and when signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a first control signal;
after the first control signal is determined, the control signal output end of the signal processing circuit outputs a control signal to the fourth end of the adjustable capacitor circuit, and when the signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a second control signal.
The invention solves the problem of identifying whether the electronic tag is transferred by adopting the radio frequency chip comprising the third antenna connecting part, the first antenna connecting part, the second antenna connecting part, the adjustable capacitor circuit and the signal processing circuit and by adopting the electronic tag of the radio frequency identification chip and utilizing the identification method of the chip in the electronic tag, and realizes the effect of judging whether the electronic tag is transferred by detecting the change of the basic physical and electrical characteristics of the bonding pad.
Drawings
Fig. 1 is a schematic circuit structure diagram of a radio frequency chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a radio frequency chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a connection circuit between a radio frequency chip and an antenna according to an embodiment of the present invention;
fig. 4 is a schematic view of a connection structure between a radio frequency chip and an antenna according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a switched capacitor array circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a signal processing circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another signal processing circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a circuit structure of an electronic tag according to an embodiment of the present invention;
fig. 9 is a schematic view of a connection structure between a radio frequency chip and an antenna according to another embodiment of the present invention;
fig. 10 is a schematic view of a connection structure between a radio frequency chip and an antenna according to another embodiment of the present invention;
fig. 11 is a flowchart of an identification method of an electronic tag according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a read-write process of an electronic tag according to an embodiment of the present invention;
fig. 13 is a flowchart of another method for identifying an electronic tag according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Examples
Fig. 1 is a schematic circuit structure diagram of a radio frequency chip according to an embodiment of the present invention, and fig. 2 is a schematic structure diagram of a radio frequency chip according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, a radio frequency chip 101 includes a first antenna connection portion 102 and a second antenna connection portion 103 for connecting an antenna.
A third antenna connection portion 104;
an adjustable capacitor circuit 105, wherein the adjustable capacitor circuit 105 includes a first end a, a second end B, a third end C and a fourth end D, the first end a and the second end B of the adjustable capacitor circuit 105 are respectively connected to the first antenna connection portion 102 and the second antenna connection portion 103, and the adjustable capacitor circuit 105 can adjust the capacitance between the third end C and the first end a and between the third end C and the second end B according to a control signal at the input end of the fourth end D;
the signal processing circuit 106 includes a first input end E, a second input end F, and a control signal output end G, the first input end E is connected to the third end C of the tunable capacitor circuit 105, the second input end F is connected to the third antenna connection portion 104, the control signal output end G is connected to the fourth end D of the tunable capacitor circuit 105, and the signal processing circuit 106 is configured to output a control signal to the fourth end D of the tunable capacitor circuit 105 according to signals input by the first input end E and the second input end F.
Specifically, with continued reference to fig. 2, the first antenna connection portion 102, the second antenna connection portion 103, the third antenna connection portion 104, the tunable capacitor circuit 105, and the signal processing circuit 106 may be disposed on the same layer of the rf chip 101, or may be disposed on different layers. The number of the fourth control signal terminals of the tunable capacitor circuit 105 may be multiple, and the control signal output by the control signal output terminal G of the signal processing circuit 106 to each fourth control signal terminal may form a group of switch control signals. Referring to fig. 3 to 4, fig. 3 is a schematic diagram of a connection circuit between a radio frequency chip and an antenna according to an embodiment of the present invention, fig. 4 is a schematic diagram of a connection structure between a radio frequency chip and an antenna according to an embodiment of the present invention, where a first antenna connection portion 102 and a second antenna connection portion 103 are respectively connected to a first chip connection portion 602 and a second chip connection portion 603 of an antenna 601, a third antenna connection portion 104 is connected to a third chip connection portion 606, and a parasitic capacitance is generated between the third antenna connection portion and a pad of the antenna, specifically, a parasitic capacitance is generated between the third antenna connection portion 104 and the first chip connection portion 602 and the second chip connection portion of the antenna, and since the antenna and the chip are soldered together, it can also be understood that a parasitic capacitance is generated between the third chip connection portion 606 and the first chip connection portion and the second chip connection portion 603, when the radio frequency chip 101 leaves a factory, the rf chip of the genuine product and the genuine product antenna are soldered together, the parasitic capacitance between the third antenna connection portion 104 and the pad of the genuine product antenna is also fixed, the signal processing circuit 106 can have an auto-tuning function, the signal processing circuit 106 is tuned to match C _ int1/C _ int2 with C _ ext1/C _ ext2, at this time, the signal output from the control signal output terminal G of the signal processing circuit 106 to the fourth control signal terminal is the first set of switch control signals, wherein C _ int1 is a capacitance value between the third terminal C and the first terminal a of the tunable capacitor circuit 105, C _ int2 is a capacitance value between the third terminal C and the second terminal B of the tunable capacitor circuit 105, C _ ext1 is a capacitance value between the third antenna connection portion 104 and the first chip connection portion 602, and C _ ext2 is a capacitance value between the third antenna connection portion 104 and the second chip connection portion 603; and store the gear (first group of switch control signals) adjusted, when the certified chip is torn off and attached to another antenna, because the positions, angles, etc. of the antenna and the chip are not completely the same, the parasitic capacitance between the third antenna connection portion 104 and the antenna pad to be re-welded will change, at this moment, the signal processing circuit 106 restarts the auto-tuning function, so that the capacitance value of the adjustable capacitance circuit 105 matches with the parasitic capacitance value between the third antenna connection portion 104 and the antenna pad to be re-welded, and the gear is also stored, when judging whether the chip is transferred, it can be judged that the chip is transferred only by judging that the difference between the two gears exceeds the set error.
According to the embodiment of the invention, the radio frequency chip comprises the third antenna connecting part, the first antenna connecting part, the second antenna connecting part, the adjustable capacitor circuit and the signal processing circuit, when the chip is transferred, because the parasitic capacitance between the third antenna connecting part and the antenna bonding pad changes, the signal processing circuit can detect the change of the parasitic capacitance and simultaneously adjust the capacitance value of the adjustable capacitor circuit to enable the parasitic capacitance and the adjustable capacitor circuit to be matched, and records two matched gears to judge whether the chip is transferred, so that the problem of identifying whether the chip is transferred is solved, and the effect of judging whether the chip is transferred by using basic physical electrical characteristics is realized.
With continued reference to fig. 2, the rf chip 101 includes a first side and a second side that are disposed opposite to each other, and the first antenna connection portion 102, the second antenna connection portion 103, and the third antenna connection portion 104 are pads disposed on the first side of the rf chip 101.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a switched capacitor array circuit according to an embodiment of the present invention, in which the adjustable capacitor circuit 105 is a switched capacitor array circuit, the adjustable capacitor circuit 105 includes a plurality of branches, each branch includes a capacitor and a switch connected in series; one branch or at least two branches connected in parallel is included between the third terminal C and the first terminal a of the adjustable capacitor circuit 105, and one branch or at least two branches connected in parallel is included between the third terminal C and the second terminal B of the adjustable capacitor circuit.
With continued reference to fig. 5, capacitor 201 and switch 202 form a first branch, capacitor 205 and switch 206 form a second branch, switch 203 and capacitor 204 form a third branch, switch 207 and capacitor 208 form a fourth branch, the first and second branches are connected in parallel between first terminal a and third terminal C of adjustable capacitance circuit 105, and the third and fourth branches are connected in parallel between second terminal B and third terminal C of adjustable capacitance circuit 105.
Optionally, more branches with the same structure are further included between the first branch and the second branch, and more branches with the same structure are further included between the third branch and the fourth branch.
The switch capacitor array 105 can control the switch on condition of each branch according to the input signal of the fourth signal input terminal D, i.e. adjust the equivalent capacitance between the first terminal a and the third terminal C and the equivalent capacitance between the second terminal B and the third terminal C, so that the voltage value between the first terminal a and the second terminal B changes at the potential of the third terminal C, thereby matching with the parasitic capacitance between the third antenna connection part and the antenna pad. And the structure of the parallel capacitor has relatively simple equivalent capacitance value calculation, and can improve the processing efficiency of the signal processing circuit.
Optionally, a combination structure of series connection and parallel connection of a plurality of branches may be included between the first terminal a and the third terminal C and between the second terminal B and the third terminal C, and the capacitance between the first terminal a and the third terminal C and the capacitance between the second terminal B and the third terminal C may also be adjusted.
According to the embodiment of the invention, the adjustable capacitor circuit formed by the switched capacitor array is used, so that the capacitance value of the adjustable capacitor circuit can be simply and conveniently adjusted, the capacitance value of the adjustable capacitor circuit is matched with the capacitance value between the third antenna connecting part and the antenna bonding pad, and whether the chip is transferred or not can be conveniently judged subsequently.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a signal processing circuit according to an embodiment of the present invention, where the signal processing circuit 106 includes a comparing module 301 and a processor 302;
a first input end and a second input end of the comparison module 301 are respectively used as a first input end E and a second input end F of the signal processing circuit 106, and an output end of the comparison module 301 is connected with an input end of the processor 302;
optionally, the comparing module 301 may be a comparator.
The comparison module is used for outputting a first comparison signal to the processor when the amplitude of the input signal of the second input end is greater than the amplitude of the input signal of the first input end to a preset value, and the processor adjusts the ratio of the capacitance between the first end and the third end of the adjustable capacitance circuit to the capacitance between the second end and the third end to be increased according to the first comparison signal, wherein the preset value can be set to be 5% of the amplitude of the input signal of the first input end;
when the amplitude of the input signal at the second input end is smaller than the amplitude of the input signal at the first input end to a preset value, the comparison module outputs a second comparison signal to the processor, and the processor adjusts the ratio of the capacitance between the first end and the third end of the adjustable capacitance circuit to the capacitance between the second end and the third end of the adjustable capacitance circuit to be smaller according to the second comparison signal, wherein the preset value can be set to be 5% of the amplitude of the input signal at the first input end;
when the absolute value of the difference between the amplitude of the input signal at the first input end and the amplitude of the input signal at the second input end does not exceed the preset value, the comparison module outputs a third comparison signal to the processor, and the processor maintains the ratio between the capacitance between the first end and the third end of the adjustable capacitance circuit and the capacitance between the second end and the third end of the adjustable capacitance circuit constant according to the third comparison signal, for example, the preset value may be set to 5% of the amplitude of the input signal at the first input end.
An output terminal of the processor 302 serves as a control signal output terminal of the signal processing circuit 106, and an output terminal of the processor 302 is connected to a control terminal of the switch.
When the signals input by the two input ends of the comparison module 301 are different, for example, when the comparison module is a comparator, the first input end inputs a sine wave with a larger amplitude, and the second input end inputs a sine wave with the same frequency and phase as the first input end but a smaller amplitude, the output end of the comparison module outputs a square wave with the same frequency and phase as the first input end, the processor makes the signals input by the two input ends of the comparison module the same by adjusting the capacitance value of the adjustable capacitor, that is, the output of the comparison module is in a critical state, and the conversion of any one input end can cause the output signal of the output end to be in reverse phase with the previous one.
According to the embodiment of the invention, the signal processing circuit composed of the comparison module and the processor is adopted, the third antenna connecting part and the third end of the adjustable capacitor circuit are respectively connected to the two input ends of the comparison module, the comparison result is transmitted to the processor, and the processor is used for carrying out subsequent processing, so that whether the chip is transferred or not is conveniently judged.
Referring to fig. 7, fig. 7 is a schematic structural diagram of another signal processing circuit according to an embodiment of the present invention, wherein the signal processing circuit 106 further includes a modulation circuit 401.
The processor 302 is connected to the first antenna connection portion and the second antenna connection portion through the modulation circuit 401, respectively.
The modulation circuit 401 includes a circuit configuration for modulating a signal to be modulated of the processor 302 into a radio frequency signal that can be transmitted by the antenna and a circuit for modulating a signal received from the antenna into a signal that can be processed by the processor 302. It will be readily appreciated that the connection between the processor and the modulation circuit comprises at least one, and the specific structure of the modulation circuit in figure 7 is well known to those skilled in the art.
According to the technical scheme, the processor is connected with the first antenna connecting part and the second antenna connecting part through the modulation circuit, so that the communication problem between the processor and the antenna is solved, and the effects that the processor receives the read-write instruction of the external circuit and feeds back the processing result to the external circuit are achieved.
With continued reference to fig. 4, the connection structure of the rf chip and the antenna in fig. 4 integrally forms an electronic tag, which includes the rf chip 101 and the antenna 601 in any embodiment, and the antenna 601 is connected to the first antenna connection portion 102, the second antenna connection portion 103, and the third antenna connection portion 606 of the rf chip 101.
The third chip connecting portion 606 is disposed on the antenna 601, and when the third chip connecting portion 606 is welded to the third antenna connecting portion 104, the situation that the parasitic capacitance cannot be detected due to the small parasitic capacitance of the third antenna connecting portion 104 can be avoided.
Referring to fig. 8, fig. 8 is a schematic diagram of an electronic tag circuit structure according to an embodiment of the present invention, which may correspond to the structure shown in fig. 4, wherein a first parasitic capacitor 604 is formed between the third antenna connection portion 104 and the first chip connection portion 602, and a second parasitic capacitor 605 is formed between the third antenna connection portion 104 and the second chip connection portion 603, when the rf chip enters a read-write electromagnetic field provided by an external circuit, a signal V _ ANT with a larger amplitude is generated between the first chip connection portion 602 and the second chip connection portion 603, and since the first antenna connection portion 102 and the first chip connection portion 602 are welded together and the second antenna connection portion 103 and the second chip connection portion 603 are welded together, it can also be understood that a signal V _ ANT with a larger amplitude is generated between the first antenna connection portion 102 and the second antenna connection portion 103, and all the V _ ANT passes through the adjustable capacitor circuit 105, due to the voltage division effect of the capacitance between the first terminal a and the third terminal C of the adjustable capacitance circuit 105 and the capacitance between the second terminal B and the third terminal C, a signal V _ REF with a smaller amplitude is generated at the third terminal C and is input to the first input terminal E of the comparison module; the other path of V _ ANT outputs another smaller signal V _ DEF to the second input terminal F of the comparison module through the voltage division effect of the first parasitic capacitor 606 and the second parasitic capacitor 605. When the amplitude of V _ DEF is greater than the amplitude of V _ REF to a preset value, for example, the preset value may be set to be 5% of the amplitude of V _ REF, the comparing module 301 outputs a first comparison signal to the processor 302, and the processor 302 outputs a switch control signal through the control signal output terminal G according to the first comparison signal output by the comparing module 301, so as to control the switch in the branch circuit to be turned on or off, thereby adjusting a ratio between a capacitance between the first terminal a and the third terminal C of the adjustable capacitance circuit 105 and a capacitance between the second terminal B and the third terminal C to be increased. When the amplitude of V _ DEF is smaller than the amplitude of V _ REF to a predetermined value, the comparing module 301 outputs a second comparison signal to the processor 302, so that the processor 302 outputs a switch control signal through the control signal output terminal G to control the switch in the branch circuit to be turned on or off, thereby adjusting the ratio of the capacitance between the first terminal a and the third terminal C of the adjustable capacitance circuit 105 to the capacitance between the second terminal B and the third terminal C to be smaller. When the absolute value of the difference between the amplitude of V _ DEF and the amplitude of V _ REF does not exceed the preset value, the comparing module 301 outputs a third comparison signal to the processor 302, so that the processor 302 outputs a switch control signal through the control signal output terminal G to control the switch in the branch circuit to be turned on or off, thereby adjusting the ratio between the capacitance between the first terminal a and the third terminal C of the adjustable capacitance circuit 105 and the capacitance between the second terminal B and the third terminal C to be unchanged. The processor outputs a switch control signal through the control signal output terminal G to adjust the capacitance between the first terminal a and the third terminal C and the capacitance between the second terminal B and the third terminal C of the adjustable capacitance circuit 105 until the absolute value of the difference between the amplitude of V _ DEF and the amplitude of V _ REF does not exceed a preset value, and at this time, the processor records the switch control signal (gear) output by adjustment. When the electronic tag leaves the factory, referring to fig. 4, fig. 4 may also be understood as a schematic diagram of a connection structure between the radio frequency chip and the antenna when the electronic tag leaves the factory, the processor 302 may automatically adjust to make the amplitude difference between V _ DEF and V _ REF within a preset value, and record a gear adjusted at this time, when the electronic tag is transferred, referring to fig. 9 and fig. 10, fig. 9 is a schematic diagram of a connection structure between the radio frequency chip and the antenna according to an embodiment of the present invention, fig. 10 is a schematic diagram of a connection structure between the radio frequency chip and the antenna according to an embodiment of the present invention, which may be understood as a schematic diagram of a connection structure between the radio frequency chip and the antenna when the radio frequency chip is transferred to another antenna, the radio frequency chip is attached to another antenna, at this time, a ratio between the first parasitic capacitor 604 and the second parasitic capacitor 605 changes, and when the radio frequency chip enters a magnetic field for reading and writing, the processor 302 may readjust, and enabling the amplitude difference between the V _ DEF and the V _ REF to be within a preset value, recording the gear adjusted at the moment, and if the difference between the two gears is large, such as 5% difference, judging that the electronic tag is transferred. The processor 302 may send the information of the two gears to the reader/writer through the modulation circuit, and the reader/writer may determine whether the two gears differ by a certain magnitude, or the processor may determine whether the two gears differ by a certain magnitude and directly send the determination result to the reader/writer. Meanwhile, the processor can also send other information of the electronic tag to the reader-writer. It should be noted that, if the difference between the two gear differences is 5%, it may be determined that the electronic tag has been transferred only as an example, and the difference between the two gear differences may also be another proportional value, which may be determined specifically according to the electronic tag used, for example, whether the electronic tag has been transferred is determined according to different processes and use environments.
According to the technical scheme of the embodiment, the electronic tag formed by the radio frequency chip and the antenna is adopted, and when the radio frequency chip is transferred, whether the electronic tag is transferred can be identified by judging the change of the gear value.
Optionally, the antenna 601 includes a first chip connection portion 601, a second chip connection portion 603, and a third chip connection portion 606, where the first chip connection portion 601, the second chip connection portion 603, and the third chip connection portion 606 are all bonding pads, the first antenna connection portion 102 is connected to the first chip connection portion 602, the second antenna connection portion 103 is connected to the second chip connection portion 603, and the third antenna connection portion 104 is connected to the third chip connection portion 606, and at this time, a first parasitic capacitor 604 is generated between the first antenna connection portion 102 and the third chip connection portion 606, and a second parasitic capacitor 605 is generated between the second antenna connection portion 103 and the third chip connection portion 606. The first chip connection portion 602, the second chip connection portion 603, and the third chip connection portion 606 are all in a predetermined positional relationship.
The first chip connecting portion 602, the second chip connecting portion 603, and the third chip connecting portion 606 are all in a preset positional relationship, and when each chip leaves a factory, the positional relationship among the first chip connecting portion 602, the second chip connecting portion 603, and the third chip connecting portion 606 may be set to be different, referring to fig. 9 and 10, it can also be understood that fig. 9 and 10 refer to that when the chip leaves the factory, the first chip connecting portion 602, the second chip connecting portion 603, and the third chip connecting portion 606 are set to be in the preset positional relationship, so that the proportional relationship between the first parasitic capacitor 604 and the second parasitic capacitor 605 is different, that is, the initial gears of the processors are not completely the same, and the parasitic capacitance value of the electronic tag is prevented from being broken and copied in batch, and the counterfeit cost is increased. Meanwhile, when the radio frequency chip and the antenna are packaged, the bonding angle and the contact area between the bonding pads are random, so that the ratio of the first parasitic capacitance to the second parasitic capacitance is discrete when each electronic tag leaves a factory, and batch copying is more difficult.
According to the technical scheme, the electronic tag consisting of the antenna and the radio frequency chip is adopted, and the parasitic capacitance exists between the antenna and the radio frequency chip, so that the problem of judging whether the electronic tag is transferred or not is solved by judging the change of the parasitic capacitance, and the effect of simply judging whether the electronic tag is transferred or not is achieved. Meanwhile, when each electronic tag is set to leave a factory, the parasitic capacitance proportion is different, the problem that the electronic tags are easy to copy in batches is solved, and the effect of increasing the counterfeiting cost is achieved.
Referring to fig. 11, fig. 11 is a flowchart of an identification method of an electronic tag according to an embodiment of the present invention, which can be used to identify the electronic tag according to any embodiment of the present invention, wherein,
the electronic tag comprises a radio frequency chip and an antenna, wherein the radio frequency chip comprises a first antenna connecting part and a second antenna connecting part, and the first antenna connecting part and the second antenna connecting part are connected with the antenna; a third antenna connection section; the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, wherein the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part, and the adjustable capacitor circuit can adjust the capacitance between the third end and the first end and between the third end and the second end according to a control signal of the input end of the fourth end; the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting part, and the control signal output end is connected with the fourth end of the adjustable capacitor circuit;
the electronic tag identification method comprises the following steps:
illustratively, when the electronic tag enters the reading and writing electromagnetic field again, the first input end input signal of the signal processing circuit is V _ REF, the second input end input signal of the signal processing circuit is V _ DEF, when the amplitude of V _ DEF is larger than that of V _ REF to a preset value, for example, the preset value can be set to be 5% of that of V _ REF, and the control signal output end outputs a control signal to control the ratio of the capacitance between the first end and the third end of the adjustable capacitance circuit to the capacitance between the second end and the third end to be increased. When the amplitude of the V _ DEF is smaller than that of the V _ REF to a preset value, the control signal output end outputs a control signal to control the capacitance ratio between the first end and the third end of the adjustable capacitance circuit and the capacitance between the second end and the third end to be reduced. When the difference value between the amplitude of the V _ DEF and the amplitude of the V _ REF is within a preset value, the control signal output end outputs a control signal to control the capacitance ratio between the first end and the third end of the adjustable capacitance circuit and the capacitance between the second end and the third end to be unchanged. And recording the control signal at the moment as a first control signal.
When the electronic tag enters the reading and writing electromagnetic field again, the control function of the signal processing circuit is started again, and a signal when the signals input by the first input end and the second input end are matched is recorded as a second control signal.
The embodiment stores the control signals which are well matched twice when the electronic tag enters the electromagnetic field for the first time and enters the electromagnetic field again, so that the electronic tag is convenient to be processed by a subsequent processor.
Optionally, the processor may determine whether the second control signal is matched with the first control signal, refer to fig. 12, where fig. 12 is a schematic diagram of a read-write process of the electronic tag according to an embodiment of the present invention; if the processor judges whether the electronic tag is illegal, when a read-write instruction of the reader-writer is received, the feedback information at least comprises a judgment result of the processor, and if the second control signal is not matched with the first control signal, the signal processing circuit at least outputs a signal for identifying the radio frequency chip as illegal.
Specifically, if the difference between the gear in which the second control signal is located and the gear in which the first control signal is located exceeds a certain amplitude, it may be determined that the radio frequency chip is an illegal signal, which proves that the radio frequency chip has been transferred, and if the process of determining whether the tag is illegal is implemented by the signal processing circuit, the signal processing circuit directly outputs the radio frequency chip as illegal, for example, outputs a high level 1 indicating that the radio frequency signal is illegal. It will be appreciated that the output signal may also include the value of the TID (Tag Identifier).
Whether the radio frequency chip is illegal or not, namely whether the radio frequency chip is transferred or not is judged by judging whether the first control signal and the second control signal are matched, so that the effects of higher chip safety and difficulty in copying are achieved.
Optionally, in another embodiment of the present invention, the judging whether the radio frequency chip of the electronic tag is illegal may be completed by a reader, and accordingly, the chip identification method according to the embodiment of the present invention further includes:
if an instruction for acquiring the tag information is received, the signal processing circuit at least outputs a first control signal and a second control signal through the antenna.
For example, the reader/writer performs read/write operation on the electronic tag, the reader/writer sends a command for acquiring tag information to a signal processing circuit of the electronic tag through the antenna, and the electronic tag modulates information including the first control signal and the second control signal and other tag information onto an antenna carrier and returns the information to the reader/writer.
Specifically, when the electronic tag is initialized when it leaves the factory, the information of the first control signal and the TID value are read by the reader and bound together, and then stored in the background database.
After the electronic tag flows into the market, the electronic tag is verified through a reader-writer, the information of the second control signal and the TID value are read out, then the information of the first control signal bound by the TID is found from the database and is compared with the information of the second control signal, if the information of the second control signal and the information value of the first control signal exceed a certain set value, the illegal tag is judged, and the illegal tag is displayed from the reader-writer
Referring to fig. 13, fig. 13 is a diagram of another electronic tag identification method according to an embodiment of the present invention, in the other electronic tag identification method according to the embodiment of the present invention, an antenna includes a first chip connection portion, a second chip connection portion, and a third chip connection portion, the first chip connection portion is connected to the first antenna connection portion, the second chip connection portion is connected to the second antenna connection portion, and the third antenna connection portion is connected to the third chip connection portion; the adjustable capacitor circuit is a switched capacitor array circuit and comprises a plurality of branches, and each branch comprises a capacitor and a switch which are connected in series; at least two branches are connected in parallel between the third end and the first end of the adjustable capacitor circuit, and at least two branches are connected in parallel between the third end and the second end of the adjustable capacitor circuit;
the signal processing circuit comprises a comparison module and a processor;
the first input end and the second input end of the comparison module are respectively used as the first input end and the second input end of the signal processing circuit, and the output end of the comparison module is connected with the input end of the processor;
the output end of the processor is used as the control signal output end of the signal processing circuit, and the output end of the processor is connected with the control end of the switch;
According to the technical scheme, the electronic tag consisting of the antenna and the radio frequency chip is adopted, and the parasitic capacitance exists between the antenna and the radio frequency chip, so that the problem of judging whether the electronic tag is transferred or not is solved by judging the change of the parasitic capacitance, and the effect of simply judging whether the electronic tag is transferred or not is achieved. Meanwhile, when each electronic tag is set to leave a factory, the parasitic capacitance proportion is different, the problem that the electronic tags are easy to copy in batches is solved, and the effect of increasing the counterfeiting cost is achieved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A radio frequency chip, comprising:
a first antenna connection part and a second antenna connection part for connecting an antenna;
a third antenna connection section;
the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part, and the adjustable capacitor circuit can adjust the capacitance between the third end and the first end and between the third end and the second end according to a control signal of an input end of the fourth end;
the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting part, the control signal output end is connected with the fourth end of the adjustable capacitor circuit, and the signal processing circuit is used for outputting a control signal to the fourth end of the adjustable capacitor circuit according to signals input by the first input end and the second input end of the signal processing circuit;
the signal processing circuit is used for outputting a control signal to a fourth end of the adjustable capacitor circuit through a control signal output end of the signal processing circuit, and when signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a first control signal; after the first control signal is determined, the control signal output end of the signal processing circuit outputs a control signal to the fourth end of the adjustable capacitor circuit, and when the signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a second control signal; if the second control signal is not matched with the first control signal, the signal processing circuit at least outputs a signal for identifying the radio frequency chip as illegal.
2. The RF chip of claim 1, wherein the tunable capacitor circuit is a switched capacitor array circuit, the tunable capacitor circuit comprising a plurality of branches, the branches comprising a capacitor and a switch connected in series; the adjustable capacitor circuit comprises one branch or at least two parallel branches between a third end and a first end, and the adjustable capacitor circuit comprises one branch or at least two parallel branches between the third end and a second end.
3. The radio frequency chip of claim 2, wherein the signal processing circuit comprises a comparison module and a processor;
a first input end and a second input end of the comparison module are respectively used as a first input end and a second input end of the signal processing circuit, and an output end of the comparison module is connected with an input end of the processor;
the output end of the processor is used as the control signal output end of the signal processing circuit, and the output end of the processor is connected with the control end of the switch.
4. The RF chip according to claim 3, wherein the comparing module is configured to output a first comparing signal to the processor when the amplitude of the input signal at the second input terminal is greater than the amplitude of the input signal at the first input terminal by a predetermined value, and the processor adjusts a ratio of a capacitance between the first terminal and the third terminal of the tunable capacitance circuit to a capacitance between the second terminal and the third terminal of the tunable capacitance circuit to be larger according to the first comparing signal;
when the amplitude of the input signal of the second input end is smaller than the amplitude of the input signal of the first input end to a preset value, the comparison module outputs a second comparison signal to the processor, and the processor adjusts the capacitance ratio between the first end and the third end of the adjustable capacitance circuit and the capacitance ratio between the second end and the third end to be smaller according to the second comparison signal;
when the absolute value of the difference between the amplitude of the input signal at the first input end and the amplitude of the input signal at the second input end does not exceed a preset value, the comparison module outputs a third comparison signal to the processor, and the processor maintains the ratio of the capacitance between the first end and the third end of the adjustable capacitance circuit to the capacitance between the second end and the third end of the adjustable capacitance circuit unchanged according to the third comparison signal.
5. The radio frequency chip of claim 3, wherein: the signal processing circuit further comprises a modulation circuit;
the processor is connected with the first antenna connecting part and the second antenna connecting part through the modulation circuit respectively.
6. The RF chip according to claim 1, wherein the RF chip includes a first surface and a second surface opposite to each other, and the first antenna connection portion, the second antenna connection portion and the third antenna connection portion are pads disposed on the first surface of the RF chip.
7. An electronic tag, comprising: the radio frequency chip and antenna of any one of claims 1-6, the antenna connected to the first and second antenna connections of the radio frequency chip.
8. The electronic tag according to claim 7, characterized in that: the antenna comprises a first chip connecting portion, a second chip connecting portion and a third chip connecting portion, wherein the first chip connecting portion is connected with the first antenna connecting portion, the second chip connecting portion is connected with the second antenna connecting portion, the third chip connecting portion is connected with the third antenna connecting portion, and a preset position relation is formed between the first chip connecting portion, the second chip connecting portion and the third chip connecting portion.
9. The identification method of the electronic tag is characterized in that the electronic tag comprises a radio frequency chip and an antenna, the radio frequency chip comprises a first antenna connecting part and a second antenna connecting part, and the first antenna connecting part and the second antenna connecting part are connected with the antenna; a third antenna connection section; the adjustable capacitor circuit comprises a first end, a second end, a third end and a fourth end, the first end and the second end of the adjustable capacitor circuit are respectively connected with the first antenna connecting part and the second antenna connecting part, and the adjustable capacitor circuit can adjust the capacitance between the third end and the first end and between the third end and the second end according to a control signal of an input end of the fourth end; the signal processing circuit comprises a first input end, a second input end and a control signal output end, the first input end is connected with the third end of the adjustable capacitor circuit, the second input end is connected with the third antenna connecting part, and the control signal output end is connected with the fourth end of the adjustable capacitor circuit;
the identification method of the electronic tag comprises the following steps: a control signal output end of the signal processing circuit outputs a control signal to a fourth end of the adjustable capacitor circuit, and when signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a first control signal;
after the first control signal is determined, the control signal output end of the signal processing circuit outputs a control signal to the fourth end of the adjustable capacitor circuit, and when the signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a second control signal;
further comprising: if the second control signal is not matched with the first control signal, if an instruction for acquiring the label information is received, the signal processing circuit at least outputs a signal for identifying that the radio frequency chip is illegal.
10. The method for identifying an electronic tag according to claim 9, further comprising: and if an instruction for acquiring the label information is received, the signal processing circuit at least outputs the first control signal and the second control signal through an antenna.
11. The method according to claim 9, wherein the antenna includes a first chip connection portion, a second chip connection portion, and a third chip connection portion, the first chip connection portion is connected to the first antenna connection portion, the second chip connection portion is connected to the second antenna connection portion, and the third chip connection portion is connected to the third antenna connection portion; the adjustable capacitor circuit is a switched capacitor array circuit and comprises a plurality of branches, and each branch comprises a capacitor and a switch which are connected in series; the adjustable capacitor circuit comprises one branch or at least two parallel branches between a third end and a first end, and the adjustable capacitor circuit comprises one branch or at least two parallel branches between the third end and a second end;
the signal processing circuit comprises a comparison module and a processor;
a first input end and a second input end of the comparison module are respectively used as a first input end and a second input end of the signal processing circuit, and an output end of the comparison module is connected with an input end of the processor;
the output end of the processor is used as the control signal output end of the signal processing circuit, and the output end of the processor is connected with the control end of the switch;
the control signal output end of the signal processing circuit outputs a control signal to the fourth end of the adjustable capacitor circuit, and when the signals input by the first input end and the second input end are matched, the signal output by the control signal output end is a first control signal, which includes:
the processor is tuned and adjusted to match C _ int1/C _ int2 with C _ ext1/C _ ext2, and at this time, signals output to the switches are a first group of switch control signals, where C _ int1 is a capacitance value between a third end and a first end of the adjustable capacitance circuit, is a capacitance value between a third end and a second end of C _ int2 of the adjustable capacitance circuit, C _ ext1 is a capacitance value between the third antenna connection portion and the first chip connection portion, and C _ ext2 is a capacitance value between the third antenna connection portion and the second chip connection portion;
after determining the first control signal, the control signal output terminal of the signal processing circuit outputs a control signal to the fourth terminal of the tunable capacitor circuit, and when the signals input by the first input terminal and the second input terminal match, the signal output by the control signal output terminal is a second control signal, including:
after determining the first group of switch control signals, the processor is tuned to match C _ int1/C _ int2 with C _ ext1/C _ ext2, and when the signals input to the first input end and the second input end are matched, the signals output to the switches are the second group of switch control signals;
after determining the second control signal, further comprising: if the second group of switch control signals is not matched with the first group of switch control signals, if an instruction for acquiring the label information is received, the processor at least outputs a signal for marking that the radio frequency chip is illegal, or if the instruction for acquiring the label information is received, the processor at least outputs the first group of switch control signals and the second group of switch control signals through the antenna.
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| JP2007018197A (en) * | 2005-07-06 | 2007-01-25 | Teruya:Kk | Illegal use detection function-equipped rfid tag |
| CN100524349C (en) * | 2007-04-19 | 2009-08-05 | 西安电子科技大学 | Embedded RFID card identification portable device and identification method |
| WO2010016298A1 (en) * | 2008-08-05 | 2010-02-11 | 株式会社村田製作所 | Antenna and wireless communication machine |
| US9874603B2 (en) * | 2014-07-07 | 2018-01-23 | Avery Dennison Retail Information Services, Llc | System and method for capacitive coupling testing |
| CN105913108B (en) * | 2016-04-11 | 2020-12-08 | 四川凯路威科技有限公司 | RFID chip transfer prevention method, transfer prevention RFID chip and circuit |
| KR101885160B1 (en) * | 2016-10-26 | 2018-08-03 | 한국기계연구원 | Snake along controlling device and snake along controlling method using the magnetic bearing |
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