CN109346412A - A kind of manufacturing method and thin film transistor (TFT) of thin film transistor (TFT) - Google Patents
A kind of manufacturing method and thin film transistor (TFT) of thin film transistor (TFT) Download PDFInfo
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- CN109346412A CN109346412A CN201811153108.9A CN201811153108A CN109346412A CN 109346412 A CN109346412 A CN 109346412A CN 201811153108 A CN201811153108 A CN 201811153108A CN 109346412 A CN109346412 A CN 109346412A
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- 239000010409 thin film Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 169
- 238000002161 passivation Methods 0.000 claims abstract description 123
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000008439 repair process Effects 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 171
- 239000000463 material Substances 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000002356 single layer Substances 0.000 description 8
- 239000000126 substance Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052593 corundum Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012163 sequencing technique Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910003087 TiOx Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000002615 epidermis Anatomy 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
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- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses a kind of manufacturing methods of thin film transistor (TFT), the described method comprises the following steps: forming grid；Form the gate insulating layer of covering grid；Semiconductor layer is formed on gate insulating layer；Form the source electrode and drain electrode contacted with semiconductor layer；Passivation layer in semiconductor is formed on the back channel of semiconductor layer, the conductivity of passivation layer is lower than the conductivity of the semiconductor layer in the semiconductor.The present invention is by being changed into insulating property (properties) by semiconductor property by the back channel of semiconductor layer to form passivation layer in semiconductor, it effectively prevent the back channel of semiconductor layer to damage in processing procedure, improve the device property of thin film transistor (TFT), the surface passivation of source electrode and drain electrode is formed to passivation layer in the metal of insulating property (properties) simultaneously, the exposure of source electrode and drain electrode metal surface is avoided, prevents the electric discharge of stored charge bring from wounding.
Description
Technical field
The present invention relates to field of liquid crystal display more particularly to the manufacturing methods and thin film transistor (TFT) of a kind of thin film transistor (TFT).
Background technique
Traditional bottom gate stagger arrangement type TFT generally comprises etching protection type device architecture and back channel-etch type device architecture.
Successively film forming sequence is that grid G E is formed, gate insulating layer GI is formed, semiconductor layer OS is formed, carves etching protection type device architecture
Erosion protective layer ES is formed, source-drain electrode SD is formed, and finally formed thin film transistor (TFT) is as shown in Figure 1.
In order to reduce processing procedure light shield quantity, effect of parasitic capacitance is reduced, back channel-etch type device architecture is developed.Carry on the back ditch
Successively film forming sequence is that grid G E is formed, gate insulating layer GI is formed, semiconductor layer OS is formed, source and drain to road etching type device architecture
Pole SD is formed, and finally formed thin film transistor (TFT) is as shown in Figure 2.
Traditional back channel-etch type TFT device has the disadvantage that:
1. the back channel of semiconductor layer damages seriously in processing procedure, device property is poor, especially for oxide TFT device
Part；
2. source-drain electrode metal surface exposes in the plasma, metal watch face when carrying out traditional back channel reparation
Easy stored charge has that metal surface electric discharge is wounded.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of manufacturing method of thin film transistor (TFT), by forming semiconductor
Passivation layer in interior passivation layer and metal solves back channel damage problem and carries on the back the source drain damage problem of channel reparation.
Technical solution provided by the invention is as follows:
The invention discloses a kind of manufacturing methods of thin film transistor (TFT), the described method comprises the following steps:
Form grid；
Form the upper gate insulating layer for being covered on grid；
Semiconductor layer is formed on gate insulating layer；
Form the source electrode and drain electrode contacted with semiconductor layer；
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, the conductivity of passivation layer is lower than in the semiconductor
The conductivity of the semiconductor layer.
It further, further include step after the step " forming passivation layer in semiconductor on semiconductor layer back channel "
It is rapid:
Passivation layer in metal is formed on the surface of source electrode and drain electrode, the conductivity of passivation layer is lower than the source in the metal
The conductivity of pole and the drain electrode.
It further, further include step before the step " forming passivation layer in semiconductor on the back channel of semiconductor layer "
It is rapid: first time repair process is carried out to the back channel of semiconductor layer；
It further comprises the steps of: after the step " forming passivation layer in metal on source electrode and drain electrode surface " to semiconductor layer
It carries on the back channel and carries out second of repair process.
It further, further include step before the step " forming passivation layer in semiconductor on the back channel of semiconductor layer "
It is rapid:
Passivation layer in metal is formed on the surface of source electrode and drain electrode, the conductivity of passivation layer is lower than the source in the metal
The conductivity of pole and the drain electrode.
Further, the step " passivation layer in semiconductor is formed on the back channel of semiconductor layer " and the step
It is further comprised the steps of: between " forming passivation layer in metal on the surface of source electrode and drain electrode "
Channel repair process is carried out to the back channel of semiconductor layer.
Further, it is further comprised the steps of: before the step " forming passivation layer in metal on the surface of source electrode and drain electrode "
First time repair process is carried out to the back channel of semiconductor layer；
It further comprises the steps of: after the step " forming passivation layer in semiconductor on the back channel of semiconductor layer " and half-and-half leads
The back channel of body layer carries out second of repair process.
Further, the step " passivation layer in semiconductor is formed on the back channel of semiconductor layer " specifically includes step
It is rapid:
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, while channel is carried out to the back channel of semiconductor layer
Repair process.
Further, the step " passivation layer in semiconductor is formed on the back channel of semiconductor layer " specifically includes step
It is rapid:
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, while metal passivation is formed in source electrode and drain electrode
Layer；The conductivity of passivation layer is lower than the conductivity of the semiconductor layer in the semiconductor, the conduction of passivation layer in the metal
Rate is lower than the conductivity of the source electrode and the drain electrode.
Further, the step " form passivation layer in semiconductor on the back channel of semiconductor layer, at the same in source electrode and
Metal passivation layer is formed in drain electrode " before further comprise the steps of: first time repair process carried out to the back channel of semiconductor layer；
The step " forms passivation layer in semiconductor, while the shape in source electrode and drain electrode on the back channel of semiconductor layer
At metal passivation layer " after further comprise the steps of: second of repair process carried out to the back channel of semiconductor layer.
The invention also discloses a kind of thin film transistor (TFT)s, comprising: grid；Cover the gate insulating layer of grid；It is exhausted in grid
Semiconductor layer in edge layer；In the source electrode and drain electrode of the semiconductor layer, the source electrode and the drain electrode are with described half
It is contacted in conductor layer；The passivation layer in the semiconductor on the back channel of semiconductor layer, the conductivity of passivation layer in the semiconductor
Lower than the conductivity of the semiconductor layer.
Compared with prior art, the present invention is by being changed into insulating property (properties) by semiconductor property for the back channel of semiconductor layer
To form passivation layer in semiconductor, it effectively prevent the back channel of semiconductor layer to damage in processing procedure, improves thin film transistor (TFT)
Device property, while the surface passivation of source electrode and drain electrode is formed into passivation layer in the metal of insulating property (properties), avoid source electrode and drain electrode
Metal surface exposure prevents the electric discharge of stored charge bring from wounding.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, the present invention is given furtherly
It is bright.
Fig. 1 is etching protection type device architecture schematic diagram；
Fig. 2 is back channel-etch type device architecture schematic diagram；
Fig. 3 is the definition schematic diagram being passivated in the present invention；
Fig. 4 a- Fig. 4 f is a kind of processing step schematic diagram of the embodiment two of the manufacturing method of thin film transistor (TFT) of the present invention；
Fig. 5 is the definition schematic diagram that the present invention repairs；
Fig. 6 is a kind of structural schematic diagram of one embodiment of thin film transistor (TFT) of the present invention.
Specific embodiment
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, Detailed description of the invention will be compareed below
A specific embodiment of the invention.It should be evident that drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
Embodiment one:
A kind of manufacturing method of thin film transistor (TFT), the described method comprises the following steps:
Form grid 01；
The gate insulating layer 02 of covering grid 01 is formed on grid 01；
Semiconductor layer 03 is formed on gate insulating layer 02；
Form the source electrode 041 contacted with semiconductor layer 03 and drain electrode 042；Specifically, forming half between source electrode and drain electrode
The back channel of conductor layer 03.
Passivation layer 051 in semiconductor is formed on the back channel of semiconductor layer 03, passivation layer 051 leads in the semiconductor
Electric rate is lower than the conductivity of the semiconductor layer 03.Specifically, Fig. 3 show the definition schematic diagram of interior passivation.As shown in figure 3,
Interior passivation refers to the conductive capability that material upper epidermis is reduced using certain process, and forming one layer of conductivity on surface layer reduces
Passivation layer, material can be made by original state passivation to be new state 1, then by passivation be new state 2, for example metal can be made
The surface passivation of material is semiconductor material, then is passivated as insulating materials.
Passivation Treatment includes physical treatment, chemical treatment in the back of the channel of semiconductor layer 03, and physical treatment is mainly logical
Change material component is crossed to adjust material properties, such as atom injection, the remodeling of superficial physical structure etc., chemical treatment is mainly
It is changed into the material of another insulating property (properties), wet chemistry method, atmosphere heatingization for example, by using particular process by chemically reacting
Learn reaction method etc..
The material of semiconductor layer 03 is not limited to conventional InGaZnOm, InGaZnOm, InZnOm in the present embodiment, main special
Property is that the semiconductor layer 03 can be passivated after chemical treatment or physical treatment, i.e. material property is to insulating materials
Transformation.
The present invention carries out interior Passivation Treatment on the back channel of semiconductor layer 03, forms certain thickness on the surface layer of back channel
Semiconductor in passivation layer 051, by the back channel of semiconductor layer 03 by semiconductor property be changed into insulating property (properties) to is formed partly
Passivation layer 051 in conductor effectively prevent the back channel of semiconductor layer 03 to damage in processing procedure, and the device for improving thin film transistor (TFT) is special
Property.
It should be noted that protective layer 06 can also be re-formed on passivation layer 051 in semiconductor, TFT device is carried out
Encapsulation process avoids the influence of ambient atmosphere or material to TFT characteristic.
Embodiment two:
Preferably, above-described embodiment is improved, obtains preferred embodiment two, a kind of manufacturer of thin film transistor (TFT)
Method the described method comprises the following steps:
Grid 01 is formed on the substrate；
The gate insulating layer 02 of covering grid 01 is formed on grid 01；
Semiconductor layer 03 is formed on gate insulating layer 02；
Source electrode 041 and drain electrode 042 are respectively formed on semiconductor layer 03；Source electrode 041 and drain electrode 042 with semiconductor layer 03
Contact；
Passivation layer 051 in semiconductor is formed on the back channel of semiconductor layer 03, passivation layer 051 leads in the semiconductor
Electric rate is lower than the conductivity of the semiconductor layer 03；
Passivation layer 052 in metal is formed on the surface of source electrode 041 and drain electrode 042, the conduction of passivation layer 052 in the metal
Conductivity of the rate lower than the source electrode 041 and the drain electrode 042.
Specifically, Passivation Treatment includes physical treatment, chemical treatment, object in the layer on surface of metal of the drain electrode 042 of source electrode 041
Reason processing mainly adjusts material properties by changing material component, and chemical treatment is mainly changed by chemical reaction another
A kind of material that electric conductivity reduces.
It first is passivated the back channel of semiconductor layer 03 to form passivation layer 051 in semiconductor in the present embodiment, it is then right
The surface of source electrode 041 and drain electrode 042 is passivated to form passivation layer 052 in metal, passes through the table in source electrode 041 and drain electrode 042
Face forms passivation layer 052 in metal, can effectively prevent the charge accumulated of metal surface, and electric discharge is avoided to wound.
It should be noted that protective layer 06 can also be re-formed on passivation layer 052 in metal, TFT device is carried out close
Envelope processing, avoids the influence of ambient atmosphere or material to TFT characteristic.
Fig. 4 a- Fig. 4 f is a kind of processing step schematic diagram of the embodiment two of the manufacturing method of thin film transistor (TFT) of the present invention.
The method specifically includes:
S1, such as Fig. 4 a, the formation of grid 01, can be made of single-layer metal or oxide conducting material, can also be with
It is multiple layer metal or oxide conducting material, such as common are Al/Mo, Ti/Cu, single layer Mo, single layer ITO etc.；
S2, such as Fig. 4 b, the formation of gate insulating layer 02, the material of use is mainly the material of insulating property (properties), can be single layer
Oxide insulating layer, such as SiO2、Al2O3, it can be the insulating materials of multilayer, but for oxide semiconductor thin-film crystalline substance
Body pipe, general upper layer are oxide dielectric material, such as SiNx+SiO2, SiNx+Al2O3Etc.；
S3, such as Fig. 4 c, the formation of semiconductor layer 03, the material with semiconductor property, such as common InGaZnOm, or
InZnO, InGaZnSnO etc.；
S4, such as Fig. 4 d, source electrode 041 and drain electrode 042 are formed, and can be made of single-layer metal or oxide conducting material
Material, is also possible to multiple layer metal or oxide conducting material, such as common are Mo/Al/Mo, Ti/Cu, single layer Mo, single layer ITO
Etc.；
S5, such as Fig. 4 e, the formation of passivation layer 052 in passivation layer 051 and metal in semiconductor, mainly according to selected half
03 material of conductor layer and metal layer material carry out in Passivation Treatment, such as by metal Al surface passivation be Al2O3, the surface Ti is blunt
TiOx is turned to, the oxygen content in InGaZnOm material is changed or the raising of Ga content makes it be changed into insulating property (properties).
S6, such as Fig. 4 f, the formation of protective layer 06, the material of use is mainly the material of insulating property (properties), can be the oxygen of single layer
Compound insulating layer, such as SiO2、Al2O3, it can be the insulating materials of multilayer, but for oxide semiconductor thin-film transistor,
General lower layer is oxide dielectric material, such as SiO2+ SiNx, SiO2+Al2O3Etc..
It should be noted that the invention also includes the other embodiments improved to above-described embodiment, other realities
The sequencing for not limiting that passivation layer 051 is formed with passivation layer 052 in metal in semiconductor in example is applied, semiconductor can be initially formed
Interior passivation layer 051, re-forms passivation layer 052 in metal, can also be formed simultaneously in semiconductor and be passivated in passivation layer 051 and metal
Layer 052.
Embodiment three:
Preferably, above-described embodiment is improved, obtains preferred embodiment three, a kind of manufacturer of thin film transistor (TFT)
Method the described method comprises the following steps:
Grid 01 is formed on the substrate；
The gate insulating layer 02 of covering grid 01 is formed on grid 01；
Semiconductor layer 03 is formed on gate insulating layer 02；
Source electrode 041 and drain electrode 042 are respectively formed on semiconductor layer 03；Source electrode 041 and drain electrode 042 with semiconductor layer 03
Contact；
First time repair process is carried out to the back channel of semiconductor layer 03；
Passivation layer 051 in semiconductor is formed on the back channel of semiconductor layer 03, passivation layer 051 leads in the semiconductor
Electric rate is lower than the conductivity of the semiconductor layer 03；
Passivation layer 052 in metal is formed on the surface of source electrode 041 and drain electrode 042, the conduction of passivation layer 052 in the metal
Conductivity of the rate lower than the source electrode 041 and the drain electrode 042；
Second of repair process is carried out to the back channel of semiconductor layer 03.
Specifically, the present invention also increases additional in order to improve the back channel interface damage of back channel-etch type TFT device
Repair process technique, Fig. 5 are the definition schematic diagram for illustrating to repair, and heretofore described repair process refers to material in processing procedure mistake
It is damaged in journey, then makes material be restored to original state by special process.
List in semiconductor that passivation layer 052 carries out first before being formed in passivation layer 051 and metal in the present embodiment
Secondary repair process, passivation layer 052 carries out second of repair process after being formed again in passivation layer 051 and metal in semiconductor
Situation, it should be noted that for increased repair process, can adjust as required it is successive suitable with interior passivation layer formation
Sequence, the formation of passivation layer 052 can be post-processed first as needed with repair process in passivation layer 051 and metal in semiconductor, can also
To handle simultaneously, the present invention is not especially limited.
Specifically, since the sequencing that passivation layer 052 is formed in passivation layer 051 in semiconductor and metal is not construed as limiting,
And repair process and the sequencing of interior passivation layer formation are also not construed as limiting, and following several possible technique steps are set forth below
It is rapid:
1. being initially formed passivation layer 052 in source electrode 041 and the metal of drain electrode 042, then the repair process of back channel is carried out, it can be with
The electric discharge problem for avoiding metal surface finally carries out passivation in the back channel of semiconductor layer 03 again；
2. being initially formed passivation layer 052 in source electrode 041 and the metal of drain electrode 042, then carries on the back channel and carry out repair process, simultaneously
The back channel of interior passivation semiconductor layer 03 forms passivation layer 051 in semiconductor；
3. be formed simultaneously in source electrode 041 and the metal of drain electrode 042 passivation layer 051 in passivation layer 052 and semiconductor, due to
It is passivated while being provided with repairing effect, it may be unnecessary to additional repair process；
4. the first time repair process of back channel is first carried out, metal surface electric discharge damage does not occur as boundary when processing,
Then source electrode 041 and drain electrode 042 are carried out again (does not limit source electrode 041 and drain electrode herein with passivation in the back channel of semiconductor layer 03
042 with semiconductor layer 03 back channel passivation sequence), finally carry out second of back channel repair process again.
In the present invention it is interior passivation and repair process technique include a variety of different selection schemes, can according to material property into
Row configuration, such as can first be passivated and repair again, or first repair and be passivated again, or be passivated and repair simultaneously.
The invention also discloses a kind of thin film transistor (TFT)s, are manufactured using the manufacturing method of above-mentioned thin film transistor (TFT), and Fig. 6 is this
A kind of structural schematic diagram of one embodiment of thin film transistor (TFT) is invented, as shown in fig. 6, specifically including that
Grid 01；The effect of grid 01 is the grid 01 to form TFT device, is responsible for opening and closing TFT device；
Cover the gate insulating layer 02 of grid 01；Gate insulating layer 02 mainly isolation of semiconductor layer 03 and grid 01, with
Charge inducing is formed in semiconductor layer 03；
Semiconductor layer 03 on gate insulating layer 02；Source electrode 041 and drain electrode 042 on the semiconductor layer 03,
The source electrode 041 and the drain electrode 042 are contacted on the semiconductor layer 03；Semiconductor layer 03 is mainly responsible for connection source electrode
041 and drain electrode 042, pass through semiconductor conduction state control source electrode 041 and drain electrode 042 switch state；
The passivation layer 051 in the semiconductor on the back channel of semiconductor layer 03, the conduction of passivation layer 051 in the semiconductor
Rate is lower than the conductivity of the semiconductor layer 03；That device can be improved is reliable for passivation layer 052 in passivation layer 051 and metal in semiconductor
Property；
Protective layer 06 is mainly sealed processing to film transistor device, avoids ambient atmosphere or material to film
The influence of transistor characteristic.
It should be noted that above-described embodiment can be freely combined as needed.The above is only of the invention preferred
Embodiment, it is noted that for those skilled in the art, in the premise for not departing from the principle of the invention
Under, several improvements and modifications can also be made, these modifications and embellishments should also be considered as the scope of protection of the present invention.
Claims (10)
1. a kind of manufacturing method of thin film transistor (TFT), which is characterized in that the described method comprises the following steps:
Form grid；
Form the gate insulating layer of covering grid；
Semiconductor layer is formed on gate insulating layer；
Form the source electrode and drain electrode contacted with semiconductor layer；
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, the conductivity of passivation layer is lower than described in the semiconductor
The conductivity of semiconductor layer.
2. the manufacturing method of thin film transistor (TFT) as described in claim 1, which is characterized in that the step " is carried on the back in semiconductor layer
Passivation layer in semiconductor is formed on channel " it further comprises the steps of: later
Form passivation layer in metal on the surface of source electrode and drain electrode, in the metal conductivity of passivation layer lower than the source electrode and
The conductivity of the drain electrode.
3. the manufacturing method of thin film transistor (TFT) as claimed in claim 2, which is characterized in that the step is " in semiconductor layer
It is further comprised the steps of: before passivation layer in formation semiconductor on back channel " and first time repair place is carried out to the back channel of semiconductor layer
Reason；
The back ditch to semiconductor layer is further comprised the steps of: after the step " forming passivation layer in metal on source electrode and drain electrode surface "
Road carries out second of repair process.
4. the manufacturing method of thin film transistor (TFT) as described in claim 1, which is characterized in that the step is " in semiconductor layer
Passivation layer in semiconductor is formed on back channel " it further comprises the steps of: before
Form passivation layer in metal on the surface of source electrode and drain electrode, in the metal conductivity of passivation layer lower than the source electrode and
The conductivity of the drain electrode.
5. the manufacturing method of thin film transistor (TFT) as claimed in claim 4, which is characterized in that the step is " in semiconductor layer
Between passivation layer in formation semiconductor on back channel " and the step " forming passivation layer in metal on the surface of source electrode and drain electrode "
It further comprises the steps of:
Channel repair process is carried out to the back channel of semiconductor layer.
6. the manufacturing method of thin film transistor (TFT) as claimed in claim 4, which is characterized in that the step is " in source electrode and drain electrode
Surface form passivation layer in metal " before further comprise the steps of: first time repair process carried out to the back channel of semiconductor layer；
It further comprises the steps of: after the step " forming passivation layer in semiconductor on the back channel of semiconductor layer " to semiconductor layer
Back channel carry out second of repair process.
7. the manufacturing method of thin film transistor (TFT) as claimed in claim 4, which is characterized in that the step is " in semiconductor layer
Passivation layer in semiconductor is formed on back channel " specifically include step:
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, while channel reparation is carried out to the back channel of semiconductor layer
Processing.
8. the manufacturing method of thin film transistor (TFT) as described in claim 1, which is characterized in that the step is " in semiconductor layer
Passivation layer in semiconductor is formed on back channel " specifically include step:
Passivation layer in semiconductor is formed on the back channel of semiconductor layer, while metal passivation layer is formed in source electrode and drain electrode；
The conductivity of passivation layer is lower than the conductivity of the semiconductor layer in the semiconductor, and the conductivity of passivation layer is low in the metal
In the conductivity of the source electrode and the drain electrode.
9. the manufacturing method of thin film transistor (TFT) as claimed in claim 8, which is characterized in that the step is " in semiconductor layer
Carry on the back and form passivation layer in semiconductor on channel, while forming metal passivation layer in source electrode and drain electrode " before further comprise the steps of: pair
The back channel of semiconductor layer carries out first time repair process；
The step " forms passivation layer in semiconductor on the back channel of semiconductor layer, while forming gold in source electrode and drain electrode
It is further comprised the steps of: after category passivation layer " and second of repair process is carried out to the back channel of semiconductor layer.
10. a kind of thin film transistor (TFT) characterized by comprising
Grid；
Cover the gate insulating layer of grid；
Semiconductor layer on gate insulating layer；
In the source electrode and drain electrode of the semiconductor layer, the source electrode and the drain electrode are contacted on the semiconductor layer；
The passivation layer in the semiconductor on the back channel of semiconductor layer, the conductivity of passivation layer is lower than described half in the semiconductor
The conductivity of conductor layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111599868A (en) * | 2020-05-22 | 2020-08-28 | Tcl华星光电技术有限公司 | Thin film transistor preparation method and thin film transistor |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101794819A (en) * | 2009-01-12 | 2010-08-04 | 三星移动显示器株式会社 | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor |
| CN101809747A (en) * | 2007-09-28 | 2010-08-18 | 佳能株式会社 | Thin film transistor, manufacturing method therefor, and display apparatus using the same |
| CN102646699A (en) * | 2012-01-13 | 2012-08-22 | 京东方科技集团股份有限公司 | Oxide TFT (thin film transistor) and manufacturing method thereof |
| US20130005081A1 (en) * | 2011-06-30 | 2013-01-03 | Applied Materials, Inc. | METHOD OF IGZO AND ZNO TFT FABRICATION WITH PECVD SiO2 PASSIVATION |
| CN104157693A (en) * | 2013-05-14 | 2014-11-19 | 乐金显示有限公司 | Oxide thin film transistor and method of fabricating the same |
| CN104241392A (en) * | 2014-07-14 | 2014-12-24 | 京东方科技集团股份有限公司 | Thin-film transistor, preparation method of thin-film transistor, display substrate and display device |
| CN106373998A (en) * | 2016-11-02 | 2017-02-01 | 北京大学深圳研究生院 | Fabrication method of metal oxide thin film transistor |
| CN107369716A (en) * | 2017-07-17 | 2017-11-21 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method, display device |
| CN107658345A (en) * | 2017-09-22 | 2018-02-02 | 京东方科技集团股份有限公司 | Oxide thin film transistor and preparation method thereof, array base palte and display device |
-
2018
- 2018-09-30 CN CN201811153108.9A patent/CN109346412B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101809747A (en) * | 2007-09-28 | 2010-08-18 | 佳能株式会社 | Thin film transistor, manufacturing method therefor, and display apparatus using the same |
| CN101794819A (en) * | 2009-01-12 | 2010-08-04 | 三星移动显示器株式会社 | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor |
| US20130005081A1 (en) * | 2011-06-30 | 2013-01-03 | Applied Materials, Inc. | METHOD OF IGZO AND ZNO TFT FABRICATION WITH PECVD SiO2 PASSIVATION |
| CN102646699A (en) * | 2012-01-13 | 2012-08-22 | 京东方科技集团股份有限公司 | Oxide TFT (thin film transistor) and manufacturing method thereof |
| CN104157693A (en) * | 2013-05-14 | 2014-11-19 | 乐金显示有限公司 | Oxide thin film transistor and method of fabricating the same |
| CN104241392A (en) * | 2014-07-14 | 2014-12-24 | 京东方科技集团股份有限公司 | Thin-film transistor, preparation method of thin-film transistor, display substrate and display device |
| CN106373998A (en) * | 2016-11-02 | 2017-02-01 | 北京大学深圳研究生院 | Fabrication method of metal oxide thin film transistor |
| CN107369716A (en) * | 2017-07-17 | 2017-11-21 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method, display device |
| CN107658345A (en) * | 2017-09-22 | 2018-02-02 | 京东方科技集团股份有限公司 | Oxide thin film transistor and preparation method thereof, array base palte and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599868A (en) * | 2020-05-22 | 2020-08-28 | Tcl华星光电技术有限公司 | Thin film transistor preparation method and thin film transistor |
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