CN109345998A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN109345998A CN109345998A CN201811562298.XA CN201811562298A CN109345998A CN 109345998 A CN109345998 A CN 109345998A CN 201811562298 A CN201811562298 A CN 201811562298A CN 109345998 A CN109345998 A CN 109345998A
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- 230000000087 stabilizing effect Effects 0.000 claims abstract description 14
- 238000012423 maintenance Methods 0.000 claims description 28
- 238000004891 communication Methods 0.000 claims description 21
- 239000013078 crystal Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 235000008434 ginseng Nutrition 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 210000003739 neck Anatomy 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
GOA circuit and display panel provided by the embodiments of the present application, by increasing by a Voltage stabilizing module, under the premise of not increasing additional cabling, when the current potential of reference low level signal is changed due to parasitic capacitance, according to the current potential of the first low-frequency clock signal and the second low-frequency clock signal adjustment reference low level signal, the reference low-potential signal made is more stable, and then improves the stability of GOA circuit.
Description
Technical field
This application involves field of display technology, and in particular to a kind of GOA circuit and display panel.
Background technique
GOA (full name in English: Gate Driver on Array, Chinese name: integrated gate drive circuitry) technology is by grid
Pole driving circuit is integrated in the array substrate of display panel, so as to save grid-driving integrated circuit part, with from material
Product cost is reduced in terms of material cost and manufacture craft two.Coupling or electric leakage of the existing GOA circuit due to parasitic capacitance
The influence of stream easily causes GOA circuit unstable.
Summary of the invention
The embodiment of the present application is designed to provide a kind of GOA circuit and display panel, can be improved the stabilization of GOA circuit
Property.
The embodiment of the present application provides a kind of GOA circuit, comprising: the GOA unit of multi-stage cascade, every level-one GOA unit are wrapped
It includes: pull-up control module, lower transmission module, pull-up module, pull-down module, drop-down maintenance module, Voltage stabilizing module and bootstrap capacitor；
The pull-up control module access upper level grade communication number and upper level scanning signal, and it is electrically connected at first
Node, for exporting the upper level scanning signal to the first node under the control of the upper level grade communication number；
The lower transmission module accesses high frequency clock signal, and is electrically connected at the first node, for described first
The same level grade communication number is exported under the control of Electric potentials of node；
The pull-up module accesses the high frequency clock signal, and is electrically connected at the first node, for described
The same level scanning signal is exported under the control of Electric potentials of first node；
The pull-down module access next stage scanning signal and reference low level signal, and it is electrically connected at described first
Node and the same level scanning signal, for being pulled down according to the next stage scanning signal and the reference low level signal
The current potential of the current potential of the first node and the same level scanning signal；
The drop-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal and the low electricity of the reference
Ordinary mail number, and it is electrically connected at the first node and the same level scanning signal, for pulling down institute in the pull-down module
It states the current potential of the first node and described the same level after the current potential of first node and the current potential of the same level scanning signal
The current potential of scanning signal maintains the current potential of the reference low level signal；
The Voltage stabilizing module accesses first low-frequency clock signal and second low-frequency clock signal, and electrically connects
It is connected to the reference low level signal, it is low according to described first for when the current potential of the reference low level signal is elevated
Frequency clock signal and second low-frequency clock signal drag down the current potential of the reference low level signal；
One end of the bootstrap capacitor is electrically connected at the first node, and the other end of the bootstrap capacitor is electrically connected
In the same level scanning signal.
In GOA circuit described herein, the pull-up control module includes: the first transistor；
The grid of the first transistor is electrically connected at the upper level grade communication number, the source electrode of the first transistor
It is electrically connected at the upper level scanning signal, the drain electrode of the first transistor is electrically connected at the first node.
In GOA circuit described herein, the lower transmission module includes: second transistor；
The grid of the second transistor is electrically connected at the first node, and the source electrode of the second transistor electrically connects
It is connected to the high frequency clock signal, the drain electrode of the third transistor is electrically connected at the same level grade communication number.
In GOA circuit described herein, the pull-up module includes: third transistor；
The grid of the third transistor is electrically connected at the first node, and the source electrode of the third transistor electrically connects
It is connected to the high frequency clock signal, the drain electrode of the third transistor is electrically connected at the same level scanning signal.
In GOA circuit described herein, the pull-down module includes: the 4th transistor and the 5th transistor；
The grid of 4th transistor and the grid of the 5th transistor are electrically connected at the next stage and sweep
Retouch signal；The source electrode of 4th transistor and the source electrode of the 5th transistor are electrically connected at the reference low level
Signal；The drain electrode of 4th transistor is electrically connected at the first node and is electrically connected, the drain electrode of the 5th transistor
It is electrically connected at the same level scanning signal.
In GOA circuit described herein, the drop-down maintenance module includes under the first drop-down maintenance unit and second
Draw maintenance unit, the first drop-down maintenance unit and the second drop-down maintenance unit drag down described the in the pull-down module
After the current potential of one node and the current potential of the same level scanning signal, the current potential and described the same level scanning letter of the first node are maintained
Number current potential.
In GOA circuit described herein, the first drop-down maintenance unit includes: the 6th transistor, the 7th crystal
Pipe, the 8th transistor, the 9th transistor, the tenth transistor, the 11st transistor；
The source electrode of the grid of 6th transistor, source electrode and the 7th transistor is electrically connected at described first
Low-frequency clock signal；The drain electrode of 6th transistor, the leakage of the grid and the 8th transistor of the 7th transistor
Pole is electrically connected；The drain electrode of 7th transistor, the drain electrode of the 9th transistor, the grid of the tenth transistor and
The grid of 11st transistor is electrically connected；The grid of the grid and the 9th transistor of 8th transistor is electric
Property is connected to the first node；Source electrode, the tenth transistor of the source electrode of 8th transistor, the 9th transistor
Source electrode and the source electrode of the 11st transistor be electrically connected at the reference low level signal；Tenth transistor
Drain electrode be electrically connected at the same level scanning signal；The drain electrode of 11st transistor is electrically connected at the first segment
Point；
The second drop-down maintenance unit includes: the tenth two-transistor, the 13rd transistor, the 14th transistor, the tenth
Five transistors, the 16th transistor, the 17th transistor；
The source electrode of the grid of tenth two-transistor, source electrode and the 13rd transistor is electrically connected at described
Second low-frequency clock signal；The drain electrode of tenth two-transistor, the 13rd transistor grid and the described 14th
The drain electrode of transistor is electrically connected；The drain electrode of 13rd transistor, the drain electrode of the 15th transistor, the described 16th
The grid of the grid of transistor and the 17th transistor is electrically connected；The grid of 14th transistor and described the
The grid of 15 transistors is electrically connected at the first node；The source electrode of 14th transistor, the 15th crystalline substance
The source electrode of the source electrode of body pipe, the source electrode of the 16th transistor and the 17th transistor is electrically connected at the ginseng
Examine low level signal；The drain electrode of 16th transistor is electrically connected at the same level scanning signal；17th crystal
The drain electrode of pipe is electrically connected at the first node.
In GOA circuit described herein, the Voltage stabilizing module includes: the 18th transistor and the 19th crystal
Pipe；
The grid of 18th transistor is electrically connected at first low-frequency clock signal, the 18th transistor
Source electrode be electrically connected at second low-frequency clock signal, the grid of the 19th transistor is electrically connected at described second
Low-frequency clock signal, the source electrode of the 19th transistor are electrically connected at first low-frequency clock signal, and the described 18th
The drain electrode of transistor and the drain electrode of the 19th transistor are electrically connected at the reference low level signal.
It is described when first low-frequency clock signal carries out low and high level conversion in GOA circuit described herein
Second low-frequency clock signal is low level；When second low-frequency clock signal carries out low and high level conversion, described first is low
Frequency clock signal is low level；
And it removes first low-frequency clock signal and carries out low and high level conversion and second low-frequency clock signal progress
The polarity of the time of low and high level conversion, first low-frequency clock signal and second low-frequency clock signal is opposite.
The embodiment of the present application also provides a kind of display panel, including above-described GOA circuit.
GOA circuit and display panel provided by the embodiments of the present application are additionally walked by increasing by a Voltage stabilizing module not increasing
Under the premise of line, when the current potential of reference low level signal is changed due to parasitic capacitance, believed according to the first low-frequency clock
Number and the second low-frequency clock signal adjustment reference low level signal current potential, the reference low-potential signal made is more stable, in turn
Improve the stability of GOA circuit.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the structural schematic diagram of GOA circuit provided by the embodiments of the present application.
Fig. 2 is the structural schematic diagram of a GOA unit in GOA circuit provided by the embodiments of the present application.
Fig. 3 is the circuit diagram of a GOA unit in GOA circuit provided by the embodiments of the present application.
Fig. 4 is the signal timing diagram of a GOA unit in GOA circuit provided by the embodiments of the present application.
Fig. 5 is the structural schematic diagram of display panel provided by the embodiments of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description.Obviously, described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall in the protection scope of this application.
All transistors used in the examples of the application can be thin film transistor (TFT) or field-effect tube or other characteristic phases
Same device, since the source electrode of the transistor used here, drain electrode are symmetrical, so its source electrode, drain electrode can be interchanged.
In the embodiment of the present application, to distinguish the two poles of the earth of transistor in addition to grid, wherein source electrode will be known as in a pole, another pole is known as leaking
Pole.Intermediate ends by the form prescribed switch transistor in attached drawing are grid, signal input part is drain electrode, output end is source electrode.
Furthermore transistor used by the embodiment of the present application may include P-type transistor and/or two kinds of N-type transistor, wherein p-type is brilliant
Body pipe is connected when grid is low level, ends when grid is high level, and N-type transistor is to lead when grid is high level
It is logical, end when grid is low level.
Referring to Fig. 1, Fig. 1 is the structural schematic diagram of GOA circuit provided by the embodiments of the present application.As shown in Figure 1, the application
The GOA circuit that embodiment provides includes the GOA unit of multi-stage cascade.Fig. 1 is mono- with cascade N-1 grades of GOA units, N grades of GOA
For member and N+1 grades of GOA units.
When N grades of GOA units work, the scanning signal of N grades of GOA units output is high potential, is used to open display
In panel in a line each pixel transistor switch, and the pixel electrode in each pixel is filled by data-signal
Electricity；N grades of grade communications number are used to control the work of N+1 grades of GOA units；When N+1 grades of GOA units work, N+1 grades
The scanning signal of GOA unit output is high potential, while the scanning signal of N grades of GOA units output is low potential.
Referring to Fig. 2, Fig. 2 is the structural schematic diagram of a GOA unit in GOA circuit provided by the embodiments of the present application.As schemed,
Shown in 2, which includes: pull-up control module 101, lower transmission module 102, pull-up module 103, pull-down module 104, drop-down
Maintenance module 105, Voltage stabilizing module 106 and bootstrap capacitor Cbt.
Wherein, pull-up control module 101 accesses upper level grade communication ST (N-1) and upper level scanning signal G (N-
1) it, and is electrically connected at first node Q (N), believes for scanning upper level under the control of upper level grade communication ST (N-1)
Number G (N-1) output is to first node Q (N).
Wherein, lower transmission module 102 accesses high frequency clock signal CK, and is electrically connected at first node Q (N), for the
The same level grade communication ST (N) is exported under the control of Electric potentials of one node Q (N).
Wherein, pull-up module 103 accesses high frequency clock signal CK, and is electrically connected at first node Q (N), for the
The same level scanning signal G (N) is exported under the control of Electric potentials of one node Q (N).
Wherein, pull-down module 104 accesses next stage scanning signal G (N+1) and reference low level signal VSS, and electrically
It is connected to first node Q (N) and the same level scanning signal G (N), for according to next stage scanning signal G (N+1) and with reference to low
Level signal VSS pulls down the current potential of first node Q (N) and the current potential of the same level scanning signal G (N).
Wherein, drop-down maintenance module 105 accesses the first low-frequency clock signal LC1, the second low-frequency clock signal LC2 and ginseng
Low level signal VSS is examined, and is electrically connected at first node Q (N) and the same level scanning signal G (N), in pull-down module
After the current potential of 104 drop-downs first node Q (N) and the current potential of the same level scanning signal G (N) by the current potential of first node Q (N) and
The current potential of the same level scanning signal G (N) maintains the current potential of reference low level signal VSS.
Wherein, Voltage stabilizing module 106 accesses the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2, and electrically
It is connected to reference low level signal VSS, for when the current potential of reference low level signal VSS is elevated, when according to the first low frequency
Clock signal LC1 and the second low-frequency clock signal LC2 drag down the current potential of reference low level signal VSS.
Wherein, one end of bootstrap capacitor Cbt is electrically connected at first node Q (N), and the other end of bootstrap capacitor Cbt is electrical
It is connected to the same level scanning signal G (N).
It should be noted that GOA circuit provided by the embodiments of the present application is not increasing volume by increasing Voltage stabilizing module 106
Under the premise of outer cabling, when the current potential of reference low level signal VSS is changed due to parasitic capacitance, according to the first low frequency
The current potential of clock signal LC1 and the second low-frequency clock signal LC2 adjustment reference low level signal VSS, the reference low potential letter made
It is number more stable, and then improve the stability of GOA circuit.
Referring to Fig. 3, Fig. 3 is the circuit diagram of a GOA unit in GOA circuit provided by the embodiments of the present application.Such as Fig. 3
Shown, pull-up control module 101 includes: the first transistor T1；The grid of the first transistor T1 is electrically connected at upper level grade biography
Signal ST (N-1), the source electrode of the first transistor T1 are electrically connected at upper level scanning signal G (N-1), the leakage of the first transistor T1
Pole is electrically connected at the first node Q (N).
Lower transmission module 102 includes: second transistor T2；The grid of second transistor T2 is electrically connected at first node Q
(N), the source electrode of second transistor T2 is electrically connected at high frequency clock signal CK, and the drain electrode of third transistor T3 is electrically connected at this
Grade grade communication ST (N).
Pull-up module 103 includes: third transistor T3；The grid of third transistor T3 is electrically connected at first node Q
(N), the source electrode of third transistor T3 is electrically connected at high frequency clock signal CK, and the drain electrode of third transistor T3 is electrically connected at this
Grade scanning signal G (N).
Pull-down module 104 includes: the 4th transistor T4 and the 5th transistor T5；The grid and the 5th of 4th transistor T4
The grid of transistor T5 is electrically connected at next stage scanning signal G (N+1)；The source electrode and the 5th crystal of 4th transistor T4
The source electrode of pipe T5 is electrically connected at reference low level signal VSS；The drain electrode of 4th transistor T4 is electrically connected at first node Q
(N) it is electrically connected, the drain electrode of the 5th transistor T5 is electrically connected at the same level scanning signal G (N).
Pulling down maintenance module 105 includes the first drop-down maintenance unit 1051 and the second drop-down maintenance unit 1052, under first
Maintenance unit 1051 and the second drop-down maintenance unit 1052 is drawn to drag down the current potential and the same level of first node Q (N) in pull-down module 104
After the current potential of scanning signal G (N), the current potential of first node Q (N) and the current potential of the same level scanning signal G (N) are maintained.
First drop-down maintenance unit 1051 includes: the 6th transistor T6, the 7th transistor T7, the 8th transistor T8, the 9th
Transistor T9, the tenth transistor T10, the 11st transistor T11；Grid, source electrode and the 7th transistor of 6th transistor T6
The source electrode of T7 is electrically connected at the first low-frequency clock signal LC1；The drain electrode of 6th transistor T6, the 7th transistor T7 grid
And the 8th transistor T8 drain electrode be electrically connected；Drain electrode, the drain electrode of the 9th transistor T9, the tenth crystal of 7th transistor T7
The grid of the grid of pipe T10 and the 11st transistor T11 are electrically connected；The grid and the 9th transistor T9 of 8th transistor T8
Grid be electrically connected at first node Q (N)；Source electrode, the tenth crystal of the source electrode of 8th transistor T8, the 9th transistor T9
The source electrode of the source electrode of pipe T10 and the 11st transistor T11 are electrically connected at reference low level signal VSS；Tenth transistor
The drain electrode of T10 is electrically connected at the same level scanning signal G (N)；The drain electrode of 11st transistor T11 is electrically connected at first node Q
(N)。
Second drop-down maintenance unit 1052 includes: the tenth two-transistor T12, the 13rd transistor T13, the 14th transistor
T14, the 15th transistor T15, the 16th transistor T16, the 17th transistor T17；The grid of tenth two-transistor T12, source
The source electrode of pole and the 13rd transistor T13 are electrically connected at the second low-frequency clock signal LC2；Tenth two-transistor T12's
The drain electrode of drain electrode, the grid of the 13rd transistor T13 and the 14th transistor T14 is electrically connected；13rd transistor T13's
Drain electrode, the drain electrode of the 15th transistor T15, the grid of the grid of the 16th transistor T16 and the 17th transistor T17 are electrical
Connection；The grid of 14th transistor T14 and the grid of the 15th transistor T15 are electrically connected at first node Q (N)；The
The source electrode of 14 transistor T14, the source electrode of the 15th transistor T15, the 16th transistor T16 source electrode and the 17th crystal
The source electrode of pipe T17 is electrically connected at reference low level signal VSS；The drain electrode of 16th transistor T16 is electrically connected at the same level
Scanning signal G (N)；The drain electrode of 17th transistor T17 is electrically connected at first node Q (N).
Voltage stabilizing module 106 includes: the 18th transistor T18 and the 19th transistor T19；18th transistor T18's
Grid is electrically connected at the first low-frequency clock signal LC1, and the source electrode of the 18th transistor T18 is electrically connected at the second low-frequency clock
Signal LC2, the grid of the 19th transistor T19 are electrically connected at the second low-frequency clock signal LC2, the 19th transistor T19's
Source electrode is electrically connected at drain electrode and the 19th transistor T19 of first the low-frequency clock signal LC1, the 18th transistor T18
Drain electrode is electrically connected at reference low level signal VSS.
Specifically, referring to Fig. 4, Fig. 4 is the signal sequence of a GOA unit in GOA circuit provided by the embodiments of the present application
Figure.Wherein, when the first low-frequency clock signal LC1 carries out low and high level conversion, the second low-frequency clock signal LC2 is low level；
When second low-frequency clock signal LC2 carries out low and high level conversion, the first low-frequency clock signal LC1 is low level；And remove first
Low-frequency clock signal LC1 carries out low and high level conversion and the second low-frequency clock signal LC2 is carried out the time of low and high level conversion, the
The polarity of one low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite.
In the first clock cycle, upper level grade communication ST (N-1) is high potential, and the first transistor T1 is opened, due to
The upper level scanning signal G (N-1) of the source electrode input of the first transistor T1 is high potential at this time, so that the electricity of first node Q (N)
Position is elevated, and second transistor T2 and third transistor T3 are opened；At this time since high frequency clock signal CK is low potential, this
Grade grade communication ST (N) and the same level scanning signal G (N) is low potential.
In the second clock period, upper level grade communication ST (N-1) is low potential, and the first transistor T1 is closed, first segment
The current potential of point Q (N) continues to remain high potential, and second transistor T2 and third transistor T3 are still opened.High frequency clock at this time
Signal CK is high potential, and therefore, the same level grade communication ST (N) and the same level scanning signal G (N) are high potential.At this stage, originally
Grade scanning signal G (N) is high potential, so that the corresponding scan line of the same level GOA unit is electrically charged, it is corresponding to open the same level scan line
One-row pixels, the row pixel are lit.
Meanwhile in this stage, since the same level scanning signal G (N) is high potential, under the action of bootstrap capacitor Cbt, by the
The current potential of one node Q (N) is further raised, and guarantees the opening and the same level grade communication of second transistor T2 and third transistor T3
Number ST (N) and the same level scanning signal G (N) is high potential signal.
In the third clock cycle, high frequency clock signal CK is low potential, the same level grade communication ST (N) and the same level scanning signal
G (N) is low-potential signal.
In addition, in this stage, since next stage scanning signal G (N+1) is high potential signal so that the 4th transistor T4 and
5th transistor T5 is opened, and is directly connected to first node Q (N) and the same level scanning signal G (N) with reference low level signal VSS,
The current potential of first node Q (N) and the same level scanning signal G (N) are pulled low to the current potential of reference low level signal VSS.
Since the current potential of first node Q (N) is pulled low, the 8th transistor T8 and the 9th transistor T9 are closed.At this point, first
Low-frequency clock signal LC1 is high potential, and the 5th transistor T5 and the 6th transistor T6 are opened, the tenth transistor T10 and the 11st
Transistor T11 is opened, and is further connected to first node Q (N) and the same level scanning signal G (N) with reference low level signal VSS,
To maintain first node Q (N) and the same level scanning signal G (N) in the current potential of reference low level signal VSS.
Certainly, if the second low-frequency clock signal LC2 is high potential, the first low-frequency clock signal LC1 is low potential, then uses
Second pulls down maintenance unit 1052 to maintain first node Q (N) and the same level scanning signal G (N) reference low level signal VSS's
Current potential, working principle is similar with the first drop-down maintenance unit 1051, and which is not described herein again.
In the embodiment of the present application, first node Q (N) passes through the 5th transistor T5 or the 11st transistor T11 and reference
Low level signal VSS connection, the same level scanning signal G (N) pass through the 6th transistor T6 or the tenth transistor T10 and reference low level
Signal VSS connection.When coupling due to parasitic capacitance of first node Q (N) or the same level scanning signal G (N) or leakage current
When influencing to occur potential change, they can pass through the 5th transistor T5, the 6th transistor T6, the tenth transistor T10 or the 11st
Transistor T11 discharges charge to reference low level signal VSS, and the current potential of reference low level signal VSS may be elevated, in turn
Influence the stability of GOA circuit.When the first low-frequency clock signal LC1 is high potential, the second low-frequency clock signal LC2 is low potential
When, the 18th transistor T18 is opened, and the 19th transistor T19 is closed, at this time reference low level signal VSS and when the second low frequency
The LC2 connection of clock signal, the second low-frequency clock signal LC2 can play the role of assisting pressure stabilizing.Similarly, when the second low-frequency clock is believed
When number LC2 is high potential, the first low-frequency clock signal LC1 is low potential, the 19th transistor T19 is opened, the 18th transistor
T18 is closed, and reference low level signal VSS is connect with the first low-frequency clock signal LC1 at this time, and the first low-frequency clock signal LC1 can
To play the role of assisting pressure stabilizing.
Referring to Fig. 5, Fig. 5 is the structural schematic diagram of display panel provided by the embodiments of the present application.As shown in figure 5, this is aobvious
Show that panel includes display area and the GOA circuit 200 being integrally disposed on the frontside edge of display area；Wherein, the GOA circuit
200 is similar with the structure of above-mentioned GOA circuit and principle, and which is not described herein again.
The above is only the embodiment of the present invention, are not intended to limit the scope of the invention, all to be said using the present invention
Equivalent structure or equivalent flow shift made by bright book and accompanying drawing content is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (10)
1. a kind of GOA circuit characterized by comprising the GOA unit of multi-stage cascade, every level-one GOA unit include: pull-up
Control module, lower transmission module, pull-up module, pull-down module, drop-down maintenance module, Voltage stabilizing module and bootstrap capacitor；
The pull-up control module access upper level grade communication number and upper level scanning signal, and it is electrically connected at first segment
Point, for exporting the upper level scanning signal to the first node under the control of the upper level grade communication number；
The lower transmission module accesses high frequency clock signal, and is electrically connected at the first node, in the first node
Control of Electric potentials under export the same level grade communication number；
The pull-up module accesses the high frequency clock signal, and is electrically connected at the first node, for described first
The same level scanning signal is exported under the control of Electric potentials of node；
The pull-down module access next stage scanning signal and reference low level signal, and it is electrically connected at the first node
And the same level scanning signal, for according to the next stage scanning signal and reference low level signal drop-down
The current potential of the current potential of first node and the same level scanning signal；
The drop-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal and reference low level letter
Number, and it is electrically connected at the first node and the same level scanning signal, in pull-down module drop-down described the
The current potential of the first node and described the same level are scanned after the current potential of one node and the current potential of the same level scanning signal
The current potential of signal maintains the current potential of the reference low level signal；
The Voltage stabilizing module accesses first low-frequency clock signal and second low-frequency clock signal, and is electrically connected at
The reference low level signal, for when the current potential of the reference low level signal is elevated, when according to first low frequency
Clock signal and second low-frequency clock signal drag down the current potential of the reference low level signal；
One end of the bootstrap capacitor is electrically connected at the first node, and the other end of the bootstrap capacitor is electrically connected at institute
State the same level scanning signal.
2. GOA circuit according to claim 1, which is characterized in that the pull-up control module includes: the first transistor；
The grid of the first transistor is electrically connected at the upper level grade communication number, and the source electrode of the first transistor is electrical
It is connected to the upper level scanning signal, the drain electrode of the first transistor is electrically connected at the first node.
3. GOA circuit according to claim 1, which is characterized in that the lower transmission module includes: second transistor；
The grid of the second transistor is electrically connected at the first node, and the source electrode of the second transistor is electrically connected at
The high frequency clock signal, the drain electrode of the third transistor are electrically connected at the same level grade communication number.
4. GOA circuit according to claim 1, which is characterized in that the pull-up module includes: third transistor；
The grid of the third transistor is electrically connected at the first node, and the source electrode of the third transistor is electrically connected at
The high frequency clock signal, the drain electrode of the third transistor are electrically connected at the same level scanning signal.
5. GOA circuit according to claim 1, which is characterized in that the pull-down module includes: the 4th transistor and the 5th
Transistor；
The grid of 4th transistor and the grid of the 5th transistor are electrically connected at the next stage scanning letter
Number；The source electrode of 4th transistor and the source electrode of the 5th transistor are electrically connected at the reference low level letter
Number；The drain electrode of 4th transistor is electrically connected at the first node and is electrically connected, the drain electrode electricity of the 5th transistor
Property is connected to the same level scanning signal.
6. GOA circuit according to claim 1, which is characterized in that the drop-down maintenance module includes that the first drop-down maintains
Unit and the second drop-down maintenance unit, the first drop-down maintenance unit and the second drop-down maintenance unit are in the lower drawing-die
After block drags down the current potential of the first node and the current potential of the same level scanning signal, current potential and the institute of the first node are maintained
State the current potential of the same level scanning signal.
7. GOA circuit according to claim 6, which is characterized in that the first drop-down maintenance unit includes: the 6th crystal
Pipe, the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 11st transistor；
The source electrode of the grid of 6th transistor, source electrode and the 7th transistor is electrically connected at first low frequency
Clock signal；The drain electrode electricity of the drain electrode of 6th transistor, the grid of the 7th transistor and the 8th transistor
Property connection；The drain electrode of 7th transistor, the drain electrode of the 9th transistor, the grid of the tenth transistor and described
The grid of 11st transistor is electrically connected；The grid of the grid and the 9th transistor of 8th transistor electrically connects
It is connected to the first node；The source of the source electrode of 8th transistor, the source electrode of the 9th transistor, the tenth transistor
The source electrode of pole and the 11st transistor is electrically connected at the reference low level signal；The leakage of tenth transistor
Pole is electrically connected at the same level scanning signal；The drain electrode of 11st transistor is electrically connected at the first node；
The second drop-down maintenance unit includes: the tenth two-transistor, the 13rd transistor, the 14th transistor, the 15th crystalline substance
Body pipe, the 16th transistor, the 17th transistor；
The source electrode of the grid of tenth two-transistor, source electrode and the 13rd transistor is electrically connected at described second
Low-frequency clock signal；The drain electrode of tenth two-transistor, the 13rd transistor grid and the 14th crystal
The drain electrode of pipe is electrically connected；Drain electrode, the drain electrode of the 15th transistor, the 16th crystal of 13rd transistor
The grid of the grid of pipe and the 17th transistor is electrically connected；The grid and the described 15th of 14th transistor
The grid of transistor is electrically connected at the first node；Source electrode, the 15th transistor of 14th transistor
Source electrode, the source electrode of the 16th transistor and the source electrode of the 17th transistor be electrically connected at it is described with reference to low
Level signal；The drain electrode of 16th transistor is electrically connected at the same level scanning signal；17th transistor
Drain electrode is electrically connected at the first node.
8. GOA circuit according to claim 1, which is characterized in that the Voltage stabilizing module include: the 18th transistor and
19th transistor；
The grid of 18th transistor is electrically connected at first low-frequency clock signal, the source of the 18th transistor
Pole is electrically connected at second low-frequency clock signal, and the grid of the 19th transistor is electrically connected at second low frequency
Clock signal, the source electrode of the 19th transistor are electrically connected at first low-frequency clock signal, the 18th crystal
The drain electrode of pipe and the drain electrode of the 19th transistor are electrically connected at the reference low level signal.
9. any one of -8 GOA circuit according to claim 1, which is characterized in that carried out in first low-frequency clock signal
When low and high level is converted, second low-frequency clock signal is low level；Height electricity is carried out in second low-frequency clock signal
When flat turn is changed, first low-frequency clock signal is low level；
And it removes first low-frequency clock signal and carries out low and high level conversion and second low-frequency clock signal progress height
The polarity of the time of level conversion, first low-frequency clock signal and second low-frequency clock signal is opposite.
10. a kind of display panel, which is characterized in that including the described in any item GOA circuits of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811562298.XA CN109345998B (en) | 2018-12-20 | 2018-12-20 | GOA circuit and display panel |
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| CN201811562298.XA CN109345998B (en) | 2018-12-20 | 2018-12-20 | GOA circuit and display panel |
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| CN109345998B CN109345998B (en) | 2021-09-03 |
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| CN110890077A (en) * | 2019-11-26 | 2020-03-17 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and liquid crystal display panel |
| CN114842786A (en) * | 2022-04-26 | 2022-08-02 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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| CN109345998B (en) | 2021-09-03 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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