CN109344097A - Data transmission method and device - Google Patents
Data transmission method and device Download PDFInfo
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- CN109344097A CN109344097A CN201811068363.3A CN201811068363A CN109344097A CN 109344097 A CN109344097 A CN 109344097A CN 201811068363 A CN201811068363 A CN 201811068363A CN 109344097 A CN109344097 A CN 109344097A
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- fpga
- memory
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- storage control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The application provides a kind of data transmission method and device, method is applied to storage control, and storage control is equipped with FPGA, and the FPGA in FPGA and opposite end storage control is interconnected by XAUI, method includes: to obtain to lower brush data, the first memory will be written to lower brush data；Pass through FPGA, with dma mode read in first memory to lower brush data, and reading is sent to by the XAUI to the FPGA in the storage control of opposite end to lower brush data, without realizing the data transmission between two storage controls by CPU control, since FPGA is served only for carrying out data transmission, the data transmission efficiency between two storage controls can be improved.Again since the FPGA in two storage controls is the data transmission realized by XAUI, and XAUI has the data transmission feature of high bandwidth, low delay, therefore can be further improved the data transmission efficiency between two storage controls.
Description
Technical field
This application involves field of communication technology more particularly to a kind of data transmission methods and device.
Background technique
Current dual control storage system generally comprise application server, two be completely independent and identical storage control,
Disk chassis.Wherein, application server is separately connected by SAN (Storage Area Network, storage area network) network
Be connected to the rear end of two storage controls, storage control by Switching Module with disk chassis, two storage controls it
Between (including data communication and control communicate) is communicated by interconnected bus.In order to guarantee the property of dual control storage system
Can, when needing to carry out data interaction between two storage controls, need interconnection that there is high bandwidth, the data of low delay
Transmittability.
However, since the CPU of storage control is while control interconnection carries out data transmission, it is also necessary to execute it
His task, such as task schedule, heartbeat detection, the tasks such as access for handling application server, to not can guarantee two storages
Data transmission efficiency between controller.
Summary of the invention
In view of this, the application provides a kind of data transmission method and device, controlled with solving two storages in the related technology
The low problem of data transmission efficiency between device processed.
According to the embodiment of the present application in a first aspect, providing a kind of data transmission method, the method is applied to storage control
Device processed, the storage control are equipped with FPGA, and the FPGA in the FPGA and opposite end storage control is interconnected by XAUI, institute
The method of stating includes:
It obtains to lower brush data, described the first memory will be written to lower brush data；
By the FPGA, with dma mode read in first memory to lower brush data, and by reading to lower brush
Data are sent to the FPGA in the storage control of opposite end by the XAUI.
According to the second aspect of the embodiment of the present application, a kind of data transmission device is provided, described device is applied to storage control
Device processed, the storage control are equipped with FPGA, and the FPGA in the FPGA and opposite end storage control is interconnected by XAUI, institute
Stating device includes:
Simultaneously writing module is obtained, it, will be described to lower brush data the first memory of write-in for obtaining to lower brush data；
Read and sending module, for by the FPGA, with dma mode read in first memory to lower brush number
According to, and reading is sent to by the XAUI to lower brush data to the FPGA in the storage control of opposite end.
Using the embodiment of the present application, by the way that the FPGA for controlling data transmission is arranged in storage control, CPU is being obtained
It gets when lower brush data, directly the first memory will can be written to lower brush data, be read under from the first memory by FPGA
Brush data, and being sent in the FPGA of opposite end storage control to lower brush data by reading by the channel XAUI, without
The data transmission realized between two storage controls is controlled by CPU, and since the FPGA in storage control is served only for
Carry out data transmission, therefore the data transmission efficiency between two storage controls can be improved, and since two storages control
FPGA in device is the data transmission realized by XAUI, and XAUI has the data transmission feature of high bandwidth, low delay, therefore
It can be further improved the data transmission efficiency between two storage controls.
Detailed description of the invention
Fig. 1 is a kind of the application dual control data interaction structure chart shown according to an exemplary embodiment；
Fig. 2 is a kind of the application embodiment flow chart of data transmission method shown according to an exemplary embodiment；
Fig. 3 is a kind of the application hardware structure diagram of storage control shown according to an exemplary embodiment；
Fig. 4 is a kind of the application example structure figure of data transmission device shown according to an exemplary embodiment.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects be described in detail in claims, the application.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not departing from
In the case where the application range, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determination ".
Fig. 1 is a kind of the application dual control data interaction structure chart shown according to an exemplary embodiment, the storage in Fig. 1
Controller A and storage control B is completely independent for two in dual control storage system and identical storage control, two storages
FPGA (Field Programmable Gate Array, field programmable gate array) between controller passes through XAUI
(10Gigabit Attachment Unit Interface, 10G accessory unit interface) realizes interconnection, between FPGA and memory
It is written and read by dma mode.
When there is data to send from storage control A to storage control B, the CPU in storage control A will be brushed under data
Into memory, when the FPGA in storage control A, which has found to have in memory, to be brushed under data, read from memory by dma mode
The data of lower brush, and the data are sent to the FPGA in storage control B by XAUI, the FPGA in storage control B is logical
Dma mode is crossed, memory is written using the data received as reported data, is had when in the CPU discovery memory in storage control B
When reported data is written, reported data is read from memory, and business processing is carried out to the reported data.
Based on foregoing description it is found that when having data transmission between two storage controls, directly by storage control
FPGA realize the transmission of two store controller datas, need not move through CPU control and realize data transmission, due to storage control
In FPGA be served only for carrying out the transmission of data, therefore the data transmission efficiency between two storage controls can be improved, again
Since FPGA in two storage controls is the data transmission realized by XAUI, and XAUI has high bandwidth, low delay
Data transmission feature, therefore can be further improved the data transmission efficiency between two storage controls.
It is described in detail below with technical solution of the specific embodiment to the application.
Fig. 2 is a kind of the application embodiment flow chart of data transmission method shown according to an exemplary embodiment, should
The embodiment of data transmission method can be applied to any storage control (hereinafter referred to as local terminal storage control in above-mentioned Fig. 1
Device), if embodiment is applied on storage control A, opposite end storage control is storage control B, if embodiment is answered
For storage control B, then opposite end storage control is to storage control A.As shown in Fig. 2, the data transmission method includes
Following steps:
Step 201: obtaining to lower brush data, described the first memory will be written to lower brush data.
In one embodiment, it for the process obtained to lower brush data, breaks down in opposite end storage control, recovery pair
When holding the business of storage control, the data in local terminal storage control can be determined as to lower brush data；Or local terminal is deposited
When storage controller receives externally input data, which can be also determined as to lower brush data.
In one embodiment, for by the process that the first memory is written to lower brush data, local terminal storage control can
To distribute one section of memory space from the first memory, and will be in the memory space of lower brush data write-in distribution.
Wherein, memory can be divided into the first memory and the second memory in advance by local terminal storage control, and the first memory is only
The data entered for storing CPU write, the second memory is served only for the data of storage FPGA write-in, due to belonging to CPU to lower brush data
The data to be written, it is therefore desirable to be written in the first memory.
Step 202: by the FPGA, with dma mode read in first memory to lower brush data.
In one embodiment, local terminal storage control can will be written after it the first memory will be written to lower brush data
Position informing to FPGA, thus the FPGA can according to the writing position, with dma mode read in first memory to
Lower brush data.
Wherein, writing position can be the initial address and offset of the memory space of distribution described in above-mentioned steps 201
Amount, it will be appreciated by persons skilled in the art that dma mode can be realized by the relevant technologies, this will not be detailed here by the application.
It should be noted that can be set in FPGA after it will read to lower brush data in the first memory for the first memory
The first label is set, to discharge the first memory when detecting that the first memory setting has the first label, and deletes the first label.
Wherein, it based on described in above-mentioned steps 201, can be marked for the memory space setting first distributed from the first memory
Note, for indicating that the data in this section of memory space have been walked by FPGA reading, so that the CPU when local terminal storage control is detected
When this section of memory space is provided with the first label, this section of memory space can be discharged, and deletes the first label, so that the section stores
Space can continue to use.
Step 203: by the FPGA, reading being sent to opposite end storage control by the XAUI to lower brush data
FPGA in device.
In one embodiment, local terminal storage control can be encapsulated as ethernet frame to lower brush data for described by FPGA
Afterwards, then by the ethernet frame by XAUI the FPGA being sent in the storage control of opposite end.
Wherein, since the channel XAUI is a kind of optical-fibre channel, and optical-fibre channel requires data to pass with the format of ethernet frame
It is defeated, it is therefore desirable to first will to retransmit the FPGA into opposite end storage control, such as table after lower brush data are encapsulated as ethernet frame
It is a kind of illustrative ethernet frame structure shown in 1,7 byte representations of lead code (Preamble) therein are used for data
The rate synchronization sent and received in transmission process；1 byte representation of frame first symbol (SFD), indicates that next byte starts
It is truthful data；6 byte representations of target MAC (Media Access Control) address (dst MAC), indicate the address of the recipient of frame；Source MAC
(srcMAC) with 6 byte representations, the address of the sender of frame is indicated；2 byte representations of length (length), indicate the frame
Data field length available；2 byte representations of type (type), indicate the protocol type of the frame data；Data and filling
(data and pad) belongs to data field, with 46~1500 byte representations, if Ethernet frame length after data field is added
Less than 64 bytes are spent, " filling " can be added in data field, until reaching 64 bytes；4 words of Frame Check Sequence (FCS)
Section indicates judge whether error of transmission if mistake abandons the ethernet frame to the ethernet frame for recipient.
Table 1
It should be noted that be the data for storing FPGA write-in based on the second memory described in above-mentioned steps 201, because
This reads data to be reported when local terminal storage control detects that the second memory setting has the second label from the second memory,
And delete second label, it is described second label be FPGA in the data to be reported for sending opposite end storage control with dma mode
The label added after the second memory is written, and business processing is carried out to the data to be reported of reading.
Wherein, the second label is for indicating that the data in the second memory have been walked by CPU reading, the sky that data can be occupied
Between discharge, and delete second label, with facilitate be recycled.
In the embodiment of the present application, by the way that the FPGA for controlling data transmission is arranged in storage control, CPU is being obtained
To when lower brush data, directly the first memory will can be written to lower brush data, be read from the first memory to lower brush by FPGA
Data, and being sent in the FPGA of opposite end storage control to lower brush data by reading by the channel XAUI, without warp
Cross CPU control realize two storage controls between data transmission, and due to the FPGA in storage control be served only for into
The transmission of row data, therefore the data transmission efficiency between two storage controls can be improved, and due to two storage controls
In FPGA be the data transmission realized by XAUI, and XAUI has the data transmission feature of high bandwidth, low delay, therefore can
To further increase the data transmission efficiency between two storage controls.
Fig. 3 is a kind of the application hardware structure diagram of storage control shown according to an exemplary embodiment, the storage
Controller includes: communication interface 301, processor 302, machine readable storage medium 303 and bus 304；Wherein, communication interface
301, processor 302 and machine readable storage medium 303 complete mutual communication by bus 304.Processor 302 passes through reading
Machine-executable instruction corresponding with the control logic of data transmission method in machine readable storage medium 302 is taken and executes, it can
Above-described data transmission method is executed, the particular content of this method is not repeated herein referring to above-described embodiment.
The machine readable storage medium 303 mentioned in the application can be any electronics, magnetism, optics or other physics and deposit
Storage device may include or store information, such as executable instruction, data, etc..For example, machine readable storage medium may is that
Volatile memory, nonvolatile memory or similar storage medium.Specifically, machine readable storage medium 303 can be
RAM (Radom Access Memory, random access memory), flash memory, memory driver (such as hard disk drive), any class
The storage dish (such as CD, DVD) of type perhaps similar storage medium or their combination.
Fig. 4 is a kind of the application example structure figure of data transmission device shown according to an exemplary embodiment, institute
Data transmission device is stated applied to any storage control in above-mentioned Fig. 1, as shown in figure 4, the data transmission device includes:
Simultaneously writing module 410 is obtained, it, will be described to lower brush data the first memory of write-in for obtaining to lower brush data；
Simultaneously sending module 420 is read, for reading described first with direct memory access dma mode by the FPGA
In memory to lower brush data, and being sent in the storage control of opposite end by the XAUI to lower brush data by reading
FPGA。
In an optional implementation, described device further includes (being not shown in Fig. 4):
Notification module, after in the acquisition, simultaneously described the first memory will be written to lower brush data in writing module, by
Writing position is notified to the FPGA；
It is described to read simultaneously sending module 420, it is specifically used for reading first memory by the FPGA with dma mode
In in lower brush data procedures, according to said write position, with dma mode read in first memory to lower brush number
According to.
In an optional implementation, described device further includes (being not shown in Fig. 4):
Simultaneously release module is marked, for reading in the simultaneously sending module 420 that reads by the FPGA with dma mode
In first memory to lower brush data after, by the FPGA be first memory setting first mark；Work as detection
When having the first label to first memory setting, first memory is discharged, and deletes first label.
It is described to read simultaneously sending module 420 in an optional implementation, it is specifically used for read by the FPGA
It, will be described to lower brush number during the FPGA being sent in the storage control of opposite end to lower brush data by the XAUI taken
According to being encapsulated as ethernet frame；The FPGA ethernet frame being sent to by the XAUI in the storage control of opposite end.
In an optional implementation, described device further includes (being not shown in Fig. 4):
Reported data obtains and processing module, for when detecting that the second memory setting has the second label, from described the
Data to be reported are read in two memories, and delete second label, and second label is that the FPGA is stored by opposite end
The label added after the second memory is written with dma mode in the data to be reported that controller is sent；To the data to be reported of reading into
Row business processing.
The function of each unit and the realization process of effect are specifically detailed in the above method and correspond to step in above-mentioned apparatus
Realization process, details are not described herein.
For device embodiment, since it corresponds essentially to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.The apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize application scheme.Those of ordinary skill in the art are not paying
Out in the case where creative work, it can understand and implement.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the application
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the application, these modifications, purposes or
Person's adaptive change follows the general principle of the application and including the undocumented common knowledge in the art of the application
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the application are by following
Claim is pointed out.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including described want
There is also other identical elements in the process, method of element, commodity or equipment.
The foregoing is merely the preferred embodiments of the application, not to limit the application, all essences in the application
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the application protection.
Claims (10)
1. a kind of data transmission method, which is characterized in that the method is applied to storage control, sets on the storage control
There is on-site programmable gate array FPGA, the FPGA in the FPGA and opposite end storage control passes through 10G accessory unit interface
XAUI interconnection, which comprises
It obtains to lower brush data, described the first memory will be written to lower brush data；
By the FPGA, with direct memory access dma mode read in first memory to lower brush data, and will read
The FPGA being sent to lower brush data by the XAUI in the storage control of opposite end.
2. the method according to claim 1, wherein after it described the first memory will be written to lower brush data,
The method also includes:
Writing position is notified to the FPGA；
By the FPGA with dma mode read in first memory to lower brush data, comprising:
According to said write position, with dma mode read in first memory to lower brush data.
3. the method according to claim 1, wherein reading described first by the FPGA with dma mode
In memory to lower brush data after, the method also includes:
It is first memory setting first label by the FPGA；
When detecting that first memory setting has the first label, first memory is discharged, and deletes first label.
4. the method according to claim 1, wherein by the FPGA, by passing through to lower brush data for reading
The XAUI is sent to the FPGA in the storage control of opposite end, comprising:
Ethernet frame is encapsulated as to lower brush data by described；
The FPGA ethernet frame being sent to by the XAUI in the storage control of opposite end.
5. the method according to claim 1, wherein the method further includes:
When detecting that the second memory setting has the second label, data to be reported are read from second memory, and delete institute
State the second label, second label be the FPGA in the data to be reported for sending opposite end storage control with dma mode
The label added after the second memory is written；
Business processing is carried out to the data to be reported of reading.
6. a kind of data transmission device, which is characterized in that described device is applied to storage control, sets on the storage control
There is on-site programmable gate array FPGA, the FPGA in the FPGA and opposite end storage control passes through 10G accessory unit interface
XAUI interconnection, described device include:
Simultaneously writing module is obtained, it, will be described to lower brush data the first memory of write-in for obtaining to lower brush data；
It reads and sending module is read in first memory for passing through the FPGA with direct memory access dma mode
To lower brush data, and reading is sent to by the XAUI to the FPGA in the storage control of opposite end to lower brush data.
7. device according to claim 6, which is characterized in that described device further include:
Notification module, for will be written after described the first memory will be written to lower brush data in the acquisition and writing module
Position informing gives the FPGA；
It is described read and sending module, specifically for read by the FPGA with dma mode in first memory to
In lower brush data procedures, according to said write position, with dma mode read in first memory to lower brush data.
8. device according to claim 6, which is characterized in that described device further include:
Simultaneously release module is marked, is used in the reading and sending module is by the FPGA, with dma mode reading described first
In memory to lower brush data after, by the FPGA be first memory setting first mark；When detecting described
When one memory setting has the first label, first memory is discharged, and deletes first label.
9. device according to claim 6, which is characterized in that it is described to read simultaneously sending module, specifically for passing through
FPGA is stated, it, will during the FPGA that reading is sent in the storage control of opposite end to lower brush data by the XAUI
It is described to be encapsulated as ethernet frame to lower brush data；The ethernet frame is sent in the storage control of opposite end by the XAUI
FPGA.
10. device according to claim 6, which is characterized in that described device further include:
Reported data obtains and processing module, for when detecting that the second memory setting has the second label, out of described second
Middle reading data to be reported are deposited, and delete second label, second label is that opposite end is being stored control by the FPGA
The label added after the second memory is written with dma mode in the data to be reported that device is sent；Industry is carried out to the data to be reported of reading
Business processing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811068363.3A CN109344097A (en) | 2018-09-13 | 2018-09-13 | Data transmission method and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811068363.3A CN109344097A (en) | 2018-09-13 | 2018-09-13 | Data transmission method and device |
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Application publication date: 20190215 |