CN109343337B - Multi-target fractional order PID control method for DC buck converter - Google Patents
Multi-target fractional order PID control method for DC buck converter Download PDFInfo
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Abstract
The invention discloses a multi-target fractional order PID control method for a direct current buck converter, which comprises the steps of taking the time of an error between actual output voltage and reference voltage of the direct current buck converter multiplied by absolute error integral, actual output voltage overshoot and stable time as three optimization objective functions, designing an efficient multi-target differential evolution solver to obtain an optimal control parameter of the fractional order PID control method in an off-line manner, and inputting the optimal control parameter into an actual digital processing signal processor, thereby realizing the real-time control of the actual output voltage of the direct current buck converter. Compared with the prior art, the method can automatically acquire the optimal control parameters of the direct current buck converter by means of a computer aided design technology, and the actual output voltage of the direct current buck converter has smaller overshoot and ripple, faster stable speed and better robust performance.
Description
Technical Field
The invention relates to the intelligent control technology in the field of power electronic conversion, in particular to a multi-target fractional order PID control method for a direct current buck converter.
Background
The switching power converter is an important link of a modern power electronic system, and the operating state of the switching power converter directly influences the working performance of the whole electronic system, so that modeling and control of the switching power converter are always one of research hotspots in academic circles and engineering application fields at home and abroad. Recent studies have shown that: as a typical piecewise-smooth nonlinear time-varying system, the switching power converter has nonlinear dynamics phenomena such as frequency reduction, low-frequency fluctuation, subharmonic oscillation, bifurcation, intermittence, chaos and the like, and the complex nonlinear characteristics seriously affect the performance of the system.
With the rapid development of digital controllers and signal processing techniques in recent years, digital control techniques are beginning to be widely applied to the fields of power conversion and ac driving. The stability and operating performance of a switching power converter are largely determined by a controller designed based on a system model. The traditional linear controllers such as Proportional-Integral-Derivative (PID) controllers have the advantages of simplicity, effectiveness and the like, are widely applied to actual engineering, but have better control performance only in a range near a specific working point, and are difficult to ensure the stability and normal operation under the working conditions of input signals or load sudden change and the like. Many scholars at home and abroad explore the stability limitation of sliding mode control, predictive control, fuzzy control and the like to improve the linear control mode, but the optimal design and digital implementation processes of the control methods of sliding mode control, predictive control, fuzzy control and the like are very complicated, and engineers with insufficient experience are difficult to implement in an engineering mode. Therefore, how to design an efficient control algorithm to improve the complex dynamic response speed and the robust performance is still an urgent problem to be solved in the field of power electronic power conversion.
Although fractional calculus and integer calculus occur almost simultaneously, fractional calculus has not received much attention because of its long-term lack of practical background. Until recently, research findings in the fields of physics, machinery, information, materials, engineering, and the like have shown that: the fractional order phenomenon not only exists actually, but also the system modeling, analyzing and controlling method based on the fractional order calculus theory is more accurate than the traditional integer order method, so that the fractional order calculus theory has wide application prospect and becomes a research in the academic and engineering application fieldsOne of the hot spots. In recent years, scholars at home and abroad perform fractional order modeling and computer simulation analysis on Boost converters in different modes of continuous, pseudo-continuous, discontinuous and the like of inductive current, so that the advantages of a fractional order model compared with an integer order model are further verified. In the fractional order control method, the fractional order PI is recently subjected toλDμStudies of the controller showed that: fractional order PI after introducing two adjustable fractional order parameters lambda and muλDμCompared with the traditional integer order PID controller, the controller has better dynamic and steady-state control performance and robustness; and more research work has verified the advantages of fractional order controls over integer order controls. However, the application research of the fractional order control method in the switching power conversion system is very limited, the fractional order PID control research aiming at the Boost converter and the Buck converter is mainly focused on, the adopted fractional order PID control parameters mainly depend on the experience of engineers or single target optimization methods such as a single target genetic algorithm, and the like, so that the compromise optimization of a plurality of performance indexes of the dynamic response and the steady state response of the output voltage of the direct current converter is difficult to realize simultaneously.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a multi-target fractional order PID control method for a direct current buck converter.
The invention aims to realize the control method through the following technical scheme, and the method is used for controlling the multi-target Fractional order PID of the direct current buck converter and is characterized in that a hardware part of the direct current buck converter comprises an input direct current power supply, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short), an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, an analog-to-digital converter, a digital signal processor, a current sensor, a voltage sensor and a driving circuit, the feedback control of the output voltage of the direct current buck converter is realized by adopting a Fractional-order proportional-integral-derivative (PID) control method, and control parameters in the Fractional order PID method are optimized and set through a multi-target differential-derivative solver, and the method can comprise the following steps:
(1) the Simulink simulation model for fractional order PID control of the output voltage of the direct current buck converter is established by MATLAB2012b software, and comprises a power system simulation module Powergui, an input direct current power supply, a MOSFET switching tube, an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, a reference value of the output voltage, a comparator, a fractional order PID control module, a pulse width modulation module, a current and voltage measurement module and a virtual oscilloscope, wherein a transfer function G of the fractional order PID controllerfc(s) is shown in equation (1):
Gfc(s)＝KP+KIs-λ+KDsμ (1)
wherein KPDenotes the proportionality coefficient, KIDenotes the integral coefficient, KDDenotes a differential coefficient, λ denotes an order of fractional order integration, and μ denotes an order of fractional order differentiation;
(2) setting parameters of a multi-target differential evolution solver: population size NP, variation factor F, crossover probability CR, maximum number of iterations ImaxThe maximum capacity of the external elite archive EA is NP;
(3) randomly generating a starting population P of size NPI＝{Pi1,2, NP, wherein the ith individual PiRepresenting 5 control parameters K for a fractional order PID controllerP、KI、KDLambda, mu, i.e. Pi＝[KP,KI,KD,λ,μ]The specific production process is as follows: pi＝R(CU－CL)+CLIn which C isUAnd CLRepresents KP、KI、KDUpper limit and lower limit vectors of 5 control parameters of lambda and mu, wherein R represents a uniformly distributed random number vector generated in a range of 0 to 1, and an initial value of an external elite archive EA is set as an empty set;
(4) p according to the formulas (2) to (4)IEvaluating the target function corresponding to each individual;
f2＝|Vomax-Vr| (3)
f3＝ts (4)
wherein f is1、f2And f3Respectively representing the 1 st, 2 nd and 3 rd objective functions, VoRepresenting the actual output voltage, V, of the DC buck converterrRepresenting the reference output voltage, V, of the DC buck converteromaxRepresenting the maximum value of the actual output voltage, tsRepresenting the settling time of the actual output voltage to a steady state value, t representing the simulated run time of the DC buck converter, tmaxA maximum time value representing a simulated run time window of the dc buck converter;
(5) p pairs using Pareto fitness evaluation criterion based on non-dominated rankingIIn the method, each individual is subjected to non-dominant sorting, and if only one non-dominant individual exists, the individual is marked as PN(ii) a If there are multiple non-dominant individuals, one non-dominant individual is selected according to the tournament policy, marked as PN；
(6) Updating the external elite archive EA, wherein the specific updating rule is as follows:
(6.1) if the existing capacity of EA is less than NP, PNAdding into EA;
(6.2) if the EA is full, then add P is first calculatedNThe crowding distance of all individuals in the subsequent EA is specifically calculated as follows: adding PNThe number of individuals in the subsequent EA is n ═ NP +1, and 3 fitness functions { f } corresponding to all individuals { EA (j) } 1,2k(ea (j)), j ═ 1,2, …, n, k ═ 1,2,3, respectively, are sorted in ascending order, such that f isk(EA(Ω(1)))≤fk(EA(Ω(2)))≤…≤fk(EA (Ω (n))), wherein Ω (j), j ═ 1,2, …, n is the ranking index, EA (n)))k(Ω (j)), j ═ 1,2, …, n denotes the individual in the external document EA whose k-th fitness function value rank is Ω (j), j ═ 1,2, …, n corresponds; EAk(omega (1)) and EAkThe congestion distances of (Ω (n)) are denoted by d (EA)k(omega (1))) and d (EA)k(Ω (n))), namely EAk(Ω(1))＝EAk(Ω (n)) ═ infinity; EA of other individualskThe congestion distance of (Ω (j)), j being 2, …, and (n-1) is denoted by d (EA)k(Ω (j))), j ═ 2, …, (n-1), as calculated according to equation (5):
if PNIs the minimum distance of congestion, PNNot added to the EA; otherwise, P will be usedNReplacing the non-dominant solution corresponding to the densest position in the EA;
(7) for each individual PiFrom PIThree different individuals P are randomly selectedr1、Pr2And Pr3Performing real number variation according to formula (6) to generate a new variant individual PmiThe population after mutation is marked as Pm＝{Pmi,i＝1,2,…,NP}；
Pmi＝Pr3+F(Pr1-Pr2),r1≠r2≠r3≠i,i＝1,2,…,NP (6)
Wherein F represents a mutagen, and r1, r2 and r3 represent three different individuals randomly selected from PIThe sequence number of (1);
(8) generating a population P after the crossover operation according to the crossover operation shown in equation (7)c＝{Pci,i＝1,2,…,NP}；
Wherein P isciRepresenting new individuals after crossover operation, CR representing crossover probability, riRepresents a uniformly distributed random number generated in the range of 0 to 1;
(9) judging whether the current iteration number is less than the set maximum iteration number Imax(ii) a If so, then P is unconditionally acceptedI＝PcReturning to the step (4)) (ii) a Otherwise, entering the step (10);
(10) taking the final external elite archive EA as a final Pareto optimal solution set, and selecting EAk(omega (0.5NP)) as the optimum control parameter K of the fractional order PID controllerP、KI、KD、λ、μ；
(11) Aiming at the actual direct current buck converter corresponding to the Simulink simulation model in the step (1), the hardware part of the direct current buck converter comprises an input direct current power supply, an MOSFET (metal oxide semiconductor field effect transistor), an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, an analog-to-digital converter, a digital signal processor, a current sensor, a voltage sensor and a driving circuit, the digital signal processor is adopted to realize a fractional order PID controller, and the optimal control parameter K of the fractional order PID controller obtained in the step (10) is usedP、KI、KDAnd lambda and mu are input into a digital signal processor, so that the optimal control of the output voltage of the direct current buck converter is realized, and the specific realization process is as follows:
(11.1) setting the sampling period to TsReference output voltage V at kth sampling period of DC buck converterr(k)；
(11.2) the voltage sensor detects the actual output voltage signal V of the DC step-down convertero(t) to an analog-to-digital converter which outputs an output voltage signal V at the kth sampling periodo(k)；
(11.3) the digital signal processor calculates the error signal e (k) Vr(k)－Vo(k)；
(11.4) obtaining the optimal control parameter K of the fractional order PID controller obtained in the step (10)P、KI、KDLambda and mu are input into a digital signal processor, and the digital signal processor calculates an output signal d (k) of the controller at the kth sampling period according to a fractional order PID controller shown as a formula (1);
(11.5) converting d (k) into a pulse width duty ratio signal d (t) by a pulse width modulation module in the digital signal processor, and controlling an MOSFET switching tube by a driving circuit so as to realize the optimized control of the output voltage of the direct current buck converter;
(12) and recording and displaying the output voltage real-time signal of the direct current buck converter by using an oscilloscope.
The invention has the following effective effects: compared with the prior art, the method can automatically acquire the optimal control parameters of the direct current buck converter by means of a computer aided design technology, and the actual output voltage of the direct current buck converter has smaller overshoot and ripple, faster stable speed and better robust performance.
Drawings
FIG. 1 is a schematic diagram of a multi-target fractional order PID control method for a DC buck converter;
FIG. 2 is a schematic diagram of an implementation of a multi-objective fractional order PID control method for a DC buck converter.
Detailed Description
The purpose and effect of the present invention will be more apparent from the following further description of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a multi-target digital fractional order PID control method for a DC buck converter, where L represents inductance, C represents capacitance, and R representslRepresenting a resistance, R, in series with an inductancecRepresenting a resistance, R, in series with a capacitoroDenotes the output resistance, S1And S2Respectively representing the on-state and off-state of a switching tube in a DC buck converter, Vi(t) represents the continuous-time input voltage, V, of the DC buck convertero(t) represents the continuous-time actual output voltage of the DC buck converter, IL(t) represents the continuous-time current through the inductor, Vo(k) Representing the actual discrete-time output voltage of the DC buck converter during the k-th sampling period, e (k) representing the discrete-time error signal during the k-th sampling period, Vr(k) The digital pulse width modulator is used for expressing the discrete time reference output voltage of the direct current buck converter in the k sampling period, d (k) expresses the discrete time output signal of the fractional order PID controller in the k sampling period, d (t) expresses the pulse width duty ratio signal output by the digital pulse width modulator, and the fractional order PID controller is realized by adopting a digital signal processor.
FIG. 2 is a schematic diagram of an implementation of a multi-objective fractional order PID control method for a DC buck converter.
Take the DC buck converter shown in FIG. 1 as an example, where the system parameter is Vi(t) 10-15V, Vr(t) 5 volts, L17.5 microhenries, Rl0.8 ohm, C250 microfarad, Rc0.3 ohm, RoThe method is implemented by adopting the multi-target digital fractional order PID control technology provided by the invention when the power is 0.3 ohm.
(1) MATLAB2012b software is adopted to establish a Simulink simulation model for fractional order PID control of output voltage of a direct current buck converter shown in figure 1, and the Simulink simulation model comprises a power system simulation module Powergui, an input direct current power supply, a MOSFET switching tube, an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, a reference value of output voltage, a comparator, a fractional order PID control module, a pulse width modulation module, a current and voltage measurement module and a virtual oscilloscope, wherein a transfer function G of the fractional order PID controllerfc(s) is shown in equation (1):
Gfc(s)＝KP+KIs-λ+KDsμ (1)
wherein KPDenotes the proportionality coefficient, KIDenotes the integral coefficient, KDDenotes a differential coefficient, λ denotes an order of fractional order integration, and μ denotes an order of fractional order differentiation;
(2) setting parameters of a multi-target differential evolution solver: population size NP of 50, variation factor F of 1.2, crossover probability CR of 0.9, maximum number of iterations Imax300, the maximum capacity NP of the external elite archive EA 50;
(3) randomly generating a starting population P of size NPI＝{Pi1,2, NP, wherein the ith individual PiRepresenting 5 control parameters K for a fractional order PID controllerP、KI、KDLambda, mu, i.e. Pi＝[KP,KI,KD,λ,μ]The specific production process is as follows: pi＝R(CU－CL)+CLIn which C isUAnd CLRepresents KP、KI、KDUpper limit and lower limit vectors of 5 control parameters of lambda and mu, wherein R represents a uniformly distributed random number vector generated in a range of 0 to 1, and an initial value of an external elite archive EA is set as an empty set;
(4) p according to the formulas (2) to (4)IEvaluating the target function corresponding to each individual;
f2＝|Vomax-Vr| (3)
f3＝ts (4)
wherein f is1、f2And f3Respectively representing the 1 st, 2 nd and 3 rd objective functions, VoRepresenting the actual output voltage, V, of the DC buck converterrRepresenting the reference output voltage, V, of the DC buck converteromaxRepresenting the maximum value of the actual output voltage, tsRepresenting the settling time of the actual output voltage to a steady state value, t representing the simulated run time of the DC buck converter, tmaxA maximum time value representing a simulated run time window of the dc buck converter;
(5) p pairs using Pareto fitness evaluation criterion based on non-dominated rankingIIn the method, each individual is subjected to non-dominant sorting, and if only one non-dominant individual exists, the individual is marked as PN(ii) a If there are multiple non-dominant individuals, one non-dominant individual is selected according to the tournament policy, labeled PN；
(6) Updating the external elite archive EA, wherein the specific updating rule is as follows:
(6.1) if the existing capacity of EA is less than NP, PNAdding into EA;
(6.2) if the EA is full, then add P is first calculatedNThe crowding distance of all individuals in the subsequent EA is specifically calculated as follows: adding PNNumber of individuals in post-EAThe quantity n is NP +1, and 3 fitness functions { f, corresponding to all individuals { EA (j) }, j is 1,2k(ea (j)), j ═ 1,2, …, n, k ═ 1,2,3, respectively, are sorted in ascending order, such that f isk(EA(Ω(1)))≤fk(EA(Ω(2)))≤…≤fk(EA (Ω (n))), wherein Ω (j), j ═ 1,2, …, n is the ranking index, EA (n)))k(Ω (j)), j ═ 1,2, …, n denotes the individual in the external document EA whose k-th fitness function value rank is Ω (j), j ═ 1,2, …, n corresponds; EAk(omega (1)) and EAkThe congestion distances of (Ω (n)) are denoted by d (EA)k(omega (1))) and d (EA)k(Ω (n))), namely EAk(Ω(1))＝EAk(Ω (n)) ═ infinity; EA of other individualskThe congestion distance of (Ω (j)), j being 2, …, and (n-1) is denoted by d (EA)k(Ω (j))), j ═ 2, …, (n-1), as calculated according to equation (5):
if PNIs the minimum distance of congestion, PNNot added to the EA; otherwise, P will be usedNReplacing the non-dominant solution corresponding to the densest position in the EA;
(7) for each individual PiFrom PIThree different individuals P are randomly selectedr1、Pr2And Pr3Performing real number variation according to formula (6) to generate a new variant individual PmiThe population after mutation is marked as Pm＝{Pmi,i＝1,2,…,NP}；
Pmi＝Pr3+F(Pr1-Pr2),r1≠r2≠r3≠i,i＝1,2,…,NP (6)
Wherein F represents a mutagen, and r1, r2 and r3 represent three different individuals randomly selected from PIThe sequence number of (1);
(8) generating a population P after the crossover operation according to the crossover operation shown in equation (7)c＝{Pci,i＝1,2,…,NP}；
Wherein P isciRepresenting new individuals after crossover operation, CR representing crossover probability, riRepresents a uniformly distributed random number generated in the range of 0 to 1;
(9) judging whether the current iteration number is less than the set maximum iteration number Imax(ii) a If so, then P is unconditionally acceptedI＝PcReturning to the step (4); otherwise, entering the step (10);
(10) taking the final external elite archive EA as a final Pareto optimal solution set, and selecting EAk(omega (0.5NP)) as the optimum control parameter K of the fractional order PID controllerP、KI、KD、λ、μ；
(11) Aiming at the actual direct current buck converter corresponding to the Simulink simulation model in the step (1), the hardware part of the direct current buck converter comprises an input direct current power supply, an MOSFET (metal oxide semiconductor field effect transistor), an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, an analog-to-digital converter, a digital signal processor, a current sensor, a voltage sensor and a driving circuit, the digital signal processor is adopted to realize a fractional order PID controller, and the optimal control parameter K of the fractional order PID controller obtained in the step (10) is usedP、KI、KDAnd lambda and mu are input into a digital signal processor, so that the optimal control of the output voltage of the direct current buck converter is realized, and the specific realization process is as follows:
(11.1) establishing a continuous time differential equation of the direct current buck converter shown in the formulas (8) and (9) by a mechanism analysis modeling method;
where Ψ (t) denotes a switching signal of the switching tubeI.e. by
(11.2) setting the sampling period Ts0.00001 second, reference output voltage V at k-th sampling period of DC buck converterr(k) 15 volts; discretizing the equations (8) and (9) to obtain discrete time difference equations of the direct current buck converter shown in the equations (10) and (11); the voltage sensor detects the actual output voltage signal V of the DC buck convertero(t) to an analog-to-digital converter which outputs an output voltage signal V at the kth sampling periodo(k)；
Wherein, Vo(k +1) denotes the discrete-time actual output voltage of the DC buck converter at the (k +1) th sampling period, IL(k) And IL(k +1) denotes the discrete-time current through the inductor at the kth and (k +1) th sampling periods, respectively, Vi(k) Representing the discrete-time input voltage of the direct current buck converter in the k sampling period, and psi (k) representing the switching state of the switching tube in the k sampling period;
(11.3) the digital signal processor calculates the error signal e (k) Vr(k)－Vo(k)；
(11.4) obtaining the optimal control parameter K of the fractional order PID controller obtained in the step (10)P、KI、KDLambda and mu are input into a digital signal processor, the digital signal processor calculates an output signal d (k) of the controller in the kth sampling period according to a fractional order PID controller shown in a formula (1), and the discretization method adopted by the fractional order PID controller in the embodiment is an Oustaloup filter digital implementation method;
(11.5) converting d (k) into a pulse width duty ratio signal d (t) by a pulse width modulation module in the digital signal processor, and controlling an MOSFET switching tube by a driving circuit so as to realize the optimized control of the output voltage of the direct current buck converter;
(12) and recording and displaying the output voltage real-time signal of the direct current buck converter by using an oscilloscope.
Aiming at the embodiment, compared with the existing integer order PID control and the fractional order PID control technology based on the single target genetic algorithm, the overshoot of the actual output voltage of the direct current buck converter implemented by the invention is reduced by at least 10%, the output ripple is reduced by at least 30%, the stabilization time is reduced by at least 15%, and the anti-interference capability is improved by at least 8%.
In summary, the multi-objective optimization control effect on the output voltage of the actual dc buck converter is realized by the technology of the present invention, and the following advantages are provided, which are not provided by the prior art: the invention can automatically acquire the optimal control parameters of the direct current buck converter by means of a computer aided design technology, and the actual output voltage of the direct current buck converter has smaller overshoot and ripple waves, faster stable speed and better robust performance.
Claims (3)
1. A multi-target fractional order PID control method for a DC buck converter is characterized in that the feedback control of the output voltage of the DC buck converter is realized by adopting a fractional order PID control method, and control parameters in the fractional order PID control method are optimized and set by a multi-target differential evolution solution and a decision maker, and the method comprises the following steps:
(1) the simulation method comprises the steps that MATLAB software is adopted to establish a Simulink simulation model for fractional order PID control of output voltage of a direct current buck converter, and the Simulink simulation model mainly comprises a power system simulation module Powergui, an input direct current power supply, a MOSFET switch tube, an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, a reference value of the output voltage, a comparison arithmetic unit, a fractional order PID control module, a pulse width modulation module, a current and voltage measurement module and a virtual oscilloscope; wherein the transfer function G of the fractional order PID controllerfc(s) is shown in equation (1):
Gfc(s)＝KP+KIs-λ+KDsμ (1)
wherein KPDenotes the proportionality coefficient, KIDenotes the integral coefficient, KDDenotes a differential coefficient, λ denotes an order of fractional order integration, and μ denotes an order of fractional order differentiation;
(2) setting parameters of a multi-target differential evolution solver, including population scale NP, a variation factor F, a cross probability CR and a maximum iteration number ImaxThe maximum capacity of the external elite archive EA is NP;
(3) randomly generating a starting population P of size NPI＝{Pi1,2, NP, wherein the ith individual PiRepresenting 5 control parameters K for a fractional order PID controllerP、KI、KDLambda, mu, i.e. Pi＝[KP,KI,KD,λ,μ]The specific production process is as follows: pi＝R(CU－CL)+CLIn which C isUAnd CLRepresents KP、KI、KDThe upper limit vector and the lower limit vector of 5 control parameters of lambda and mu, wherein R represents a uniformly distributed random number vector generated in the range of 0 to 1, and the initial value of an external elite archive EA is set as an empty set;
(4) p according to the formulas (2) to (4)IEvaluating the target function corresponding to each individual;
f2＝|Vomax-Vr| (3)
f3＝ts (4)
wherein f is1、f2And f3Respectively representing the 1 st, 2 nd and 3 rd objective functions, VoRepresenting the actual output voltage of the dc down-converter,Vrrepresenting the reference output voltage, V, of the DC buck converteromaxRepresenting the maximum value of the actual output voltage, tsRepresenting the settling time of the actual output voltage to a steady state value, t representing the simulated run time of the DC buck converter, tmaxA maximum time value representing a simulated run time window of the dc buck converter;
(5) p pairs using Pareto fitness evaluation criterion based on non-dominated rankingIIn the method, each individual is subjected to non-dominant sorting, and if only one non-dominant individual exists, the individual is marked as PN(ii) a If there are multiple non-dominant individuals, one non-dominant individual is selected according to the tournament policy, marked as PN；
(6) Updating an external elite archive EA;
(7) for each individual PiFrom PIThree different individuals P are randomly selectedr1、Pr2And Pr3Performing real number variation according to formula (6) to generate a new variant individual PmiThe population after mutation is marked as Pm＝{Pmi,i＝1,2,…,NP}；
Pmi＝Pr3+F(Pr1-Pr2),r1≠r2≠r3≠i,i＝1,2,…,NP (6)
Wherein F represents a mutation factor, and r1, r2 and r3 represent three different individuals randomly selected from PIThe sequence number of (1);
(8) generating a population P after the crossover operation according to the crossover operation shown in equation (7)c＝{Pci,i＝1,2,…,NP}；
Wherein, PciRepresenting new individuals after crossover operation, CR representing crossover probability, riRepresents a uniformly distributed random number generated in the range of 0 to 1;
(9) judging whether the current iteration number is less than the set maximum iteration number Imax(ii) a If so,then unconditionally accepts PI＝PcReturning to the step (4); otherwise, entering the step (10);
(10) taking the final external elite archive EA as a final Pareto optimal solution set, and selecting EAk(omega (0.5NP)) as the optimum control parameter K of the fractional order PID controllerP、KI、KD、λ、μ；
(11) Aiming at the actual direct current buck converter corresponding to the Simulink simulation model in the step (1), the hardware part of the direct current buck converter comprises an input direct current power supply, an MOSFET (metal oxide semiconductor field effect transistor), an inductor, a resistor connected with the inductor in series, a filter capacitor, a filter resistor, an output resistor, an analog-to-digital converter, a digital signal processor, a current sensor, a voltage sensor and a driving circuit, the digital signal processor is adopted to realize a fractional order PID controller, and the optimal control parameter K of the fractional order PID controller obtained in the step (10) is usedP、KI、KDLambda and mu are input into a digital signal processor, so that the optimal control of the output voltage of the direct current buck converter is realized;
(12) and recording and displaying the output voltage real-time signal of the direct current buck converter by using an oscilloscope.
2. The multi-target fractional order PID control method for a dc down-converter according to claim 1, wherein in the step (6), the specific update rule is as follows:
(6.1) if the existing capacity of EA is less than NP, PNAdding into EA;
(6.2) if the EA is full, then add P is first calculatedNThe crowding distance of all individuals in the subsequent EA is specifically calculated as follows: adding PNThe number of individuals in the subsequent EA is marked as n, that is, n equals NP +1, and 3 fitness functions { f corresponding to all individuals { EA (j) } in the EA, j equals 1,2k(ea (j)), j ═ 1,2, …, n, k ═ 1,2,3, respectively, are sorted in ascending order, such that f isk(EA(Ω(1)))≤fk(EA(Ω(2)))≤…≤fk(EA (Ω (n))), wherein Ω (j), j ═ 1,2, …, n is the ranking index, EA (n)))k(Ω (j)), j is 1,2, …, and n represents the k-thThe fitness function values are sorted into omega (j), j is 1,2, …, and n corresponds to the individual in the external document EA; EAk(omega (1)) and EAkThe congestion distances of (Ω (n)) are denoted by d (EA)k(omega (1))) and d (EA)k(Ω (n))), namely EAk(Ω(1))＝EAk(Ω (n)) ═ infinity; EA of other individualskThe congestion distance of (Ω (j)), j being 2, …, and (n-1) is denoted by d (EA)k(Ω (j))), j ═ 2, …, (n-1), as calculated according to equation (5):
if PNIs the minimum distance of congestion, PNNot added to the EA; otherwise, P will be usedNThe non-dominant solution corresponding to the densest position in the EA is replaced.
3. The multi-objective fractional order PID control method for a dc down-converter according to claim 1, wherein the specific implementation procedure in the step (11) is as follows:
(11.1) setting the sampling period to TsThe reference output voltage of the DC buck converter in the kth sampling period is Vr(k)；
(11.2) the voltage sensor detects the actual output voltage signal V of the DC step-down convertero(t) to an analog-to-digital converter which outputs an output voltage signal V at the kth sampling periodo(k)；
(11.3) the digital signal processor calculates the error signal e (k) Vr(k)－Vo(k)；
(11.4) obtaining the optimal control parameter K of the fractional order PID controller obtained in the step (10)P、KI、KDLambda and mu are input into a digital signal processor, and the digital signal processor calculates an output signal d (k) of the controller at the kth sampling period according to a fractional order PID controller model shown as a formula (1);
(11.5) the pulse width modulation module in the digital signal processor converts d (k) into a pulse width duty ratio signal d (t), and then the MOSFET switching tube is controlled by the driving circuit, so that the optimal control of the output voltage of the direct current buck converter is realized.
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