CN109324828A - A method of it orders realization flash memory more in verification platform and executes parallel - Google Patents
A method of it orders realization flash memory more in verification platform and executes parallel Download PDFInfo
- Publication number
- CN109324828A CN109324828A CN201811108370.1A CN201811108370A CN109324828A CN 109324828 A CN109324828 A CN 109324828A CN 201811108370 A CN201811108370 A CN 201811108370A CN 109324828 A CN109324828 A CN 109324828A
- Authority
- CN
- China
- Prior art keywords
- order
- verification platform
- lun
- target
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention disclose it is a kind of in verification platform realize flash memory more order the method executed parallel, flush memory device is simulated on verification platform, each LUN corresponds to an order execution thread, main thread resolve command and the data return for executing immediate command, realize the parallel execution ordered on different memory hierarchies on TARGET, LUN.The number of TARGET, LUN, the i.e. quantity of parametrization generation order execution thread are parameterized, convenient for being transplanted in the verification platform of different flash memory storage structures.The corresponding different order implementation procedure of different orders, facilitates the transplanting and multiplexing of command operation.
Description
Technical field
The present invention relates to realizing that flash memory orders the method executed parallel more in a kind of verification platform, belong to memory technology neck
Domain.
Background technique
When operating true flush memory device, flash memory (NAND FLASH) usually needs to execute a plurality of order parallel, and
It is independent of each other between a plurality of order executed parallel, that is, while executing first command, can receive and execute Article 2 life
It enables, realizes the parallel execution of first command and second command.According to the storage organization feature of flash memory, there are three types of parallel for flash memory
Order executive mode: it is executed parallel between different TARGET and executes order, phase parallel between order, identical TARGET difference LUN
Order is executed on LUN identical with TARGET parallel.Present verification platform is by using parallel model (not face object language
The model write) mode realize flash memory order more it is parallel execute, it is complicated that there are model internal signal functions, is unfavorable for model and repairs
Change, new features increase and the defects of model transplantations, limit model usage scenario, cannot simply and easily apply there are different spies
Property require verification platform in.
Summary of the invention
In view of the drawbacks of the prior art, the present invention provide it is a kind of realizing to order flash memory in verification platform more parallel execute
Method executes life parallel to realize between different TARGET, between identical TARGET difference LUN, on the identical LUN of identical TARGET
It enables.
In order to solve the technical problem, the technical solution adopted by the present invention is that: one kind realizing flash memory in verification platform
Order the method executed parallel, comprising the following steps: S01 more), verification platform be each TARGET on each LUN generate
One order execution thread, each TARGET and each LUN have unique label to identify, and order execution thread is in etc.
Wait Order triggering state, verification platform main thread, which is in, waits Wait Orders input state, main thread and each order execution thread
It is parallel to execute；S02), after verification platform main thread receives order, order is sent to command analysis device and solved by main thread
Analysis parses the order needed to be implemented and TARGET, LUN for executing the order number；S03) if, the order be to order immediately
It enables, command analysis device executes the command operation and output data is put into data register output, and main thread returns to waiting for order
Input state, not trigger command execution thread；S04) if, the order be the order with delay, the triggering of command analysis device is corresponding
TARGET, LUN number order execution thread, while will order output give the order execution thread, main thread returns to waiting for
Order input state, order execution thread receive event triggering, execute the subsequent operation of the order；S05) if, a certain
In the order execution thread implementation procedure of a TARGET, LUN, main thread receives new command request, then executes repetition step
S02、S03、S04。
Further, before executing this method, flash memory architecture is established in verification platform first, flash memory architecture includes multiple
TARGET, command analysis device and data register, each TARGET include multiple LUN, the order of command analysis device parsing input
And it is transferred to the LUN of corresponding TARGET, data and output after data register deposit command analysis.
Further, this method is applied in the verification platform based on object oriented language.
Beneficial effects of the present invention: this method in verification platform for realizing that the more order parallel work-flows of flash memory are simply bright
, flush memory device is simulated on verification platform, the corresponding order execution thread of each LUN, main thread resolve command is simultaneously held
The data of row immediate command return, and realize the parallel execution ordered on different memory hierarchies on TARGET, LUN.Ginseng
The quantity that the number of numberization TARGET, LUN, i.e. parametrization generate order execution thread, convenient for being transplanted to different flash memory storages
In the verification platform of structure.The corresponding different order implementation procedure of different orders, facilitates the transplanting and multiplexing of command operation.
This method can be applied in the verification platform based on object oriented language, compared in the parallel mould of verification platform
The method that the mode of type (model that not face object language is write) realizes flash memory model, between this method functional module mutually solely
It is vertical, increase additive model convenient for model modification, new features and transplanted on different verification platforms, can preferably apply there are different spies
Property require verification platform in.
Detailed description of the invention
Fig. 1 is flush memory device storage organization schematic diagram；
Fig. 2 is flash memory model framework schematic diagram in verification platform；
Fig. 3 is main thread implementation procedure schematic diagram；
Fig. 4 is the implementation procedure schematic diagram of an order execution thread.
Specific embodiment
The present invention is further illustrated in the following with reference to the drawings and specific embodiments.
As shown in Figure 1, being flush memory device storage organization schematic diagram, including multiple TARGET, each TARGET include more again
A LUN, order is input to flash memory, and after address resolution, reading and writing data behaviour is executed from TARGET, LUN of corresponding address
Make.According to the storage organization of flash memory, order, phase can be executed parallel between different TARGET there are three types of parallel command executive mode
With executing order on TARGET difference LUN parallel, parallel on the identical LUN of identical TARGET executes order.According to flash command
Feature can be divided into order and the order with delay immediately, and it is complete that flash memory receives the instant data for returning to request after ordering immediately
At the command operation, after flash memory receives the order with delay, subsequent operation needs the flash memory consumption regular hour to complete
Operation, identifies whether the current command operates completion using the status signal on flash interface.Between different TARGET or phase
When with execution order parallel on TARGET difference LUN, parallel execution order can be any order, identical in identical TARGET
When the upper parallel execution of LUN is ordered, if the order of previous item input is with the order of delay, latter item order must be instant
Order.
This method is exactly to be proposed according to the These characteristics of flash memory.
Described in the present embodiment in verification platform realize flash memory more order the method executed parallel the following steps are included:
S01), flash memory architecture is established in verification platform, as shown in Fig. 2, flash memory architecture includes multiple TARGET, command analysis device and data
Register, each TARGET include multiple LUN, the order that the parsing of command analysis device inputs and the LUN for being transferred to corresponding TARGET,
Data and output after data register deposit command analysis.
S02), verification platform is that each LUN on each TARGET generates an order execution thread, each TARGET
There is unique label to identify with each LUN, order execution thread, which is in, waits command triggers state, verification platform main line
Journey, which is in, waits Wait Orders input state, and main thread executes parallel with each order execution thread；
S03), after verification platform main thread receives order, order is sent to command analysis device and parsed by main thread, parsing
The order that needs to be implemented out and TARGET, LUN for executing the order number；
S04) if, the order be to order immediately, command analysis device executes the command operation and output data is put into data and posts
Storage output, main thread return to waiting for order input state, not trigger command execution thread；
S05) if, the order be the order with delay, the order that command analysis device triggers corresponding TARGET, LUN number is held
Line journey, while giving order output to the order execution thread, main thread returns to waiting for order input state, order execution thread
Event triggering is received, the subsequent operation of the order is executed；
S06) if, in the order execution thread implementation procedure of some TARGET, LUN, main thread receives new order
Request, then execute repetition step S03, S04, S05.
As shown in figure 3, being main thread implementation procedure schematic diagram, Fig. 4 is the implementation procedure of an order execution thread, each
The corresponding order execution thread of a LUN, order execution thread execute parallel with main thread.
The present embodiment the method is being verified for realizing that the more order parallel work-flows of flash memory are simple and clear in verification platform
Flush memory device is simulated on platform, the corresponding order execution thread of each LUN, main thread resolve command simultaneously executes immediate command
Data return, realize on TARGET, LUN the parallel execution ordered on different memory hierarchies.Parametrization TARGET,
The quantity that the number of LUN, i.e. parametrization generate order execution thread is put down convenient for being transplanted to the verifying of different flash memory storage structures
In platform.The corresponding different order implementation procedure of different orders, facilitates the transplanting and multiplexing of order.
This method can be applied in the verification platform based on object oriented language, compared in the parallel mould of verification platform
The method that the mode of type (model that not face object language is write) realizes flash memory model, between this method functional module mutually solely
It is vertical, increase additive model convenient for model modification, new features and transplanted on different verification platforms, can preferably apply there are different spies
Property require verification platform in.
Described above is only basic principle and preferred embodiment of the invention, and those skilled in the art do according to the present invention
Improvement and replacement out, belong to the scope of protection of the present invention.
Claims (3)
1. a kind of order the method executed parallel realization flash memory in verification platform more, it is characterised in that: the following steps are included:
S01), verification platform be each TARGET on each LUN generate an order execution thread, each TARGET and each
LUN has unique label to identify, order execution thread be in wait command triggers state, verification platform main thread be in etc.
Wait Order input state, main thread execute parallel with each order execution thread；S02), when verification platform main thread receives
After order, order is sent to command analysis device and parsed by main thread, is parsed the order needed to be implemented and is executed the order
TARGET, LUN number；S03) if, the order be to order immediately, command analysis device executes the command operation and by output data
It is put into data register output, main thread returns to waiting for order input state, not trigger command execution thread；S04) if, should
Order is the order with delay, and command analysis device triggers the order execution thread of corresponding TARGET, LUN number, while will life
Output is enabled to give the order execution thread, main thread returns to waiting for order input state, and order execution thread receives event triggering,
Execute the subsequent operation of the order；S05) if, in the order execution thread implementation procedure of some TARGET, LUN, main line
Journey receives new command request, then executes repetition step S02, S03, S04.
2. according to claim 1 order the method executed parallel realization flash memory in verification platform more, it is characterised in that:
Before executing this method, flash memory architecture is established in verification platform first, flash memory architecture includes multiple TARGET, command analysis device sum number
According to register, each TARGET includes multiple LUN, and the order of command analysis device parsing input is simultaneously transferred to corresponding TARGET's
LUN, data register deposit command analysis after data and output.
3. according to claim 1 order the method executed parallel realization flash memory in verification platform more, it is characterised in that:
This method is applied in the verification platform based on object oriented language.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811108370.1A CN109324828B (en) | 2018-09-21 | 2018-09-21 | Method for realizing flash memory multi-command parallel execution in verification platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811108370.1A CN109324828B (en) | 2018-09-21 | 2018-09-21 | Method for realizing flash memory multi-command parallel execution in verification platform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109324828A true CN109324828A (en) | 2019-02-12 |
| CN109324828B CN109324828B (en) | 2023-06-02 |
Family
ID=65266236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811108370.1A Active CN109324828B (en) | 2018-09-21 | 2018-09-21 | Method for realizing flash memory multi-command parallel execution in verification platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109324828B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147373A (en) * | 2019-05-23 | 2019-08-20 | 泰康保险集团股份有限公司 | Data processing method, device and electronic equipment |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000023876A2 (en) * | 1998-10-16 | 2000-04-27 | Auspice, Inc. | Enterprise communication protocol |
| CN1613120A (en) * | 2002-01-04 | 2005-05-04 | 英特尔公司 | Flash memory access using a plurality of command cycles |
| US20080060072A1 (en) * | 2006-09-01 | 2008-03-06 | Fuji Xerox Co., Ltd. | Information processing system, information processing method, information processing program, computer readable medium and computer data signal |
| US20100217849A1 (en) * | 2009-02-26 | 2010-08-26 | Oracle International Corporation | Automatic Administration of UNIX Commands |
| CN102012791A (en) * | 2010-10-15 | 2011-04-13 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
| RU2454739C1 (en) * | 2011-01-12 | 2012-06-27 | Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации | Method of programming nand flash memory ic and apparatus for realising said method |
| US20120173792A1 (en) * | 2010-12-30 | 2012-07-05 | Lassa Paul A | Controller and Method for Performing Background Operations |
| CN102890477A (en) * | 2012-09-26 | 2013-01-23 | 西安交通大学 | On-line active dynamic balance measurement and control device and on-line active dynamic balance measurement and control method |
| US20140089567A1 (en) * | 2012-09-24 | 2014-03-27 | Violin Memory Inc | Hardware integrity verification |
| WO2016039774A1 (en) * | 2014-09-12 | 2016-03-17 | Intel Corporation | Facilitating dynamic parallel scheduling of command packets at graphics processing units on computing devices |
| CN105788636A (en) * | 2016-04-05 | 2016-07-20 | 山东华芯半导体有限公司 | EMMC controller based on parallel multichannel structure |
| CN105830040A (en) * | 2013-12-20 | 2016-08-03 | 拉姆伯斯公司 | A memory appliance for accessing memory |
| CN106469026A (en) * | 2015-08-14 | 2017-03-01 | 马维尔国际贸易有限公司 | Flexible interface for nand flash memory |
-
2018
- 2018-09-21 CN CN201811108370.1A patent/CN109324828B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000023876A2 (en) * | 1998-10-16 | 2000-04-27 | Auspice, Inc. | Enterprise communication protocol |
| CN1613120A (en) * | 2002-01-04 | 2005-05-04 | 英特尔公司 | Flash memory access using a plurality of command cycles |
| US20080060072A1 (en) * | 2006-09-01 | 2008-03-06 | Fuji Xerox Co., Ltd. | Information processing system, information processing method, information processing program, computer readable medium and computer data signal |
| US20100217849A1 (en) * | 2009-02-26 | 2010-08-26 | Oracle International Corporation | Automatic Administration of UNIX Commands |
| CN102012791A (en) * | 2010-10-15 | 2011-04-13 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
| US20120173792A1 (en) * | 2010-12-30 | 2012-07-05 | Lassa Paul A | Controller and Method for Performing Background Operations |
| RU2454739C1 (en) * | 2011-01-12 | 2012-06-27 | Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации | Method of programming nand flash memory ic and apparatus for realising said method |
| US20140089567A1 (en) * | 2012-09-24 | 2014-03-27 | Violin Memory Inc | Hardware integrity verification |
| CN102890477A (en) * | 2012-09-26 | 2013-01-23 | 西安交通大学 | On-line active dynamic balance measurement and control device and on-line active dynamic balance measurement and control method |
| CN105830040A (en) * | 2013-12-20 | 2016-08-03 | 拉姆伯斯公司 | A memory appliance for accessing memory |
| WO2016039774A1 (en) * | 2014-09-12 | 2016-03-17 | Intel Corporation | Facilitating dynamic parallel scheduling of command packets at graphics processing units on computing devices |
| CN106687927A (en) * | 2014-09-12 | 2017-05-17 | 英特尔公司 | Facilitating dynamic parallel scheduling of command packets at graphics processing units on computing devices |
| CN106469026A (en) * | 2015-08-14 | 2017-03-01 | 马维尔国际贸易有限公司 | Flexible interface for nand flash memory |
| CN105788636A (en) * | 2016-04-05 | 2016-07-20 | 山东华芯半导体有限公司 | EMMC controller based on parallel multichannel structure |
Non-Patent Citations (4)
| Title |
|---|
| LEO FREITAS .ETC: "POSIX and the Verification Grand Challenge：A Roadmap", 《13TH IEEE INTERNATIONAL CONFERENCE ON ENGINEERING OF COMPLEX COMPUTER SYSTEMS（ICECCS 2008）》 * |
| LEO FREITAS .ETC: "POSIX and the Verification Grand Challenge：A Roadmap", 《13TH IEEE INTERNATIONAL CONFERENCE ON ENGINEERING OF COMPLEX COMPUTER SYSTEMS（ICECCS 2008）》, 31 March 2008 (2008-03-31), pages 1 - 10 * |
| 秦锐: "专用型SOC片内Flash读写控制系统的设计与实现", 《中国优秀硕士学位论文全文数据库》 * |
| 秦锐: "专用型SOC片内Flash读写控制系统的设计与实现", 《中国优秀硕士学位论文全文数据库》, 31 January 2018 (2018-01-31), pages 135 - 254 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147373A (en) * | 2019-05-23 | 2019-08-20 | 泰康保险集团股份有限公司 | Data processing method, device and electronic equipment |
| CN110147373B (en) * | 2019-05-23 | 2021-06-22 | 泰康保险集团股份有限公司 | Data processing method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109324828B (en) | 2023-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106940428B (en) | Chip verification method, device and system | |
| US20140108403A1 (en) | License Reconciliation with Multiple License Types and Restrictions | |
| CN102760176B (en) | Hardware transaction level simulation method, engine and system | |
| CN106325758B (en) | A kind of queue storage space management method and device | |
| US20220147676A1 (en) | Integrated circuit simulation and design method and system thereof | |
| CN108984393A (en) | A kind of unit testing code automatic generation method and device | |
| CN105074656A (en) | Methods and apparatus to manage concurrent predicate expressions | |
| CN110457033A (en) | Device and method for generating dynamic trace data on GPU | |
| CN108513658A (en) | A kind of transaction methods and device | |
| US8886588B2 (en) | Structured requirement generation and assessment | |
| CN111367792A (en) | Test method, test device, storage medium and electronic equipment | |
| CN115168130A (en) | Chip testing method and device, electronic equipment and storage medium | |
| US10430215B1 (en) | Method and system to transfer data between hardware emulator and host workstation | |
| CN109324828A (en) | A method of it orders realization flash memory more in verification platform and executes parallel | |
| CN110134504A (en) | A kind of operating system demand layer Formal Modeling and device based on finite state machine | |
| CN113919158A (en) | Simulation method and device for flight control panel and storage medium | |
| US10073938B2 (en) | Integrated circuit design verification | |
| US7945418B2 (en) | Stream based stimulus definition and delivery via interworking | |
| CN100358302C (en) | Method for testing network element interface by state apparatus | |
| CN113779918A (en) | SoC simulation method, device, computing equipment and computer storage medium | |
| US8707306B1 (en) | Implementing user-selectable concurrent access protection mechanism in a multi-tasking modeling environment | |
| CN103345377A (en) | FIFO storer control method and device | |
| US10386909B1 (en) | Method and system to mitigate large power load steps due to intermittent execution in a computation system | |
| Helmstetter et al. | Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications | |
| CN110399296A (en) | The method, system and medium of interactive interface between test client and server-side |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |