CN109324256B - Wire alignment device - Google Patents
Wire alignment device Download PDFInfo
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- CN109324256B CN109324256B CN201811536288.9A CN201811536288A CN109324256B CN 109324256 B CN109324256 B CN 109324256B CN 201811536288 A CN201811536288 A CN 201811536288A CN 109324256 B CN109324256 B CN 109324256B
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- 238000012360 testing method Methods 0.000 claims abstract description 34
- 238000001514 detection method Methods 0.000 claims abstract description 9
- 230000000087 stabilizing effect Effects 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000012937 correction Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/58—Testing of lines, cables or conductors
- G01R31/60—Identification of wires in a multicore cable
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The invention discloses a pair of line testers, which consists of a main tester and an auxiliary tester, wherein during testing, the line can be quickly wired by selecting the on-off state of a power supply, the on-off state of an independent power supply can be correspondingly controlled according to the number of cable cores of a cable to be tested, if the number of the cable cores is small, the independent power supply with less number can be selectively started to supply power for the main tester for line detection, the rest of the main testers are in a power-off state, and if the number of the cable cores is large, the independent power supply with more number can be correspondingly started to supply power for the main tester. The line detection result can be displayed through the main display circuit and the auxiliary display circuit. The pair of wires can meet the task of cable pair with more wire cores and the task of cable pair with fewer wire cores, and meet the requirements of various types of cables.
Description
Technical Field
The invention relates to the field of cable core testing, in particular to a pair of wire cutters.
Background
The cables are mainly used for power transmission, electric communication and winding of coils or windings for finger-wound electric devices, and the cables may be classified into power cables, signal cables, control cables, compensation cables and shielding cables according to different performances. In the power system, a cable for disclosing a power source to electric equipment is called a primary cable, a cable for signal transmission and signal feedback is called a secondary cable, and for example, a motor operation column control cable, a metering, protection and electric communication cable is called a secondary cable.
In an electric power system, it is particularly important to perform core alignment on a cable before performing cable wiring, and the core alignment is mainly used for preventing secondary circuit faults. Whether the cable core is quickly and accurately aligned or not greatly influences the progress and quality of the whole engineering. At present, although there are cable line aligning devices for aligning the wire cores of the cables, these line aligning devices all adopt a unified power supply to supply power, but the number of the line aligning interfaces of these cable line aligning devices is too small to meet the line aligning task of the cables with a large number of wire cores, or the number of the line aligning interfaces is large, when the cables with a small number of wire cores are aligned, the remaining interfaces of the cable line aligning devices are idle, which causes resource waste and power loss. Therefore, the cable alignment device existing in the market at present has poor flexibility and can not well meet the alignment requirements of various types of cables.
Disclosure of Invention
The invention aims to disclose a wire alignment device, which has higher flexibility, can meet the wire alignment task of cables with more wire cores, can also meet the wire alignment task of cables with fewer wire cores, and meets the alignment requirements of various types of cables.
In order to achieve the above purpose, the embodiment of the invention discloses the following technical scheme:
The embodiment of the invention discloses a pair of wires, which comprises:
a main tester and an auxiliary tester for performing an alignment test;
The main tester at least comprises two groups of pair line circuits and output terminals connected with the output ends of the pair line circuits, and all the output terminals are numbered in sequence;
Each of the pair of line circuits includes: a decimal counter circuit;
an inverting circuit connected with the CLK pin of the decimal counter circuit and used for generating counting pulses;
The power supply is connected with a power input pin of the decimal counter circuit and is used for independently supplying power to the decimal counter circuit;
a main display circuit connected to an output pin of the decimal counter circuit;
The secondary tester includes: the number of the input terminals is the same as that of the output terminals of the main tester, and the auxiliary display circuits are connected with the input terminals, and all the input terminals are also numbered in sequence corresponding to the output terminals;
when the alignment test is performed, the main display circuit and the auxiliary display circuit are both used for displaying an alignment test result.
Optionally, the main display circuit includes:
And the main diode groups have the same number as the output pins of the decimal counter circuit, each main diode group comprises a main light-emitting diode, the positive electrode of the main light-emitting diode is connected with the output pin of the decimal counter circuit corresponding to each main light-emitting diode, the negative electrode of the main light-emitting diode is connected with the main loop diode corresponding to each output pin of the decimal counter circuit, and the negative electrode of the main light-emitting diode and the positive electrode of the main loop diode are connected with the corresponding output terminal.
Optionally, the auxiliary display circuit includes:
Each auxiliary diode group is connected with each input terminal, each auxiliary diode group comprises an auxiliary light-emitting diode, the anode of each auxiliary light-emitting diode is connected with the corresponding input terminal, the cathode of each auxiliary loop diode is connected with the corresponding input terminal, and the cathode of each auxiliary light-emitting diode is connected with the anode of each auxiliary loop diode; and the cathodes of all the auxiliary light emitting diodes are connected with the anodes of all the auxiliary loop diodes.
Optionally, the decimal counter circuit is specifically a CD4017 chip.
Optionally, the main tester includes two sets of the pair of line circuits, eight output pins of a CD4017 chip in each set of the pair of line circuits are correspondingly connected with eight main diode groups, and output ends of sixteen main diode groups are connected with respective corresponding output terminals;
All the output terminals are numbered first to sixteenth in sequence;
correspondingly, the auxiliary tester comprises sixteen input terminals and sixteen auxiliary diode groups correspondingly connected with the sixteen input terminals;
All of the input terminals are numbered first to sixteenth in sequence corresponding to all of the output terminals.
Optionally, the inverting circuit includes: a first CD4069 inverter and a second CD4069 inverter;
The first end of the first CD4069 inverter is connected with the first end of the capacitor and the CLK pin respectively, the second end of the capacitor is connected with the first end of the first resistor and the first end of the second resistor respectively, the second end of the first resistor is connected with the second end of the first CD4069 inverter and the first end of the second CD4069 inverter respectively, and the second end of the second CD4069 inverter is connected with the second end of the second resistor.
Optionally, the main tester further includes an RJ11 interface, and correspondingly, the auxiliary tester also includes the RJ11 interface;
and the main tester and the auxiliary tester conduct alignment test on the data wire corresponding to the RJ11 interface through the RJ11 interface.
Optionally, the main tester further includes an RJ45 interface, and correspondingly, the auxiliary tester also includes the RJ45 interface;
And the main tester and the auxiliary tester conduct alignment test on the data line corresponding to the RJ45 interface through the RJ45 interface.
Optionally, the pair of wires further includes:
One end of the current limiting protection device is connected with a power input pin of the decimal counter circuit, and the other end of the current limiting protection device is connected with the power supply and is used for performing current limiting protection on the decimal counter circuit.
Optionally, the pair of wires further includes:
One end of the voltage stabilizing circuit is connected with the current limiting protection device, and the other end of the voltage stabilizing circuit is connected with a power input pin of the decimal counter circuit and is used for stabilizing the output voltage of the power supply.
It can be seen that the embodiment of the invention discloses a pair of line testers, which is used for performing a pair of line test, wherein the main tester at least comprises two groups of line circuits and output terminals connected with the output ends of the line circuits, all the output terminals are numbered sequentially, a decimal counter circuit in each pair of line circuits is powered by independent power supply voltage, the auxiliary tester comprises input terminals, the number of which is the same as that of the output terminals of the main tester, and all the input terminals also correspond to the output terminals in sequence. When the main tester and the auxiliary tester perform the alignment test, the power supply for the main tester can be correspondingly controlled to be on-off according to the number of the wire cores, if the number of the wire cores is small, the independent power supplies with less numbers can be selected to be turned on for supplying power for the main tester to perform the alignment test, the rest main testers are in a power-off state, and if the number of the wire cores is large, the independent power supplies with more numbers can be correspondingly turned on for supplying power for the main tester to perform the alignment test. The alignment detection results of the main tester and the auxiliary tester during alignment detection can be displayed through the main display circuit and the auxiliary display circuit. Therefore, by independently controlling each group of the wire circuits through the independent power supply, not only can the wire task of more wires of the wire cores be met, but also the wire task of fewer wires of the wire cores be met, and the wire requirements of various types of cables are met.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a pair of wire guides according to a first embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a specific implementation manner of a wire harness according to an embodiment of the present invention;
fig. 3 is a schematic view of an appearance structure of a pair of wire guides according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of a pair of wire guides according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention discloses a wire alignment device, which has higher flexibility, can meet the wire alignment task of cables with more wire cores, can also meet the wire alignment task of cables with fewer wire cores, and meets the alignment requirements of various types of cables.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pair of wires disclosed in a first embodiment of the present invention, in fig. 1, a pair of wires with a pair of wire test targets being a cable a is taken as an example to describe the pair of wires disclosed in the embodiment of the present invention, and in fig. 1, only two pairs of wire circuits are taken as an example, but the pair of wire circuits are not represented. The main tester 1 comprises at least two groups of the pair line circuits 10 and output terminals 20 connected with the output ends of the pair line circuits 10, all the output terminals 20 are numbered sequentially, each pair line circuit 10 comprises a decimal counter circuit 101, an inverter circuit 102 connected with a CLK pin of the decimal counter circuit 101 and used for generating counting pulses by a main display circuit 104, a power supply 103 connected with a power supply input pin of the decimal counter circuit 101 and used for independently supplying power to the decimal counter circuit 101, a main display circuit 104 connected with the output pins of the decimal counter circuit 101, the auxiliary tester 2 comprises input terminals 30 which are the same as the number of the output terminals 20 of the main tester 1 and auxiliary display circuits 201 connected with the input terminals 30, all the input terminals 30 are numbered sequentially corresponding to the output terminals 20, and the main display circuit 104 and the auxiliary display circuits 201 are used for displaying the pair line test results when the pair line test is performed.
Specifically, in this embodiment, the main tester 1 and the auxiliary tester 2 should be used together, the decimal counter circuit 101 in the pair circuit 10 may be a CD4017 chip, and the main display circuit 104 may be an LCD display screen or a diode group composed of light emitting diodes.
Taking the example that the main tester 1 in fig. 1 includes two pairs of pair circuits 10, eight main diode groups are correspondingly connected to eight output ends of the CD4017 chips in each pair circuit 10, the output ends of the sixteen main diode groups are connected to the corresponding output terminals 20, the numbers of the output terminals 20 are first to sixteenth, the corresponding auxiliary tester 2 includes sixteen input terminals 30 and sixteen auxiliary diode groups correspondingly connected to the sixteen input terminals 30, and all the input terminals 30 are sequentially numbered first to sixteenth corresponding to all the output terminals 20.
First: the main display circuit 104 in the main tester 1 is described below:
The main display circuit 104 includes main diode groups having the same number of output pins as the decimal counter circuit 101, each of the main diode groups includes a main light emitting diode having an anode connected to the output pin of the decimal counter circuit 101, a main loop diode having a cathode connected to the output pin of the decimal counter circuit 101, and both the cathode of the main light emitting diode and the anode of the main loop diode are connected to the respective corresponding output terminals 20.
If the flashing sequence of each main light emitting diode group in the main tester 1 is that the flashing sequence is from top to bottom in sequence with the serial number of the output terminal, the fact that the wire cores for testing the wires are not connected in a staggered manner is indicated, and otherwise, the wire cores for testing the wires are not connected in a staggered manner.
Second,: the following description is made of the sub display circuit 201 in the sub tester 2:
The auxiliary display circuit 201 includes auxiliary diode groups connected to the respective input terminals 30, each of the auxiliary diode groups including auxiliary light emitting diodes having anodes connected to the respective corresponding input terminals 30, auxiliary loop diodes having cathodes connected to the respective corresponding input terminals 30, cathodes of the auxiliary light emitting diodes being connected to anodes of the auxiliary loop diodes, cathodes of all the auxiliary light emitting diodes being connected to anodes of all the auxiliary loop diodes.
If the flashing sequence of each auxiliary light emitting diode group in the auxiliary tester 2 is that the input terminal numbers are sequentially flashing from top to bottom, that is, the flashing sequence of each main light emitting diode group in the main tester 1 is corresponding to the flashing sequence, the wire cores of the wire test are not connected in a staggered manner, otherwise, the wire cores are not connected in a staggered manner.
Third,: the following description is made of the inverter circuit 102 in the main tester 1, the inverter circuit 102 including a first CD4069 inverter and a second CD4069 inverter;
The first end of the first CD4069 inverter is respectively connected with the first end of the capacitor and the CLK pin, the second end of the capacitor is respectively connected with the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is respectively connected with the second end of the first CD4069 inverter and the first end of the second CD4069 inverter, and the second end of the second CD4069 inverter is connected with the second end of the resistor.
Specifically, the CD4069 inverter is applied as an amplifier in the embodiment of the present invention, and is combined with a capacitor, a first resistor and a second resistor to form a resistor-capacitor oscillator, so as to generate counting pulses required by the decimal timer circuit 101, and the oscillation period is about 1 second. When the CLK pin of the decimal timer circuit 101 is low, the decimal timer circuit is allowed to count, otherwise, the counting is stopped.
The technical solution disclosed in the embodiment of the present invention is fully described below by taking the decimal counter circuit 101 as a CD4017 chip and the structures of the main display circuit 104 and the inverter circuit 102 described in the above embodiment as examples, where the CD4017 chip is a chip containing 8 output pins, the number of the corresponding output terminals 20 is 16, and the diode groups in the main display circuit 104 and the auxiliary display circuit 201 are also 16 groups correspondingly.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a specific implementation manner of a pair of pair-line circuits 10 disclosed in the embodiment of the present invention, in which fig. 2 includes two pairs of pair-line circuits 10, each pair of pair-line circuits 10 includes an independent power supply circuit, the independent power supply circuit includes a power supply VCC for indicating a light emitting diode that the independent power supply VCC normally operates, the power supply VCC may be E1 and E2 with an operating voltage of 9V, and in the following, a pair of pair-line circuits are illustrated as an example, and in the other pair of pair-line circuits, the pair of pair-line circuits may be referred to as the pair of pair-line circuits: the CD4017 chips in each pair of pair circuits (in the embodiment of the present invention, the CD4017 chip in the first pair of pair circuits is denoted as U1, and the CD4017 chip in the second pair of pair circuits is denoted as U2), each of the CD4017 chips U1 and U2 includes a CLK pin (14 pins), a power input pin CLKBN pin (13 pins) and a reset pin RES (15 pins) for connecting 8 output pins (corresponding to D00-D07 pins in fig. 2) of the main diode group, and the remaining two spare pins (connecting D08 pins and D09 pins of the reset pin RES, corresponding to serial numbers of the pins and corresponding to fig. 2) and a C/OUT pin. The CLK pin of the CD4017 chip is connected to the inverter circuit 102, the inverter circuit 102 includes a CD4069 inverter U1-a, a CD4069 inverter U1-B, the first resistor R2 and the second resistor R3 and the capacitor C1, eight output pins (D00-D07) of the CD4017 chip U1 are respectively and correspondingly connected to eight main diode groups, the cathode of the main light emitting diode in the main diode groups is connected to the anode of the main loop diode and connected to the corresponding output terminal, the eight output terminals are sequentially and sequentially arranged to 1-8, the eight output pins of the CD4017 chip U2 are also correspondingly connected to eight main diode groups, and the eight output terminals correspondingly connected to the eight main diode groups connected to the output terminal of the CD4017 chip U2 are sequentially and sequentially arranged to 9-16, so the total number of output terminals corresponding to the main tester 1 is 16.
For the auxiliary tester 2, the number of the input terminals 30 of the auxiliary tester 2 is correspondingly the same as that of the output terminals 20 of the main tester 1, and the input terminals 30 are also sequentially ordered by 1-16, and 16 diode groups are correspondingly connected to the input terminals 30 of the auxiliary tester 2.
The working principle of fig. 2 disclosed in the embodiment of the present invention will be described with reference to fig. 3, fig. 3 is a schematic view of an appearance structure of a pair of wires disclosed in the embodiment of the present invention, and two power switch keys 31 in fig. 3 are used as schematic views, and if more groups of wires are included, the power switch keys 31 should also be set, and a power indicator 34 is correspondingly set. The pair of wires includes an output terminal 20 and an input terminal 30 and an RJ11 interface and an RJ45 interface. The RJ11 interface and the RJ45 interface on the main tester 1 and the auxiliary tester 2 are used for testing telephone lines and network lines respectively. The main tester 1 and the sub tester 2 include a main indicator lamp 32 and a sub indicator lamp 33 (corresponding to each diode group in fig. 2) for displaying the result of the alignment test, the indicator lamps being sequentially arranged in line sequence numbers from top to bottom. The operation principle of fig. 2 will be described by taking an example of a cable alignment test by the output terminal 20 and the input terminal 30.
Firstly, it should be noted that, if the number of the wire cores to be tested for the wire at this time is 8 cores or less, only one group of wire cores may be turned on, that is, one power supply is turned on to supply power to the corresponding wire cores, so as to achieve the purpose of saving battery power, if the number of the wire cores to be tested for the wire at this time is 8 cores or less than 16 cores, both groups of wire cores may be turned on, that is, two power supplies are turned on to supply power to the corresponding wire cores respectively, and if the number of the wire cores to be tested for the wire at this time exceeds 16 cores, since the main tester 1 disclosed in the embodiment of the invention includes at least two groups of wire cores, the wire cores may also be tested for the wire cores by turning on other groups of wire cores. The working principle of fig. 2 is described below by taking the number of cores as 16 as an example:
Description of the operation of the wire bonder with respect to fig. 3: on the one hand, two groups of power switches of the line coupler can be started simultaneously, the electric cores at two ends of the cable to be tested are fixed at the output terminals of the main tester 1 and the auxiliary tester 2 through the lead clamps, and when the test is started, if the indicator lamps of the main tester 1 and the auxiliary tester 2 flash sequentially from top to bottom, the line sequence of the cable is correct at the moment, and the line sequence of the cable is marked according to the numbers of the terminals on the main tester 1 and the auxiliary tester 2. If the indicator lamps of the main tester 1 and the auxiliary tester 2 do not flash sequentially from top to bottom, the staggered connection of the wire cores of the cable is described, when the wire core error correction is performed, a group of wire cores can be closed first, the wire cores which are connected in a staggered manner are searched sequentially from the group of wire cores, the efficiency of the wire core error correction is improved, and the wire core error correction is performed quickly. On the other hand, the power switch of a pair of line aligning devices can be started successively to detect the line cores of the cables connected with the pair of line aligning devices, if the line cores of the cables connected with the opened first pair of line aligning devices are staggered, the indicator lamps of the main tester 1 and the auxiliary tester 2 are not sequentially flashed, the staggered cable core can be rapidly determined, then the second pair of line aligning devices is started to detect the line cores of the cables in the same operation, and the line aligning detection efficiency is high.
When the network cable and the telephone cable are tested by the RJ11 interface and the RJ45 interface, as the wire cores of the telephone cable and the network cable are generally 8 cores or less, only a group of wire-aligning circuits are needed to be started, then the telephone cable or the network cable is inserted into the RJ11 interface or the RJ45 interface corresponding to the main tester 1 and the auxiliary tester 2, if the indicator lamps of the pair of wire-aligning circuits flash sequentially from top to bottom, the wire cores of the telephone cable or the network cable are not connected in a staggered way, namely the wire-aligning test is successful; if the indicator lights of the pair of wires do not flash in sequence, the staggered connection of the wire cores of the telephone wires or the network wires is indicated, and the wire cores of the telephone wires or the network wires are continuously adjusted until the indicator lights of the pair of wires flash in sequence from top to bottom.
Next, description is made of the operation principle of fig. 2:
Firstly, when each pair of line circuits is in a working state, when a first pulse is added to a CLK pin of a CD4017 chip, only D00 outputs a high level from a D00-D07 pin of the CD4017 chip, when a second pulse is added, only D01 outputs a high level from a D00-D07 pin of the CD4017 chip, and so on, when a tenth pulse is added, only D009 outputs a high level, and an output end CO/OUT pin generates a positive pulse, so that one round of counting is completed. When the inverting circuit 102 inputs pulses continuously to the CLK pin of the CD4017 chip, the main LED group connected to the CD4017 sequentially emits light. If the cable includes 16 cores, the 16 cores are respectively connected with the corresponding output terminal 20 and the input terminal 30, and if the 16 cores are connected correctly, when a count pulse occurs once, the current direction should be the main light emitting diode group-output terminal 1 correspondingly connected to the D00 pin of the CD4017 chip of the main tester 1, the cable core 1, and the auxiliary light emitting diode group correspondingly connected to the input terminal 1 of the auxiliary tester 2. And by analogy, the 16 main LEDs and the auxiliary LEDs flash from top to bottom according to line sequence numbers. If the 16 wire cores have staggered wire cores, the 16 main LEDs and the auxiliary LEDs will not flash in sequence at this time.
It can be seen that the embodiment of the invention discloses a pair of line testers, which is used for performing a pair of line test, wherein the main tester at least comprises two groups of line circuits and output terminals connected with the output ends of the line circuits, all the output terminals are numbered sequentially, a decimal counter circuit in each pair of line circuits is powered by independent power supply voltage, the auxiliary tester comprises input terminals, the number of which is the same as that of the output terminals of the main tester, and all the input terminals also correspond to the output terminals in sequence. When the main tester and the auxiliary tester perform the alignment test, the power supply for the main tester can be correspondingly controlled to be on-off according to the number of the wire cores, if the number of the wire cores is small, the independent power supplies with less numbers can be selected to be turned on for supplying power for the main tester to perform the alignment test, the rest main testers are in a power-off state, and if the number of the wire cores is large, the independent power supplies with more numbers can be correspondingly turned on for supplying power for the main tester to perform the alignment test. The alignment detection results of the main tester and the auxiliary tester during alignment detection can be displayed through the main display circuit and the auxiliary display circuit. Therefore, by independently controlling each group of the wire circuits through the independent power supply, not only can the wire task of more wires of the wire cores be met, but also the wire task of fewer wires of the wire cores be met, and the wire requirements of various types of cables are met.
In addition, since the harmonic wave in the circuit affects the output voltage of the power supply to be easily fluctuated, when the output voltage is fluctuated, the output voltage of the power supply will be excessively large, and damage will be caused to the decimal counter circuit 101, in order to stabilize the output voltage of the power supply and protect the decimal counter circuit 101, the invention discloses a second embodiment, please refer to fig. 4, fig. 4 is a schematic diagram illustrating the structure of a pair of line counters disclosed in the second embodiment of the invention, and on the basis of the first embodiment, the pair of line counters further comprises:
one end is connected with a power input pin of the decimal counter circuit 101, the other end is connected with a voltage stabilizing circuit 106 connected with one end of a current limiting protection device 105, and the other end of the current limiting protection device 105 is connected with a power supply 103 and used for carrying out current limiting protection on the decimal counter circuit 101 and stabilizing the output voltage of the power supply.
Specifically, the current limiting protection device 105 in this embodiment may be a fuse, a relay, etc., the voltage stabilizing circuit 106 may be a voltage stabilizing chip in the prior art, and the voltage stabilizing circuit 106 and the current limiting protection device 105 are not improvements of the embodiment of the present invention, so that the current limiting protection devices 105 of the voltage stabilizing circuit 106 are not described again.
The above describes in detail a pair of wire guides disclosed in the present application. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Claims (9)
1. A wire alignment device, comprising: a main tester and an auxiliary tester for performing an alignment test;
The main tester at least comprises two groups of pair line circuits and output terminals connected with the output ends of the pair line circuits, and all the output terminals are numbered in sequence;
each pair of line circuits includes: a decimal counter circuit;
an inverting circuit connected with the CLK pin of the decimal counter circuit and used for generating counting pulses;
The power supply is connected with a power input pin of the decimal counter circuit and is used for independently supplying power to the decimal counter circuit;
a main display circuit connected to an output pin of the decimal counter circuit;
The secondary tester includes: the number of the input terminals is the same as that of the output terminals of the main tester, and the auxiliary display circuits are connected with the input terminals, and all the input terminals are also numbered in sequence corresponding to the output terminals;
When the alignment test is performed, the main display circuit and the auxiliary display circuit are both used for displaying an alignment test result;
the main tester comprises two groups of the pair line circuits, eight output pins of a CD4017 chip in each group of the pair line circuits are correspondingly connected with eight main diode groups, and the output ends of sixteen main diode groups are connected with corresponding output terminals;
All the output terminals are numbered first to sixteenth in sequence;
correspondingly, the auxiliary tester comprises sixteen input terminals and sixteen auxiliary diode groups correspondingly connected with the sixteen input terminals;
All the input terminals are numbered first to sixteenth in sequence corresponding to all the output terminals;
If the number of the wire cores required to be subjected to the wire alignment test is 8 cores or less than 8 cores, only one group of wire alignment circuits are started, and if the number of the wire cores required to be subjected to the wire alignment test is 8 cores or less than 16 cores, both groups of wire alignment circuits are started;
when the number of the wire cores is 16, the process of testing the wire cores comprises the following steps:
simultaneously starting two groups of power switches of the wire alignment device, if the wire cores of the cable are connected in a staggered way, closing a group of wire alignment circuits, and sequentially searching the wire cores which are connected in a staggered way from the group of wire alignment circuits;
or a power switch of a group of line aligning devices is started in advance to perform line alignment detection, if the line cores of the cables connected with the started first group of line aligning devices are staggered, indicator lamps of the main tester and the auxiliary tester are not sequentially flashed, staggered cable line cores are determined, and then a second group of line aligning devices are started to perform cable cell line alignment detection in the same operation.
2. The pair of wires of claim 1, wherein the main display circuit comprises:
And the main diode groups have the same number as the output pins of the decimal counter circuit, each main diode group comprises a main light-emitting diode, the positive electrode of the main light-emitting diode is connected with the output pin of the decimal counter circuit corresponding to each main light-emitting diode, the negative electrode of the main light-emitting diode is connected with the main loop diode corresponding to each output pin of the decimal counter circuit, and the negative electrode of the main light-emitting diode and the positive electrode of the main loop diode are connected with the corresponding output terminal.
3. The pair of wires of claim 2, wherein the secondary display circuit comprises:
Each auxiliary diode group is connected with each input terminal, each auxiliary diode group comprises an auxiliary light-emitting diode, the anode of each auxiliary light-emitting diode is connected with the corresponding input terminal, the cathode of each auxiliary loop diode is connected with the corresponding input terminal, and the cathode of each auxiliary light-emitting diode is connected with the anode of each auxiliary loop diode; and the cathodes of all the auxiliary light emitting diodes are connected with the anodes of all the auxiliary loop diodes.
4. A pair of wires according to claim 3, wherein the decimal counter circuit is embodied as a CD4017 chip.
5. The pair of wires of claim 1, wherein the inverting circuit comprises: a first CD4069 inverter and a second CD4069 inverter;
The first end of the first CD4069 inverter is connected with the first end of the capacitor and the CLK pin respectively, the second end of the capacitor is connected with the first end of the first resistor and the first end of the second resistor respectively, the second end of the first resistor is connected with the second end of the first CD4069 inverter and the first end of the second CD4069 inverter respectively, and the second end of the second CD4069 inverter is connected with the second end of the second resistor.
6. The pair of wires of any of claims 1-5, wherein the primary tester further comprises an RJ11 interface, and the secondary tester correspondingly also comprises the RJ11 interface;
and the main tester and the auxiliary tester conduct alignment test on the data wire corresponding to the RJ11 interface through the RJ11 interface.
7. The pair of wires of any of claims 1-5, wherein the primary tester further comprises an RJ45 interface, and the secondary tester also comprises the RJ45 interface, respectively;
And the main tester and the auxiliary tester conduct alignment test on the data line corresponding to the RJ45 interface through the RJ45 interface.
8. The pair of wires of claim 1, wherein the pair of wires circuit further comprises:
One end of the current limiting protection device is connected with a power input pin of the decimal counter circuit, and the other end of the current limiting protection device is connected with the power supply and is used for performing current limiting protection on the decimal counter circuit.
9. The pair of wires of claim 8, wherein the pair of wires circuit further comprises:
One end of the voltage stabilizing circuit is connected with the current limiting protection device, and the other end of the voltage stabilizing circuit is connected with a power input pin of the decimal counter circuit and is used for stabilizing the output voltage of the power supply.
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| CN201811536288.9A CN109324256B (en) | 2018-12-14 | 2018-12-14 | Wire alignment device |
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| CN201811536288.9A CN109324256B (en) | 2018-12-14 | 2018-12-14 | Wire alignment device |
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| CN109324256A CN109324256A (en) | 2019-02-12 |
| CN109324256B true CN109324256B (en) | 2024-05-21 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111103556B (en) * | 2019-11-22 | 2022-02-01 | 国网浙江省电力有限公司丽水供电公司 | Wire alignment device convenient to use |
| CN114035121A (en) * | 2021-10-28 | 2022-02-11 | 保定天威线材制造有限公司 | Wire searching tester in equipment line and use method |
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| CN109324256A (en) | 2019-02-12 |
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