CN109302155A - The feed forward type amplitude linearity method and circuit of deep AB power-like amplifier - Google Patents
The feed forward type amplitude linearity method and circuit of deep AB power-like amplifier Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
- H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
- H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
Present invention discloses the feed forward type amplitude linearity methods and circuit of a kind of depth AB power-like amplifier, described method includes following steps: input signal envelope detector output signal is converted to CMOS radio-frequency power amplifier PA bias voltage, bias voltage is allowed to reduce as input signal amplitude increases, gain raising caused by CMOS radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region is offset to reduce bring gain reduction with CMOS radio-frequency power amplifier PA bias voltage, reaches linearisation amplitude gain.The linearisation that the amplitude gain of lower PA is biased to deep AB class may be implemented in the feed forward type amplitude linearity method of PA bias voltage automatic circuit proposed by the present invention, depth AB power-like amplifier, achievees the purpose that reduction power consumption while keeping PA linear.
Description
Technical field
The invention belongs to technical field of integrated circuits, are related to a kind of CMOS radio-frequency power amplifier more particularly to a kind of depth
The feed forward type amplitude linearity method of AB power-like amplifier.
Background technique
CMOS radio-frequency power amplifier (PA) have the advantages that can on piece it is integrated, but due to the limitation of device performance, design
The high performance PA of high efficiency is also a huge challenge out.OFDM technology is due to its channel utilization height, the advantages such as anti-interference
It is largely used in the agreements such as WLAN, LTE, but lacking by OFDM itself intrinsic peak value average power ratio (PAPR)
Point requires PA to have the outstanding linearity, while average emitted power being needed to fill on the basis of peak transmitted power in transmitting terminal
Divide and retract, this will be greatly reduced the emission effciency of PA.
A kind of mode for improving rollback emission effciency is that PA is biased in deep AB class state, i.e., the PA under peak power output
The angle of flow close to 180 °.It being biased compared with A class, this bias mode can substantially reduce the DC power under rollback power, but
The linearity for also resulting in PA becomes very poor.It is the relationship of the output electric current and input voltage of PA power tube as shown in Fig. 1 (a),
Export electric current IoutWith input voltage VinApproximation meets
Wherein VthFor the threshold voltage of power tube, K is related to the breadth length ratio of technique and power tube.
Vin-IoutGain is
When input signal is the sinusoidal signal that voltage amplitude is A, bias voltage VbWhen, input signal expression formula is
Vin=Asin (ω0t)+Vb
Exporting electric current is
Select bias voltage VbIt is defeated as input sinusoidal voltage amplitude is gradually increased in Fig. 1 (b) when close to threshold voltage
Electric current first works in V outin-IoutThe lesser region of gain, progresses into Vin-IoutThe biggish region of gain, signal also gradually lose
Very, as shown in Fig. 1 (c).
Component, that is, fundamental component identical with frequency input signal is the output of PA real concern in output distorted signal.Figure
2 show that for PA from the fundamental frequency signal gain (AM-AM) for being input to output, dotted line is not under the sinusoidal voltage input of different amplitudes
Output voltage is considered by the gain of supply voltage clipping, and solid line considers the clipping effect of supply voltage.Work as input signal amplitude
Change from small to big, fundamental frequency signal gain increases 3dB or more, this can introduce very serious non-linear.Will use be biased in deep AB class
The PA of state, it is necessary to solve this nonlinear problem.
Digital pre-distortion linearization technology
Referring to Fig. 3, the mode that Fig. 3 discloses a kind of solution is using digital pre-distortion technology (DPD), by data training
The AM-AM distortion shape of PA is obtained, the data to be sent first pass through DPD processing, are equivalent to the inverse function by AM-AM, then lead to
PA is crossed, the output signal not being distorted can be obtained.This method there are the problem of first is that more violent DPD processing can reduce
The utilization rate of DAC dynamic range, second is that when signal bandwidth is wider, when the memory effect of PA has a significant impact, the effect of DPD processing
It will be greatly reduced.
Envelope feedback linearization technique
Referring to Fig. 4, it is the bias voltage for adjusting PA by a feedback control loop that Fig. 4, which discloses another way, by force will
The gain of PA is arranged in fixed value.Such as Fig. 4, the output voltage of PA carries out envelope detected after an attenuator, exports envelope
Signal and input envelope signal compare, and adjustment PA biasing makes to export the fixation multiple that envelope remains input envelope, thus
Inhibit the non-linear of AM-AM curve.The problem of this mode be the stability of loop it is difficult to ensure that, and the bandwidth that can be realized has
Limit.Signal bandwidth is wider, and loop bandwidth requirement is wider, and design difficulty is bigger, and stability is also more difficult to be guaranteed.
In view of this, nowadays there is an urgent need to design a kind of new PA bias voltage adjustment mode, to overcome existing adjustment
Drawbacks described above existing for mode.
Summary of the invention
The technical problems to be solved by the present invention are: providing a kind of PA bias voltage automatic circuit, it can be achieved that depth
The linearisation of the amplitude gain of PA under the biasing of AB class achievees the purpose that reduce power consumption while keeping PA linear.
The present invention provides a kind of feed forward type amplitude linearity method of depth AB power-like amplifier, it can be achieved that inclined to deep AB class
The linearisation of the amplitude gain of PA under setting achievees the purpose that reduce power consumption while keeping PA linear.
The present invention provides a kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, it can be achieved that inclined to deep AB class
The linearisation of the amplitude gain of PA under setting achievees the purpose that reduce power consumption while keeping PA linear.
In order to solve the above technical problems, the present invention adopts the following technical scheme:
A kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, the feed forward type amplitude linearity circuit packet
It includes:
Bias-voltage generating circuit subtracts the electricity comprising envelope information of envelope detected circuit output from a fixed current
Stream is then converted into bias voltage to generate the bias current with input signal amplitude negative correlation；So as to use bias voltage
It reduces bring CMOS radio-frequency power amplifier PA gain reduction and offsets CMOS radio-frequency power amplifier PA transistor from subthreshold value
Gain increases caused by area enters saturation region.
As one embodiment of the present invention, the bias-voltage generating circuit includes:
Bias current control circuit, to the export envelope detector and directly proportional electric current of input signal amplitude square
From a fixed current Ib1In subtract, with generate and input signal amplitude negative correlation bias current, thus with the drop of bias voltage
Low bring CMOS radio-frequency power amplifier PA gain reduction offsets CMOS radio-frequency power amplifier PA transistor from sub-threshold region
Gain increases caused by into saturation region, achievees the purpose that linearize amplitude gain；
Bias voltage conversion circuit, to the biased electrical with signal amplitude negative correlation for generating bias current control circuit
Circulation is changed to the bias voltage of CMOS radio-frequency power amplifier PA.
As one embodiment of the present invention, the bias-voltage generating circuit includes: current mirroring circuit, the first electric current
Source Ib1, bias voltage generating circuit；
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope of envelope detected circuit output
Information current mirror image is Ipd, IpdIncrease with the increase of input signal amplitude；
First current source connects current mirroring circuit to generate the first fixed current, the first current source；
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source, and bias voltage generating circuit is used
To receive the data of current mirroring circuit, the first current source, by the powered down current mirror circuit of the first fixed current of the first current source generation
The mirror image I of the envelope information electric current of outputpd, obtained electric current reduces with the increase of input signal amplitude, generates with defeated
Enter the increase of signal amplitude and reduced bias voltage.
As one embodiment of the present invention, the bias-voltage generating circuit further includes the second current source Ib2, biasing
Voltage protection circuit；Biased electrical voltage protection circuit is separately connected the first current source, the second current source, bias voltage generating circuit；
Second current source generates the first current source to generate the second fixed current, biased electrical voltage protection circuit
The second fixed current that first fixed current is generated with the second current source separates, and guarantees the 9th MOS of bias voltage generating circuit
The minimum drain terminal electric current of pipe M9 is greater than 0, to prevent bias voltage to be reduced to 0.
As one embodiment of the present invention, the feed forward type amplitude linearity circuit further includes envelope detected circuit,
To export the electric current for being proportional to input signal envelope square.
As one embodiment of the present invention, the envelope detected circuit includes: that square circuit, high fdrequency component filter out
Circuit, the high fdrequency component filtering circuit connect square circuit；
The input of the square circuit is voltage, is exported to be proportional to the electric current of input voltage square；
The high fdrequency component filtering circuit filters out high fdrequency component to the electric current for exporting the square circuit, obtains
Output electric current is proportional to square of input signal amplitude.
As one embodiment of the present invention, the bias-voltage generating circuit includes: current mirroring circuit, the first electric current
Source Ib1, bias voltage generating circuit；
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope of envelope detected circuit output
Information current mirror image is Ipd, IpdIncrease with the increase of input signal amplitude；
First current source is to generate the first fixed current, the first current source Ib1Connect current mirroring circuit；
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source Ib1, bias voltage generating circuit
To receive the data of current mirroring circuit, the first current source, the first fixed current that the first current source generates is subtracted into current mirror electricity
The mirror image I of the envelope information electric current of road outputpd, obtained electric current reduces with the increase of input signal amplitude, generate with
The increase of input signal amplitude and reduced bias voltage.
As one embodiment of the present invention, the bias-voltage generating circuit further includes the second current source Ib2, biasing
Voltage protection circuit；Biased electrical voltage protection circuit is separately connected the first current source, the second current source Ib2, bias voltage generate electricity
Road；
The second current source Ib2To generate the second fixed current, biased electrical voltage protection circuit generates the first current source
The second fixed current for being generated with the second current source of the first fixed current separate, guarantee the 9th of bias voltage generating circuit
The minimum drain terminal electric current of metal-oxide-semiconductor M9 is greater than 0, to prevent bias voltage to be reduced to 0.
As one embodiment of the present invention, the envelope detected circuit include the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2,
Third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, first capacitor C1, the second capacitor C2, third capacitor C3, first resistor R1, second resistance
R2,3rd resistor R3；
The bias-voltage generating circuit includes the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor
M9, the first current source Ib1, the second current source Ib2；
The second end of the second capacitor C2 is separately connected the grid of the first end of 3rd resistor R3, the second metal-oxide-semiconductor M2, the
The second end of three capacitor C3 is separately connected the grid of the first end of second resistance R2, the first metal-oxide-semiconductor M1, and the second of 3rd resistor R3
The second end of end connection second resistance R2；
The drain electrode of the first metal-oxide-semiconductor M1 is separately connected the drain electrode of the second metal-oxide-semiconductor M2, the drain electrode of third metal-oxide-semiconductor M3, first
The first end of resistance R1；The source electrode of first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 source electrode be grounded respectively；
The source electrode of the third metal-oxide-semiconductor is separately connected the source electrode of the 4th metal-oxide-semiconductor M4, the first current source Ib1First end,
Two current source Ib2First end；
The second end of the first resistor R1 is separately connected the grid of the first end of first capacitor C1, the 4th metal-oxide-semiconductor M4；The
The second end of one capacitor C1 is grounded；
The drain electrode of the 4th metal-oxide-semiconductor M4 is separately connected the drain electrode of the 5th metal-oxide-semiconductor, grid, the 6th MOS of the 5th metal-oxide-semiconductor
The grid of pipe M6；The source electrode of 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor M6 are grounded respectively；
The first current source Ib1Second end be separately connected the source electrode of the drain electrode of the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7；
Second current source Ib2Second end connect the 8th metal-oxide-semiconductor M8 source electrode；
The grid of the 7th metal-oxide-semiconductor M7 connects the grid of the 8th metal-oxide-semiconductor M8；The drain electrode of 7th metal-oxide-semiconductor M7 is separately connected
The drain electrode of 8th metal-oxide-semiconductor M8, the drain electrode of the grid, the 9th metal-oxide-semiconductor M9 of the 9th metal-oxide-semiconductor M9；9th metal-oxide-semiconductor M9 source electrode ground connection.
As one embodiment of the present invention, bias voltage V is setpbWith the threshold of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2
Threshold voltage is close, then exports electric current IpIt is approximately:
Wherein A is input signal amplitude, ω0For input signal angular frequency, K1,2With technique and the first metal-oxide-semiconductor M1, second
The breadth length ratio of metal-oxide-semiconductor M2 is related；
After this electric current is by the current mirror with low-pass filtering, high fdrequency component is filtered out, obtained electric current IpdIt is approximately
Fixed bias current Ib1With IpdSubtract each other, then with small fixed bias current Ib2Bias voltage is poured into after addition generates crystalline substance
Body pipe M9 generates bias voltage Vbias；Ib2It is separated with total bank tube and current subtraction circuit, to limit VbiasMinimum avoids M9's
Drain terminal electric current is reduced to 0, injures the peak power output of PA；Therefore the drain terminal electric current of the 9th metal-oxide-semiconductor M9 is
Exporting bias voltage is
Wherein K9It is related to the breadth length ratio of technique and the 9th metal-oxide-semiconductor M9, Vth9For the threshold voltage of the 9th metal-oxide-semiconductor M9；
With the increase of input signal amplitude, the electric current for reaching the 9th metal-oxide-semiconductor M9 of offset is smaller and smaller, so that output
Bias voltage VbiasAlso it is gradually reduced, until reaching a stationary value.
A kind of feed forward type amplitude linearity method of depth AB power-like amplifier, described method includes following steps:
Envelope detector exports the electric current for being proportional to input signal envelope square；
The electric current comprising envelope information of envelope detected circuit output is subtracted, from a fixed current to generate and input letter
The bias current of number amplitude negative correlation, is then converted into the bias voltage of CMOS radio-frequency power amplifier, the bias voltage with
Input signal amplitude is increased and is reduced；So as to reduce bring gain reduction with CMOS radio-frequency power amplifier PA bias voltage
Gain caused by CMOS radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region is offset to increase.
As one embodiment of the present invention, described method includes following steps:
Set bias voltage VpbIt is close with the threshold voltage of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, then export electric current IpClosely
Seemingly are as follows:
Wherein A is input signal amplitude, ω0For input signal angular frequency, K1,2With technique and the first metal-oxide-semiconductor M1, second
The breadth length ratio of metal-oxide-semiconductor M2 is related；
After this electric current is by the current mirror with low-pass filtering, high fdrequency component is filtered out, obtained electric current IpdIt is approximately
Fixed bias current Ib1With IpdSubtract each other, then with small fixed bias current Ib2Bias voltage is poured into after addition generates the
Nine metal-oxide-semiconductor M9 generate bias voltage Vbias；Ib2It is separated with total bank tube and current subtraction circuit, to limit VbiasMinimum avoids
The drain terminal electric current of 9th metal-oxide-semiconductor M9 is reduced to 0, injures the peak power output of PA；Therefore the drain terminal electric current of the 9th metal-oxide-semiconductor M9 are as follows:
Export bias voltage are as follows:
Wherein K9It is related to the breadth length ratio of technique and the 9th metal-oxide-semiconductor M9, Vth9For the threshold voltage of the 9th metal-oxide-semiconductor M9.
With the increase of input signal amplitude, the electric current for reaching the 9th metal-oxide-semiconductor M9 of offset is smaller and smaller, so that output
Bias voltage VbiasAlso it is gradually reduced, until reaching a stationary value.
The beneficial effects of the present invention are: the feed forward type amplitude linearity side of depth AB power-like amplifier proposed by the present invention
The linearisation of the amplitude gain of the PA under biasing to deep AB class may be implemented in method and circuit, and reaching reduces power consumption while keeping PA
Linear purpose.Circuit structure of the present invention is simple, and design complexities are lower, without the concern for the stability etc. of circuit under big signal
Problem, reliable performance, obtained result are sufficiently linear.
Detailed description of the invention
Fig. 1 (a) is PA power tube V-I characteristic schematic diagram.
Fig. 1 (b) is input voltage VinCharacteristic schematic diagram.
Fig. 1 (c) is output electric current IoutCharacteristic schematic diagram.
Fig. 2 is that fundamental frequency signal gain and input range relation schematic diagram (dotted line: do not consider that the fundamental frequency signal of voltage clipping increases
Solid line: benefit and input range relationship considers the fundamental frequency signal gain and input range relationship of voltage clipping).
Fig. 3 is the structural block diagram of digital pre-distortion linearization technology.
Fig. 4 is the structural block diagram of envelope feedback linearization technique.
Fig. 5 is the structural block diagram of the feedforward linearized technology of envelope.
Fig. 6 is the circuit diagram of the feed forward type amplitude linearity circuit of depth AB power-like amplifier.
Fig. 7 (a) is the relation schematic diagram (dotted line: the fundamental frequency under fixed bias voltage of fundamental frequency signal gain and input range
The relationship of signal gain and input range, solid line: the fundamental frequency signal gain and input obtained using envelope feed forward type bias voltage
The relationship of amplitude).
Fig. 7 (b) is the relationship of bias voltage and PA input terminal voltage and input voltage amplitude
Specific embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
Embodiment one
Referring to Fig. 5, Fig. 5 discloses feed forward type linear technology；The bias voltage adjustment technology of feed forward type can improve A class
Or shallow class ab ammplifier is because output soft limiting or transistor part enter the decline of gain caused by sub-threshold region.As shown in figure 5,
One envelope detector is used to detect the amplitude of input signal, while exporting one and the positively related bias voltage of input range,
When PA input signal amplitude increases, bias voltage is increased, and the PA power tube that can alleviate shallow AB class biasing enters sub-threshold region
Degree, thus the linearity of increase rate gain.
Referring to Fig. 6, present invention discloses a kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, it is described
Feed forward type amplitude linearity circuit includes: envelope detected circuit, bias-voltage generating circuit.
Envelope detected circuit is proportional to the electric current of input signal envelope square to export.Bias-voltage generating circuit to
The electric current comprising envelope information of envelope detected circuit output is subtracted from a fixed current, it is negative with input signal amplitude to generate
Relevant bias current, is then converted into bias voltage；So as to be put with the reduction bring CMOS radio-frequency power of bias voltage
Big device PA gain reduction offsets gain caused by CMOS radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region
It increases.
In certain embodiments of the present invention, the envelope detected circuit includes: that square circuit, high fdrequency component filter out
Circuit, the high fdrequency component filtering circuit connect square circuit.The input of the square circuit is voltage, is exported as direct ratio
In the electric current of input voltage square.The high fdrequency component filtering circuit filters out height to the electric current for exporting the square circuit
Frequency component, obtained output electric current are proportional to square of input signal amplitude.
In the present embodiment, envelope detected circuit includes M1~4 and C1~3 in Fig. 6, R1~3, core be a M1~
The squarer of 2 compositions, input are voltage, export to be proportional to the electric current of input voltage square, filter out high frequency by R1 and C1
Component, obtained output electric current are proportional to square of input signal amplitude.
In certain embodiments of the present invention, the bias-voltage generating circuit includes: current mirroring circuit, the first electric current
Source, bias voltage generating circuit.
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope of envelope detected circuit output
Information current mirror image is Ipd, IpdIncrease with the increase of input signal amplitude.
First current source is to generate the first fixed current Ib1, the first current source connection current mirroring circuit.
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source, and bias voltage generating circuit is used
To receive the data of current mirroring circuit, the first current source, by the first fixed current I of the first current source generationb1Subtract current mirror electricity
The mirror image I of the envelope information electric current of road outputpd, obtained electric current reduces with the increase of input signal amplitude, generate with
The increase of input signal amplitude and reduced bias voltage.
The bias-voltage generating circuit can also include the second current source, biased electrical voltage protection circuit；Bias voltage is protected
Protection circuit is separately connected the first current source, the second current source, bias voltage generating circuit.Second current source is to generate
Two fixed current Ib2, the first fixed current I that biased electrical voltage protection circuit generates the first current sourceb1It is raw with the second current source
At the second fixed current Ib2It separates, guarantees that the minimum drain terminal electric current of the 9th metal-oxide-semiconductor M9 of bias voltage generating circuit is greater than 0,
To prevent bias voltage to be reduced to 0.
In the present embodiment, bias-voltage generating circuit includes M5~9 and two current source Ib1、Ib2, effect is to examine envelope
The electric current comprising envelope information of slowdown monitoring circuit output is converted to bias voltage.Wherein M5, M6 are current mirrors, by envelope detected circuit
The envelope information current mirror of output is Ipd, IpdIncrease with the increase of input signal amplitude, it and fixed current Ib1Phase
Subtract, obtained electric current reduces with the increase of input signal amplitude, pours into the M9 of diode connection to generate as input is believed
The increase of number amplitude and reduced bias voltage.Ib2It is separated with cascode pipe M7,8 with above-mentioned electric current, guarantees the minimum drain terminal of M9
Electric current is greater than 0, to prevent bias voltage to be reduced to 0.
Specifically, the envelope detected circuit includes the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th
Metal-oxide-semiconductor M4, first capacitor C1, the second capacitor C2, third capacitor C3, first resistor R1, second resistance R2,3rd resistor R3.
The bias-voltage generating circuit includes the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor
M9, the first current source Ib1, the second current source Ib2。
The second end of the second capacitor C2 is separately connected the grid of the first end of 3rd resistor R3, the second metal-oxide-semiconductor M2, the
The second end of three capacitor C3 is separately connected the grid of the first end of second resistance R2, the first metal-oxide-semiconductor M1, and the second of 3rd resistor R3
The second end of end connection second resistance R2.
The drain electrode of the first metal-oxide-semiconductor M1 is separately connected the drain electrode of the second metal-oxide-semiconductor M2, the drain electrode of third metal-oxide-semiconductor M3, first
The first end of resistance R1；The source electrode of first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 source electrode be grounded respectively.
The source electrode of the third metal-oxide-semiconductor is separately connected the source electrode of the 4th metal-oxide-semiconductor M4, the first current source Ib1First end,
Two current source Ib2First end.
The second end of the first resistor R1 is separately connected the grid of the first end of first capacitor C1, the 4th metal-oxide-semiconductor M4；The
The second end of one capacitor C1 is grounded.
The drain electrode of the 4th metal-oxide-semiconductor M4 is separately connected the drain electrode of the 5th metal-oxide-semiconductor, grid, the 6th MOS of the 5th metal-oxide-semiconductor
The grid of pipe M6；The source electrode of 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor M6 are grounded respectively.
The first current source Ib1Second end be separately connected the source electrode of the drain electrode of the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7；
Second current source Ib2Second end connect the 8th metal-oxide-semiconductor M8 source electrode；
The grid of the 7th metal-oxide-semiconductor M7 connects the grid of the 8th metal-oxide-semiconductor M8；The drain electrode of 7th metal-oxide-semiconductor M7 is separately connected
The drain electrode of 8th metal-oxide-semiconductor M8, the drain electrode of the grid, the 9th metal-oxide-semiconductor M9 of the 9th metal-oxide-semiconductor M9；9th metal-oxide-semiconductor M9 source electrode ground connection.
For the PA of deep AB class biasing, amplitude gain is increased with the raising of input power, therefore the present invention proposes one kind
PA bias voltage automatic circuit (and feed forward type amplitude linearity circuit of depth AB power-like amplifier), can be according to input
The bias voltage of power opposite direction adjust automatically PA, actively reduces PA gain, to mitigate the amplitude gain of depth AB class PA significantly
It is non-linear.
As shown in figure 5, the principle of the present invention is the envelope detected circuit control PA by detecting amplitude input radio frequency signal
Bias voltage, generate one as input signal amplitude increases and the dull PA bias voltage reduced, utilize biased electrical pressure drop
PA power gain caused by low reduces to offset the increase of PA power gain caused by the class of depth AB shown in Fig. 2 biases.Shown in Fig. 6
It is the schematic diagram of envelope detected and bias-voltage generating circuit, wherein the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 form envelope detected
Circuit, it is assumed that bias voltage VpbIt is close with the threshold voltage of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, then export electric current IpIt can be close
Seemingly are as follows:
Wherein A is input signal amplitude, ω0For input signal angular frequency, K1,2With technique and the first metal-oxide-semiconductor M1, second
The breadth length ratio of metal-oxide-semiconductor M2 is related.
After this electric current is by the current mirror with low-pass filtering, high fdrequency component is filtered out, obtained electric current IpdIt is approximately:
Fixed bias current Ib1With IpdSubtract each other, then with small fixed bias current Ib2Bias voltage is poured into after addition generates crystalline substance
Body pipe M9 generates bias voltage Vbias。Ib2It is separated with total bank tube and current subtraction circuit, to limit VbiasMinimum avoids M9's
Drain terminal electric current is reduced to 0, injures the peak power output of PA.Therefore M9 drain terminal electric current is
Exporting bias voltage is
Wherein K9It is related to the breadth length ratio of technique and M9, Vth9For the threshold voltage of M9.
It can be seen that the electric current for reaching offset M9 is smaller and smaller with the increase of input signal amplitude, so that output
Bias voltage VbiasAlso it is gradually reduced, until reaching a stationary value.
Shown in the situation of change such as Fig. 7 (b) of the PA input biasing that the method obtains with input range, with input power
Increase, the discharge current I that envelope detected circuit generatespdAlso it increases with it, bias voltage is from initial Ib1And Ib2It is fully injected into M9 production
Raw Vb0It is gradually reduced, works as IpdIt increases to and is equal to Ib1When, VbiasCompletely by Ib2It generates, at this time VbiasReach minimum Vbmin.By
The PA power gain that this structure obtains is as shown in Fig. 7 (a) block curve, it can be seen that it is more inclined than the input that dashed curve indicates
It sets and is fixed on Vb0When power gain it is more flat, gain is upwarped caused by increasing with input range and is substantially reduced, it ensure that
Good amplitude gain characteristic of the PA under the biasing of deep AB class.
Embodiment two
The present invention discloses a kind of feed forward type amplitude linearity method of depth AB power-like amplifier, and the method includes as follows
Step: being converted to CMOS radio-frequency power amplifier PA bias voltage for input signal envelope detector output signal, allows biased electrical
Pressure is reduced as input signal amplitude increases, to reduce bring gain with CMOS radio-frequency power amplifier PA bias voltage
It reduces and offsets gain raising caused by CMOS radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region, reach line
Property amplitude gain.
The present invention also discloses a kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, the feed forward type amplitude
Linearizer includes: bias voltage conversion circuit, bias voltage control circuit.
Bias voltage conversion circuit is put input signal envelope detector output signal is converted to CMOS radio-frequency power
Big device PA bias voltage；
Bias voltage control circuit, to the bias voltage that allows the bias voltage conversion circuit to be transformed into as input is believed
Number amplitude is increased and is reduced, to reduce bring gain reduction counteracting CMOS with CMOS radio-frequency power amplifier PA bias voltage
Gain increases caused by radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region, reaches linearisation amplitude gain
Purpose.
Embodiment three
The present invention discloses a kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, the feed forward type magnitude line
Property circuit includes bias-voltage generating circuit.Bias-voltage generating circuit from a fixed current to subtract envelope detected electricity
The electric current comprising envelope information of road output is then converted into partially with generating the bias current with input signal amplitude negative correlation
Set voltage；So as to offset CMOS radio frequency function with the reduction bring CMOS radio-frequency power amplifier PA gain reduction of bias voltage
Gain increases caused by rate amplifier PA transistor enters saturation region from sub-threshold region.
The bias-voltage generating circuit includes: bias current control circuit, bias voltage conversion circuit.
Bias current control circuit, to the export envelope detector and directly proportional electric current of input signal amplitude square
From a fixed current Ib1In subtract, with generate and input signal amplitude negative correlation bias current, thus with the drop of bias voltage
Low bring CMOS radio-frequency power amplifier PA gain reduction offsets CMOS radio-frequency power amplifier PA transistor from sub-threshold region
Gain increases caused by into saturation region, achievees the purpose that linearize amplitude gain.
Bias voltage conversion circuit, to the biased electrical with signal amplitude negative correlation for generating bias current control circuit
Circulation is changed to the bias voltage of CMOS radio-frequency power amplifier PA.
The bias-voltage generating circuit may include: current mirroring circuit, the first current source Ib1, bias voltage generate electricity
Road.
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope of envelope detected circuit output
Information current mirror image is Ipd, IpdIncrease with the increase of input signal amplitude.
First current source connects current mirroring circuit to generate the first fixed current, the first current source.
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source, and bias voltage generating circuit is used
To receive the data of current mirroring circuit, the first current source, by the powered down current mirror circuit of the first fixed current of the first current source generation
The mirror image I of the envelope information electric current of outputpd, obtained electric current reduces with the increase of input signal amplitude, generates with defeated
Enter the increase of signal amplitude and reduced bias voltage.
In addition, the bias-voltage generating circuit can also include the second current source Ib2, biased electrical voltage protection circuit；Biasing
Voltage protection circuit is separately connected the first current source, the second current source, bias voltage generating circuit.
Second current source generates the first current source to generate the second fixed current, biased electrical voltage protection circuit
The second fixed current that first fixed current is generated with the second current source separates, and guarantees the 9th MOS of bias voltage generating circuit
The minimum drain terminal electric current of pipe M9 is greater than 0, to prevent bias voltage to be reduced to 0.
In conclusion the feed forward type amplitude linearity method and circuit of depth AB power-like amplifier proposed by the present invention, it can
To realize the linearisation of the amplitude gain to the PA under the biasing of deep AB class, achievees the purpose that reduce power consumption while keeping PA linear.
Circuit structure of the present invention is simple, and design complexities are lower, without the concern for the problems such as the stability of circuit, performance can under big signal
It leans on, obtained result is sufficiently linear.
Description and application of the invention herein are illustrative, is not wishing to limit the scope of the invention to above-described embodiment
In.The deformation and change of embodiments disclosed herein are possible, the realities for those skilled in the art
The replacement and equivalent various parts for applying example are well known.It should be appreciated by the person skilled in the art that not departing from the present invention
Spirit or essential characteristics in the case where, the present invention can in other forms, structure, arrangement, ratio, and with other components,
Material and component are realized.Without departing from the scope and spirit of the present invention, can to embodiments disclosed herein into
The other deformations of row and change.
Claims (12)
1. a kind of feed forward type amplitude linearity circuit of depth AB power-like amplifier, which is characterized in that the feed forward type magnitude line
Property circuit includes:
Bias-voltage generating circuit subtracts the electric current comprising envelope information of envelope detected circuit output from a fixed current,
To generate the bias current with input signal amplitude negative correlation, it is then converted into bias voltage；So as to use the drop of bias voltage
Low bring CMOS radio-frequency power amplifier PA gain reduction offsets CMOS radio-frequency power amplifier PA transistor from sub-threshold region
Gain increases caused by into saturation region.
2. feed forward type amplitude linearity circuit according to claim 1, it is characterised in that:
The bias-voltage generating circuit includes:
Bias current control circuit, to the export envelope detector and directly proportional electric current of input signal amplitude square from one
Fixed current Ib1In subtract, with generate and input signal amplitude negative correlation bias current, thus with the reduction band of bias voltage
The CMOS radio-frequency power amplifier PA gain reduction come is offset CMOS radio-frequency power amplifier PA transistor and is entered from sub-threshold region
Gain increases caused by saturation region, achievees the purpose that linearize amplitude gain；
Bias voltage conversion circuit, to the biased electrical circulation with signal amplitude negative correlation for generating bias current control circuit
It is changed to the bias voltage of CMOS radio-frequency power amplifier PA.
3. feed forward type amplitude linearity circuit according to claim 1, it is characterised in that:
The bias-voltage generating circuit includes: current mirroring circuit, the first current source Ib1, bias voltage generating circuit；
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope information of envelope detected circuit output
Current mirror is Ipd, IpdIncrease with the increase of input signal amplitude；
First current source connects current mirroring circuit to generate the first fixed current, the first current source；
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source, and bias voltage generating circuit is to connect
The data for receiving current mirroring circuit, the first current source, the powered down current mirror circuit of the first fixed current that the first current source is generated export
Envelope information electric current mirror image Ipd, obtained electric current reduces with the increase of input signal amplitude, generates as input is believed
The increase of number amplitude and reduced bias voltage.
4. feed forward type amplitude linearity circuit according to claim 3, it is characterised in that:
The bias-voltage generating circuit further includes the second current source Ib2, biased electrical voltage protection circuit；Biased electrical voltage protection circuit
It is separately connected the first current source, the second current source, bias voltage generating circuit；
Second current source to generate the second fixed current, biased electrical voltage protection circuit the first current source is generated first
The second fixed current that fixed current is generated with the second current source separates, and guarantees the 9th metal-oxide-semiconductor M9 of bias voltage generating circuit
Minimum drain terminal electric current be greater than 0, to prevent bias voltage to be reduced to 0.
5. feed forward type amplitude linearity circuit according to claim 1, it is characterised in that:
The feed forward type amplitude linearity circuit further includes envelope detected circuit, is proportional to input signal envelope square to export
Electric current.
6. feed forward type amplitude linearity circuit according to claim 5, it is characterised in that:
The envelope detected circuit includes: square circuit, high fdrequency component filtering circuit, the high fdrequency component filtering circuit connection
Square circuit；
The input of the square circuit is voltage, is exported to be proportional to the electric current of input voltage square；
The high fdrequency component filtering circuit filters out high fdrequency component to the electric current for exporting the square circuit, obtained output
Electric current is proportional to square of input signal amplitude.
7. PA bias voltage automatic circuit according to claim 1, it is characterised in that:
The bias-voltage generating circuit includes: current mirroring circuit, the first current source Ib1, bias voltage generating circuit；
The current mirroring circuit connects envelope detected circuit, and current mirroring circuit is to by the envelope information of envelope detected circuit output
Current mirror is Ipd, IpdIncrease with the increase of input signal amplitude；
The first current source Ib1To generate the first fixed current, the first current source Ib1Connect current mirroring circuit；
The bias voltage generating circuit is separately connected current mirroring circuit, the first current source, and bias voltage generating circuit is to connect
The data for receiving current mirroring circuit, the first current source, the powered down current mirror circuit of the first fixed current that the first current source is generated export
Envelope information electric current mirror image Ipd, obtained electric current reduces with the increase of input signal amplitude, generates as input is believed
The increase of number amplitude and reduced bias voltage.
8. PA bias voltage automatic circuit according to claim 7, it is characterised in that:
The bias-voltage generating circuit further includes the second current source Ib2, biased electrical voltage protection circuit；Biased electrical voltage protection circuit
It is separately connected the first current source, the second current source Ib2, bias voltage generating circuit；
The second current source Ib2To generate the second fixed current, biased electrical voltage protection circuit the first current source is generated
The second fixed current that one fixed current is generated with the second current source separates, and guarantees the 9th metal-oxide-semiconductor of bias voltage generating circuit
The minimum drain terminal electric current of M9 is greater than 0, to prevent bias voltage to be reduced to 0.
9. PA bias voltage automatic circuit according to claim 1, it is characterised in that:
The envelope detected circuit includes the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, first
Capacitor C1, the second capacitor C2, third capacitor C3, first resistor R1, second resistance R2,3rd resistor R3；
The bias-voltage generating circuit include the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9,
First current source Ib1, the second current source Ib2；
The second end of the second capacitor C2 is separately connected the grid of the first end of 3rd resistor R3, the second metal-oxide-semiconductor M2, third electricity
The second end for holding C3 is separately connected the grid of the first end of second resistance R2, the first metal-oxide-semiconductor M1, and the second end of 3rd resistor R3 connects
Connect the second end of second resistance R2；
The drain electrode of the first metal-oxide-semiconductor M1 is separately connected the drain electrode of the second metal-oxide-semiconductor M2, the drain electrode of third metal-oxide-semiconductor M3, first resistor
The first end of R1；The source electrode of first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 source electrode be grounded respectively；
The source electrode of the third metal-oxide-semiconductor is separately connected the source electrode of the 4th metal-oxide-semiconductor M4, the first current source Ib1First end, second electricity
Stream source Ib2First end；
The second end of the first resistor R1 is separately connected the grid of the first end of first capacitor C1, the 4th metal-oxide-semiconductor M4；First electricity
Hold the second end ground connection of C1；
The drain electrode of the 4th metal-oxide-semiconductor M4 is separately connected the drain electrode of the 5th metal-oxide-semiconductor, grid, the 6th metal-oxide-semiconductor M6 of the 5th metal-oxide-semiconductor
Grid；The source electrode of 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor M6 are grounded respectively；
The first current source Ib1Second end be separately connected the source electrode of the drain electrode of the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7；Second
Current source Ib2Second end connect the 8th metal-oxide-semiconductor M8 source electrode；
The grid of the 7th metal-oxide-semiconductor M7 connects the grid of the 8th metal-oxide-semiconductor M8；The drain electrode of 7th metal-oxide-semiconductor M7 is separately connected the 8th
The drain electrode of metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9 grid, the 9th metal-oxide-semiconductor M9 drain electrode；9th metal-oxide-semiconductor M9 source electrode ground connection.
10. PA bias voltage automatic circuit according to claim 1, it is characterised in that:
Set bias voltage VpbIt is close with the threshold voltage of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, then export electric current IpIt is approximately:
Wherein A is input signal amplitude, ω0For input signal angular frequency, K1,2With technique and the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2
Breadth length ratio it is related；
After this electric current is by the current mirror with low-pass filtering, high fdrequency component is filtered out, obtained electric current IpdIt is approximately
Fixed bias current Ib1With IpdSubtract each other, then with small fixed bias current Ib2Bias voltage is poured into after addition generates transistor
M9 generates bias voltage Vbias；Ib2It is separated with total bank tube and current subtraction circuit, to limit VbiasMinimum avoids the drain terminal of M9
Electric current is reduced to 0, injures the peak power output of PA；Therefore the drain terminal electric current of the 9th metal-oxide-semiconductor M9 is
Exporting bias voltage is
Wherein K9It is related to the breadth length ratio of technique and the 9th metal-oxide-semiconductor M9, Vth9For the threshold voltage of the 9th metal-oxide-semiconductor M9；
With the increase of input signal amplitude, the electric current for reaching the 9th metal-oxide-semiconductor M9 of offset is smaller and smaller, so that the biasing of output
Voltage VbiasAlso it is gradually reduced, until reaching a stationary value.
11. a kind of feed forward type amplitude linearity method of depth AB power-like amplifier, which is characterized in that the method includes as follows
Step:
Envelope detector exports the electric current for being proportional to input signal envelope square；
The electric current comprising envelope information of envelope detected circuit output is subtracted, from a fixed current to generate and input signal width
Negatively correlated bias current is spent, is then converted into the bias voltage of CMOS radio-frequency power amplifier, the bias voltage is with input
Signal amplitude is increased and is reduced；It is offset so as to reduce bring gain reduction with CMOS radio-frequency power amplifier PA bias voltage
Gain increases caused by CMOS radio-frequency power amplifier PA transistor enters saturation region from sub-threshold region.
12. the feed forward type amplitude linearity method of depth AB power-like amplifier according to claim 11, it is characterised in that:
Described method includes following steps:
Set bias voltage VpbIt is close with the threshold voltage of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, then export electric current IpIt is approximately:
Wherein, A is input signal amplitude, ω0For input signal angular frequency, K1,2With technique and the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor
The breadth length ratio of M2 is related；
After this electric current is by the current mirror with low-pass filtering, high fdrequency component is filtered out, obtained electric current IpdIt is approximately
Fixed bias current Ib1With IpdSubtract each other, then with small fixed bias current Ib2Bias voltage is poured into after addition generates the 9th MOS
Pipe M9 generates bias voltage Vbias；Ib2It is separated with total bank tube and current subtraction circuit, to limit VbiasMinimum avoids the 9th
The drain terminal electric current of metal-oxide-semiconductor M9 is reduced to 0, injures the peak power output of PA；Therefore the drain terminal electric current of the 9th metal-oxide-semiconductor M9 are as follows:
Export bias voltage are as follows:
Wherein K9It is related to the breadth length ratio of technique and the 9th metal-oxide-semiconductor M9, Vth9For the threshold voltage of the 9th metal-oxide-semiconductor M9.
With the increase of input signal amplitude, the electric current for reaching the 9th metal-oxide-semiconductor M9 of offset is smaller and smaller, so that the biasing of output
Voltage VbiasAlso it is gradually reduced, until reaching a stationary value.
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