CN109300990B - Thin film transistor, preparation method, array substrate, display panel and display device - Google Patents
Thin film transistor, preparation method, array substrate, display panel and display device Download PDFInfo
- Publication number
- CN109300990B CN109300990B CN201811150939.0A CN201811150939A CN109300990B CN 109300990 B CN109300990 B CN 109300990B CN 201811150939 A CN201811150939 A CN 201811150939A CN 109300990 B CN109300990 B CN 109300990B
- Authority
- CN
- China
- Prior art keywords
- channel region
- active layer
- thin film
- film transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 239000010409 thin film Substances 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 122
- 239000011229 interlayer Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses a thin film transistor, a preparation method of the thin film transistor, an array substrate, a display panel and a display device, relates to the technical field of display, and aims to solve the problem of short channel effect of the thin film transistor with a top gate structure. The thin film transistor comprises a substrate base plate, an active layer, a grid insulating layer and a grid electrode, wherein the active layer covers the substrate base plate, the grid insulating layer covers the active layer, the grid electrode covers the grid insulating layer, the active layer comprises a channel region and conductor regions which are located on two sides of the channel region and connected with the channel region, a placing portion is arranged on the substrate base plate and used for placing the channel region, and therefore a height difference is formed between the channel region and the conductor regions located on two sides of the channel region. The invention can be used in liquid crystal display panels and OLED display panels.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a preparation method of the thin film transistor, an array substrate, a display panel and a display device.
Background
A Thin Film Transistor (TFT) with a top gate structure is a Thin Film Transistor structure with a gate electrode above a channel region, and because the channel region is generally protected by light irradiation using the gate electrode, the electrical performance of the Thin Film Transistor with the top gate structure is generally better than that of the Thin Film Transistor with a bottom gate structure.
As shown in fig. 1, a thin film transistor in the related art includes a substrate 01, an active layer 02 covering the substrate 01, a gate insulating layer 03 covering the active layer 02, and a gate 04 covering the gate insulating layer 03, wherein the active layer 02 includes a channel region 021 and conductive regions 022 located at two sides of the channel region 021 and connected to the channel region 021.
In order to form a thin film transistor with a top gate structure, when the gate insulating layer 03 between the active layer 02 and the gate electrode 04 is formed through a patterning process, the gate insulating layer 03 covering the conductive region 022 in the active layer 02 is usually completely etched away, the region 022 to be conductive is exposed, and the exposed region 022 to be conductive is processed through a conductive process. After the conductor process is performed on the region to be conductor 022, an interlayer dielectric layer (ILD) is formed.
However, after the conductive treatment, the active layer 02 in the conventional top gate structure may be further conductive due to the high temperature and plasma bombardment of the subsequent processes, such as forming an interlayer dielectric layer, which is formed on the surface of the conductive region 022 and contacts the conductive region 022. Moreover, the interlayer dielectric layer is formed by high temperature and Plasma bombardment processes, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the Deposition temperature is about 300 ℃, and a large amount of Plasma is contained in the PECVD chamber, and the Plasma bombardment in the active layer 02 causes the further conductor formation of the originally conductive active layer 02, thereby causing the width of the channel region 021 of the thin film transistorReducing and generating short channel effect. The short channel effect can cause the threshold voltage V of the thin film transistorthThe negative drift is severe, thereby affecting the stability of the thin film transistor.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, a preparation method thereof, an array substrate, a display panel and a display device, and aims to solve the problem of short channel effect of the thin film transistor with a top gate structure.
In order to achieve the above object, in a first aspect, an embodiment of the present invention provides a thin film transistor, which includes a substrate, an active layer covering the substrate, a gate insulating layer covering the active layer, and a gate electrode covering the gate insulating layer, where the active layer includes a channel region and conductive regions located on two sides of the channel region and both connected to the channel region, and a placing portion is disposed on the substrate and used for placing the channel region, so that a height difference is formed between the channel region and the conductive regions located on two sides of the channel region.
The buffer layer covers the substrate base plate; the placing part comprises a boss arranged on the buffer layer, the active layer covers the buffer layer, and the channel region covers the boss.
The buffer layer covers the substrate base plate; the placing part comprises a groove arranged on the buffer layer, the active layer covers the buffer layer, and the channel region covers the groove bottom of the groove.
Further, the gate insulating layer covers a surface of the channel region.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor as described in the first aspect, including the following steps: providing a substrate base plate; forming a placing portion on the substrate base plate; forming an active layer on the substrate and having a portion of the active layer disposed on the placing portion to form a channel region; forming a gate insulating layer on the active layer; removing the gate insulating layer covered on the regions on two sides of the channel region in the active layer; and processing regions of the active layer, which are positioned on two sides of the channel region, through a conductor processing process to form conductor regions.
Further, a placing portion is formed on the substrate base plate; forming an active layer on the substrate and having a portion of a region of the active layer disposed on the placing portion to form a channel region, including: forming a buffer layer on the substrate base plate; etching the buffer layer to form a boss; and forming the active layer on the buffer layer, and covering a part of the active layer on the boss to form the channel region.
Further, a placing portion is formed on the substrate base plate; forming an active layer on the substrate and having a portion of a region of the active layer disposed on the placing portion to form a channel region, including: forming a buffer layer on the substrate base plate; etching to form a groove on the buffer layer;
and forming the active layer on the buffer layer, and covering a part of region of the active layer on the groove bottom of the groove to form the channel region.
In a third aspect, an embodiment of the present invention provides an array substrate, including the thin film transistor described in the first aspect.
In a fourth aspect, an embodiment of the present invention provides a display panel, including the array substrate described in the third aspect.
In a fifth aspect, an embodiment of the present invention provides a display device, including the display panel described in the fourth aspect.
In the thin film transistor and the manufacturing method thereof, the array substrate, the display panel and the display device provided by the embodiment of the invention, because the substrate is provided with the placing part which is used for placing the channel region so as to ensure that the channel region and the conductor regions positioned at two sides of the channel region have the height difference, thus, the transition region between the channel region and the conductor regions can form a ramp structure due to the height difference, in the subsequent process of the active layer after the conductor processing, such as the deposition of an interlayer dielectric layer, when the active layer is bombarded by plasma, the ramp structure between the channel region and the conductor regions can ensure that the path between the channel region and the conductor regions becomes tortuous, the length of the path is increased, thereby the diffusion of the plasma from the conductor regions to the channel region is hindered, the channel region of the thin film transistor can be prevented from becoming too narrow, and the generation of short channel effect is effectively avoided, the stability of the electrical performance of the thin film transistor is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor in the related art;
FIG. 2 is a schematic structural diagram of a TFT in an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a TFT according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a process for fabricating a thin film transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a process for fabricating a TFT in accordance with another embodiment of the present invention;
FIG. 6 is a flow chart of a process for fabricating a thin film transistor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In a first aspect, an embodiment of the present invention provides a thin film transistor, as shown in fig. 2, including a substrate 1, an active layer 2 covering the substrate 1, a gate insulating layer 3 covering the active layer 2, and a gate 4 covering the gate insulating layer 3, where the active layer 2 includes a channel region 21 and conductive regions 22 located on two sides of the channel region 21 and connected to the channel region 21, and a placing portion 5 is disposed on the substrate 1, and the placing portion 5 is used for placing the channel region 21, so that a height difference exists between the channel region 21 and the conductive regions 22 located on two sides of the channel region 21.
Wherein, the placing part 5 can be directly arranged on the substrate base plate 1; or indirectly disposed on the substrate base plate 1, for example, the placing part 5 may be disposed on a film layer covering the substrate base plate 1; the material of the active layer 2 may be any one of a-IGZO, ZnON, IZTO, a-Si, p-Si, hexathiophene, polythiophene, etc.
In the thin film transistor provided by the embodiment of the present invention, the substrate 1 is provided with the placing portion 5, the placing portion 5 is used for placing the channel region 21, so that a height difference exists between the channel region 21 and the conductive regions 22 located at two sides of the channel region 21, and thus, a transition region between the channel region 21 and the conductive regions 22 forms a ramp structure due to the height difference, so that in a subsequent process of the active layer 2 after the conductive processing, for example, in depositing the interlayer dielectric layer 7, when the active layer 2 is bombarded by plasma, the ramp structure between the channel region 21 and the conductive regions 22 makes a path between the channel region 21 and the conductive regions 22 become tortuous, and increases the length of the path, thereby hindering the diffusion of the plasma from the conductive regions 22 to the channel region 21, further preventing the channel region 21 of the thin film transistor from becoming too narrow, and effectively avoiding the generation of short channel effect, the stability of the electrical performance of the thin film transistor is ensured.
In the above-described embodiment, the structure of the placing section 5 is not exclusive, and for example, the placing section 5 may have the following structure:
as shown in fig. 2, the thin film transistor further includes a buffer layer 8, and the buffer layer 8 covers the substrate 1; the placing part 5 comprises a boss 51 arranged on the buffer layer 8, the active layer 2 covers the buffer layer 6, and the channel region 21 covers the boss 51;
as shown in fig. 3, the placement unit 5 may have the following structure: the placing part 5 comprises a groove 52 formed on the buffer layer 8, the active layer 2 covers the buffer layer 6, and the channel region 21 covers the bottom of the groove 52, wherein the channel region 21 can be partially positioned in the groove 52; or may be entirely located within the recess 52, and is not particularly limited herein;
the placement unit 5 may have the following structure: the placement portion 5 includes a boss 51 or a recess 52 provided directly on the base substrate 1.
Compared with the embodiment that the placing part 5 comprises the boss 51 or the groove 52 directly arranged on the substrate base plate 1, the embodiment that the placing part 5 comprises the boss 51 or the groove 52 arranged on the buffer layer 8 can reduce the forming difficulty of the boss 51 or the groove 52, namely, the placing part 5 is directly formed on the buffer layer 8 by etching, so that the substrate base plate 1 is prevented from being etched, and the integrity of the substrate base plate 1 is ensured; in addition, a buffer layer 8 is arranged between the active layer 2 and the substrate base plate 1, and the buffer layer 8 can prevent impurities in the substrate base plate 1 from diffusing into the active layer 2, so that the impurities are prevented from influencing the electrical performance of the thin film transistor.
To further avoid the generation of short channel effects of the thin film transistor, the gate insulating layer 3 covers the surface of the channel region 21 as shown in fig. 2 and 3. Thus, in the subsequent process of the active layer 2 after the conductor processing, for example, in the deposition of the interlayer dielectric layer 7, when the active layer 2 is bombarded by plasma, the gate insulating layer 3 can protect the channel region 21, so as to prevent the channel region 21 from being bombarded by the plasma to shorten the width of the channel region 21, and further prevent the short channel effect of the thin film transistor.
As shown in fig. 2, the substrate 1 is further covered with a light shielding layer 6(shield), the light shielding layer 6 is disposed in the buffer layer 8, and the light shielding layer 6 is used to prevent external light from irradiating the active layer 2, so as to prevent the active layer 2 from generating photo-generated carriers when being irradiated by light to affect the electrical performance of the thin film transistor.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor as described in the first aspect, including the following steps: as shown in figure 6 of the drawings,
s1, as shown in fig. 4 (a), providing a base substrate 1;
wherein, the substrate base plate 1 can be cleaned to remove the solid particles thereon, so as to avoid causing adverse effect on the subsequent process; the substrate base plate 1 can be a glass substrate base plate 1, a sapphire substrate base plate 1, a silicon substrate base plate 1 and the like;
s2, as shown in fig. 4 (b), forming a placing section 5 on the base board 1; as shown in fig. 4 (c), the active layer 2 is formed on the base substrate 1, and a partial region of the active layer 2 is provided on the placing section 5 to form the channel region 21;
wherein, the active layer 2 formed on the base substrate 1 may be: an active layer thin film is covered on a substrate base plate 1, and then an active layer 2 is formed through a photoetching process;
s3, as shown in fig. 4 (c), forming a gate insulating layer 3 on the active layer 2;
s4, as shown in (c) of fig. 4, removing the gate insulating layer 3 covering the regions of the active layer 2 on both sides of the channel region 21;
wherein the gate insulating layer 3 covering the regions on both sides of the channel region 21 may be removed by dry etching.
S5, as shown in fig. 4 (c), regions of the active layer 2 on both sides of the channel region 21 are processed by a conductor process to form the conductor regions 22.
Wherein, the conductive process treatment may be to implant ions into regions on both sides of the channel region 21 to form the conductive region 22; the treatment of the conductor process may be performed simultaneously with the removal of the gate insulator layer 3 covering the regions on both sides of the channel region 21, for example, when dry etching the gate insulator layer 3 covering the regions on both sides of the channel region 21, a plasma in the dry etching process bombards the regions on both sides of the channel region 21 to form the conductor regions 22.
The technical problems solved and the technical effects achieved by the method for manufacturing a thin film transistor according to the embodiments of the present invention are the same as the technical problems solved and the technical effects achieved by the thin film transistor in the first aspect, and are not described herein again.
In the above method for manufacturing a thin film transistor, the step S2 may include the steps of:
s21, as shown in fig. 4 (a), forming a buffer layer 8 on the base substrate 1;
wherein, before forming the buffer layer 8, the light-shielding layer 6 may be formed on the base substrate 1, and then the buffer layer 8 may be formed to cover the light-shielding layer 6;
s22, as shown in fig. 4 (b), forming a boss 51 by etching on the buffer layer 8;
after the buffer layer 8 is formed, etching away other regions of the buffer layer 8 through a photoetching process, and only keeping the boss 51;
s23, as shown in fig. 4 (c), the active layer 2 is formed on the buffer layer 8, and a partial region of the active layer 2 is overlaid on the mesa 51 to form the channel region 21.
In addition, step S2 may also include the following steps:
s21', as shown in fig. 5 (a), a buffer layer 8 is formed on the base substrate 1;
s22', as shown in fig. 5 (b), forming a groove 52 on the buffer layer 8 by etching;
wherein after the buffer layer 8 is formed, regions of the grooves 52 are then etched away on the buffer layer 8 by a photolithography process, leaving other regions of the buffer layer 8.
S23', as shown in fig. 5 (b), the active layer 2 is formed on the buffer layer 8, and a part of the region of the active layer 2 is made to cover the groove bottom of the groove 52 to form the channel region 21.
Further, step S2 may include the steps of:
s21 DEG, directly forming a boss 51 or a groove 52 on the substrate base plate 1;
s22 °, the active layer 2 is directly formed on the base substrate 1, and a partial region of the active layer 2 is overlaid on the mesa 51 or the groove bottom of the groove 52 to form the channel region 21.
The same or similar features in the embodiments of the method for manufacturing a thin film transistor as those in the embodiments of the device of the thin film transistor may be referred to the description of the embodiments of the device of the thin film transistor, and are not repeated herein.
In a third aspect, an embodiment of the present invention provides an array substrate, including the thin film transistor described in the first aspect.
The array substrate may be an array substrate in a liquid crystal display panel, or an array substrate in an OLED display panel.
In a fourth aspect, an embodiment of the present invention provides a display panel, including the array substrate described in the third aspect.
The display panel may be a liquid crystal display panel, an OLED display panel, or the like.
In a fifth aspect, an embodiment of the present invention provides a display device, including the display panel described in the fourth aspect.
The display device can be a display device comprising the display panel, such as a mobile phone, a tablet computer, a computer monitor, a television and the like.
Technical problems to be solved and technical effects to be achieved by the array substrate, the display panel and the display device provided by the embodiments of the present invention are the same as the technical problems to be solved and the technical effects to be achieved by the thin film transistor in the first aspect, and are not described herein again.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A thin film transistor comprises a substrate base plate, an active layer, a grid insulating layer and a grid, wherein the active layer covers the substrate base plate, the grid insulating layer covers the active layer, the grid covers the grid insulating layer, the active layer comprises a channel region and conductor regions which are positioned on two sides of the channel region and connected with the channel region, and the thin film transistor is characterized in that a placing part is arranged on the substrate base plate and used for placing the channel region, so that a height difference is formed between the channel region and the conductor regions positioned on two sides of the channel region;
the active layer is positioned on the side surface of the channel region and is in contact with or not in contact with the side surface part of the active layer positioned on the conductive region;
the gate insulating layer covers the surface of the channel region, and is in contact with the surface of the conductive region;
the material of the active layer is a-IGZO, ZnON or IZTO.
2. The thin film transistor of claim 1, further comprising a buffer layer overlying the substrate base plate;
the placing part comprises a boss arranged on the buffer layer, the active layer covers the buffer layer, and the channel region covers the boss.
3. The thin film transistor of claim 1, further comprising a buffer layer overlying the substrate base plate;
the placing part comprises a groove arranged on the buffer layer, the active layer covers the buffer layer, and the channel region covers the groove bottom of the groove.
4. A method for manufacturing a thin film transistor according to any one of claims 1 to 3, comprising the steps of:
providing a substrate base plate;
forming a placing portion on the substrate base plate;
forming an active layer on the substrate and having a portion of the active layer disposed on the placing portion to form a channel region;
forming a gate insulating layer on the active layer;
removing the gate insulating layer covered on the regions on two sides of the channel region in the active layer;
and processing regions of the active layer, which are positioned on two sides of the channel region, through a conductor processing process to form conductor regions.
5. The manufacturing method of a thin film transistor according to claim 4, wherein a placing portion is formed on the base substrate; forming an active layer on the substrate and having a portion of a region of the active layer disposed on the placing portion to form a channel region, including:
forming a buffer layer on the substrate base plate;
etching the buffer layer to form a boss;
and forming the active layer on the buffer layer, and covering a part of the active layer on the boss to form the channel region.
6. The manufacturing method of a thin film transistor according to claim 4, wherein a placing portion is formed on the base substrate; forming an active layer on the substrate and having a portion of a region of the active layer disposed on the placing portion to form a channel region, including:
forming a buffer layer on the substrate base plate;
etching to form a groove on the buffer layer;
and forming the active layer on the buffer layer, and covering a part of region of the active layer on the groove bottom of the groove to form the channel region.
7. An array substrate comprising the thin film transistor according to any one of claims 1 to 3.
8. A display panel comprising the array substrate according to claim 7.
9. A display device characterized by comprising the display panel according to claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811150939.0A CN109300990B (en) | 2018-09-29 | 2018-09-29 | Thin film transistor, preparation method, array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811150939.0A CN109300990B (en) | 2018-09-29 | 2018-09-29 | Thin film transistor, preparation method, array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109300990A CN109300990A (en) | 2019-02-01 |
| CN109300990B true CN109300990B (en) | 2022-04-22 |
Family
ID=65161288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811150939.0A Active CN109300990B (en) | 2018-09-29 | 2018-09-29 | Thin film transistor, preparation method, array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109300990B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109860307A (en) | 2019-02-26 | 2019-06-07 | 合肥鑫晟光电科技有限公司 | A kind of transistor and preparation method thereof, display base plate and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070040128A (en) * | 2005-10-11 | 2007-04-16 | 삼성전자주식회사 | Thin film transistor and fabrication method thereof |
| CN100544029C (en) * | 2004-04-28 | 2009-09-23 | 三星移动显示器株式会社 | The display of organic electroluminescence of thin-film transistor and this thin-film transistor of use |
| CN104347727A (en) * | 2013-07-23 | 2015-02-11 | 三星显示有限公司 | Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element |
| CN106125432A (en) * | 2016-08-29 | 2016-11-16 | 武汉华星光电技术有限公司 | Display and display floater thereof |
| CN107527940A (en) * | 2017-08-24 | 2017-12-29 | 京东方科技集团股份有限公司 | Backboard and its manufacture method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7419858B2 (en) * | 2006-08-31 | 2008-09-02 | Sharp Laboratories Of America, Inc. | Recessed-gate thin-film transistor with self-aligned lightly doped drain |
| JP2014212191A (en) * | 2013-04-18 | 2014-11-13 | セイコーエプソン株式会社 | Semiconductor device, electrooptical device, method of manufacturing semiconductor device, method of manufacturing electrooptical device, and electronic equipment |
-
2018
- 2018-09-29 CN CN201811150939.0A patent/CN109300990B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100544029C (en) * | 2004-04-28 | 2009-09-23 | 三星移动显示器株式会社 | The display of organic electroluminescence of thin-film transistor and this thin-film transistor of use |
| KR20070040128A (en) * | 2005-10-11 | 2007-04-16 | 삼성전자주식회사 | Thin film transistor and fabrication method thereof |
| CN104347727A (en) * | 2013-07-23 | 2015-02-11 | 三星显示有限公司 | Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element |
| CN106125432A (en) * | 2016-08-29 | 2016-11-16 | 武汉华星光电技术有限公司 | Display and display floater thereof |
| CN107527940A (en) * | 2017-08-24 | 2017-12-29 | 京东方科技集团股份有限公司 | Backboard and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109300990A (en) | 2019-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109300917B (en) | Array substrate, preparation method thereof and display panel | |
| CN111415948B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| CN107994066B (en) | TFT, manufacturing method, array substrate, display panel and device | |
| US9455324B2 (en) | Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device | |
| KR101530459B1 (en) | Manufacturing method of array substrate, array substrate and display | |
| CN110190031B (en) | Preparation method of thin film transistor substrate | |
| CN111341849B (en) | Display substrate, preparation method thereof and display panel | |
| US10461178B2 (en) | Method for manufacturing array substrate, array substrate and display panel | |
| CN111584509B (en) | Display panel, preparation method thereof and display device | |
| CN104064472A (en) | Thin film transistor, manufacturing method thereof and display device | |
| US9159746B2 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN112002763A (en) | TFT substrate, manufacturing method thereof and display panel | |
| US10332987B2 (en) | Thin film transistor, manufacturing method for array substrate, array substrate and display device | |
| CN112490254B (en) | Array substrate, display panel and preparation method thereof | |
| US9905592B2 (en) | Method for manufacturing TFT, array substrate and display device | |
| US11239331B2 (en) | Thin film transistor substrate and method of fabricating same | |
| CN109920856B (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| US10629633B2 (en) | Array substrate and manufacturing method thereof, display device | |
| CN109300990B (en) | Thin film transistor, preparation method, array substrate, display panel and display device | |
| US9716117B2 (en) | Method for producing a via, a method for producing an array substrate, an array substrate, and a display device | |
| CN109742031B (en) | Thin film transistor, preparation method thereof, array substrate and display device | |
| US10620492B2 (en) | Method for manufacturing array substrate, array substrate and display device | |
| US20210265510A1 (en) | Thin film transistor and manufacturing method thereof, display substrate and display apparatus | |
| KR20160089592A (en) | Method for manufacturing oxide thin film transistor | |
| US10510899B2 (en) | Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |